verilog
This commit is contained in:
commit
ed465dd690
60
a.out
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60
a.out
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@ -0,0 +1,60 @@
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#! /c/Source/iverilog-install/bin/vvp
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:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "C:\iverilog\lib\ivl\system.vpi";
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:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
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:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
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:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
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:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
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S_0000014670375350 .scope module, "hello" "hello" 2 1;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "C";
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.port_info 3 /OUTPUT 1 "D";
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o0000014670376fd8 .functor BUFZ 1, C4<z>; HiZ drive
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o0000014670377008 .functor BUFZ 1, C4<z>; HiZ drive
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L_0000014670326ea0 .functor AND 1, o0000014670376fd8, o0000014670377008, C4<1>, C4<1>;
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L_0000014670327320 .functor XOR 1, o0000014670376fd8, o0000014670377008, C4<0>, C4<0>;
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v00000146703270e0_0 .net "A", 0 0, o0000014670376fd8; 0 drivers
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v0000014670375670_0 .net "B", 0 0, o0000014670377008; 0 drivers
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v0000014670375710_0 .net "C", 0 0, L_0000014670327320; 1 drivers
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v000001467032ee60_0 .net "D", 0 0, L_0000014670326ea0; 1 drivers
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S_00000146703754e0 .scope module, "hello_tb" "hello_tb" 3 1;
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.timescale 0 0;
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v000001467032ef00_0 .var "A", 0 0;
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v000001467032b870_0 .var "B", 0 0;
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.scope S_00000146703754e0;
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T_0 ;
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%vpi_call 3 8 "$dumpfile", "dmp.vcd" {0 0 0};
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%vpi_call 3 9 "$dumpvars" {0 0 0};
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%pushi/vec4 0, 0, 1;
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%store/vec4 v000001467032ef00_0, 0, 1;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v000001467032b870_0, 0, 1;
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%delay 10, 0;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v000001467032ef00_0, 0, 1;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v000001467032b870_0, 0, 1;
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%delay 10, 0;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v000001467032ef00_0, 0, 1;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v000001467032b870_0, 0, 1;
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%delay 10, 0;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v000001467032ef00_0, 0, 1;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v000001467032b870_0, 0, 1;
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%delay 10, 0;
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%vpi_call 3 14 "$finish" {0 0 0};
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%end;
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.thread T_0;
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# The file index is used to find the file name in the following table.
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:file_names 4;
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"N/A";
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"<interactive>";
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"hello.v";
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"hello_tb.v";
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40
dmp.vcd
Normal file
40
dmp.vcd
Normal file
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$date
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Sat Apr 06 17:40:37 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module hello $end
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$var wire 1 ! A $end
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$var wire 1 " B $end
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$var wire 1 # C $end
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$var wire 1 $ D $end
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$upscope $end
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$scope module hello_tb $end
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$var reg 1 % A $end
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$var reg 1 & B $end
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$upscope $end
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$enddefinitions $end
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$comment Show the parameter values. $end
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$dumpall
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$end
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#0
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$dumpvars
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0&
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0%
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x$
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x#
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z"
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z!
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$end
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#10
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1&
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#20
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0&
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1%
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#30
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1&
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#40
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9
hello.v
Normal file
9
hello.v
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module hello(
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input wire A, B,
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output wire C, D
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);
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and(D, A, B);
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xor(C, A, B);
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endmodule
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17
hello_tb.v
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17
hello_tb.v
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module hello_tb();
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reg A;
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reg B;
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wire C, D;
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initial begin
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$dumpfile("dmp.vcd");
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$dumpvars;
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A = 0; B = 0; #10;
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A = 0; B = 1; #10;
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A = 1; B = 0; #10;
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A = 1; B = 1; #10;
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$finish;
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end
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endmodule
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24
lab2/impl/gwsynthesis/lab2.log
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24
lab2/impl/gwsynthesis/lab2.log
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GowinSynthesis start
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Running parser ...
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\BitM.v'
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Compiling module 'BitM'("C:\cygwin64\home\koray\verilog\lab2\src\BitM.v":1)
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NOTE (EX0101) : Current top module is "BitM"
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[5%] Running netlist conversion ...
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Running device independent optimization ...
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[10%] Optimizing Phase 0 completed
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[15%] Optimizing Phase 1 completed
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[25%] Optimizing Phase 2 completed
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Running inference ...
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[30%] Inferring Phase 0 completed
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[40%] Inferring Phase 1 completed
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[50%] Inferring Phase 2 completed
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[55%] Inferring Phase 3 completed
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Running technical mapping ...
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[60%] Tech-Mapping Phase 0 completed
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[65%] Tech-Mapping Phase 1 completed
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[75%] Tech-Mapping Phase 2 completed
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[80%] Tech-Mapping Phase 3 completed
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[90%] Tech-Mapping Phase 4 completed
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[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg" completed
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[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2_syn.rpt.html" completed
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GowinSynthesis finish
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19
lab2/impl/gwsynthesis/lab2.prj
Normal file
19
lab2/impl/gwsynthesis/lab2.prj
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE gowin-synthesis-project>
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<Project>
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<Version>beta</Version>
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<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
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<FileList>
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<File path="C:\cygwin64\home\koray\verilog\lab2\src\BitM.v" type="verilog"/>
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</FileList>
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<OptionList>
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<Option type="disable_insert_pad" value="0"/>
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<Option type="global_freq" value="100.000"/>
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<Option type="looplimit" value="2000"/>
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<Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg"/>
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<Option type="print_all_synthesis_warning" value="0"/>
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<Option type="ram_rw_check" value="0"/>
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<Option type="verilog_language" value="verilog-2001"/>
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<Option type="vhdl_language" value="vhdl-1993"/>
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</OptionList>
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</Project>
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76
lab2/impl/gwsynthesis/lab2.vg
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76
lab2/impl/gwsynthesis/lab2.vg
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//
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//Written by GowinSynthesis
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//Tool Version "V1.9.9.02"
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//Thu Apr 11 07:46:56 2024
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//Source file index table:
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//file0 "\C:/cygwin64/home/koray/verilog/lab2/src/BitM.v"
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`timescale 100 ps/100 ps
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module BitM (
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A,
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B,
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AlB,
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AeB,
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AgB
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)
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;
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input A;
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input B;
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output AlB;
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output AeB;
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output AgB;
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wire A_d;
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wire B_d;
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wire AlB_d;
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wire AgB_d;
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wire AeB_d;
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wire VCC;
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wire GND;
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IBUF A_ibuf (
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.O(A_d),
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.I(A)
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);
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IBUF B_ibuf (
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.O(B_d),
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.I(B)
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);
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OBUF AlB_obuf (
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.O(AlB),
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.I(AlB_d)
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);
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OBUF AeB_obuf (
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.O(AeB),
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.I(AeB_d)
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);
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OBUF AgB_obuf (
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.O(AgB),
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.I(AgB_d)
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);
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LUT2 AlB_d_s (
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.F(AlB_d),
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.I0(A_d),
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.I1(B_d)
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);
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defparam AlB_d_s.INIT=4'h4;
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LUT2 AgB_d_s (
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.F(AgB_d),
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.I0(B_d),
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.I1(A_d)
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);
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defparam AgB_d_s.INIT=4'h4;
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LUT2 AeB_d_s (
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.F(AeB_d),
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.I0(A_d),
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.I1(B_d)
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);
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defparam AeB_d_s.INIT=4'h9;
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VCC VCC_cZ (
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.V(VCC)
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);
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GND GND_cZ (
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.G(GND)
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);
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GSR GSR (
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.GSRI(VCC)
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);
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endmodule /* BitM */
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167
lab2/impl/gwsynthesis/lab2_syn.rpt.html
Normal file
167
lab2/impl/gwsynthesis/lab2_syn.rpt.html
Normal file
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
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<html>
|
||||
<head>
|
||||
<title>synthesis Report</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
div#content { margin-left: 350px; margin-right: 30px; }
|
||||
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
|
||||
div#catalog ul { list-style-type: none; }
|
||||
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
|
||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
|
||||
div#catalog a:visited { color: #0084ff; }
|
||||
div#catalog a:hover { color: #fff; background: #0084ff; }
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||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
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h1 {margin-top: 50px; }
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||||
table, th, td { border: 1px solid #aaa; }
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||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table td.label { min-width: 100px; width: 8%;}
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
|
||||
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
|
||||
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
|
||||
<ul>
|
||||
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
|
||||
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
<div id="content">
|
||||
<h1><a name="about">Synthesis Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>GowinSynthesis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\cygwin64\home\koray\verilog\lab2\src\BitM.v<br>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">GowinSynthesis Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.9.02</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device Version</td>
|
||||
<td>C</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Thu Apr 11 07:46:56 2024
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="summary">Synthesis Details</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Top Level Module</td>
|
||||
<td>BitM</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Synthesis Process</td>
|
||||
<td>Running parser:<br/> CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 181.887MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.132s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>Generate output files:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 181.887MB<br/></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
|
||||
<td>CPU time = 0h 0m 0.108s, Elapsed time = 0h 0m 0.221s, Peak memory usage = 181.887MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="resource">Resource</a></h1>
|
||||
<h2><a name="usage">Resource Usage Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Port </b></td>
|
||||
<td>5</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Buf </b></td>
|
||||
<td>5</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    IBUF</td>
|
||||
<td>2</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    OBUF</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>LUT </b></td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT2</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="utilization">Resource Utilization Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
<td><b>Utilization</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>3(3 LUT, 0 ALU) / 20736</td>
|
||||
<td><1%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Register</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as Latch</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as FF</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BSRAM</td>
|
||||
<td>0 / 46</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
46
lab2/impl/gwsynthesis/lab2_syn_resource.html
Normal file
46
lab2/impl/gwsynthesis/lab2_syn_resource.html
Normal file
@ -0,0 +1,46 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Hierarchy Module Resource</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
h1 {text-align: center; }
|
||||
h1 {margin-top: 36px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { align = "center"; padding: 5px 2px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="content">
|
||||
<h1>Hierarchy Module Resource</h1>
|
||||
<table>
|
||||
<tr>
|
||||
<th class="label">MODULE NAME</th>
|
||||
<th class="label">REG NUMBER</th>
|
||||
<th class="label">ALU NUMBER</th>
|
||||
<th class="label">LUT NUMBER</th>
|
||||
<th class="label">DSP NUMBER</th>
|
||||
<th class="label">BSRAM NUMBER</th>
|
||||
<th class="label">SSRAM NUMBER</th>
|
||||
<th class="label">ROM16 NUMBER</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BitM (C:/cygwin64/home/koray/verilog/lab2/src/BitM.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">3</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
2
lab2/impl/gwsynthesis/lab2_syn_rsc.xml
Normal file
2
lab2/impl/gwsynthesis/lab2_syn_rsc.xml
Normal file
@ -0,0 +1,2 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Module name="BitM" Lut="3" T_Lut="3(3)"/>
|
||||
88
lab2/impl/lab2_process_config.json
Normal file
88
lab2/impl/lab2_process_config.json
Normal file
@ -0,0 +1,88 @@
|
||||
{
|
||||
"BACKGROUND_PROGRAMMING" : "off",
|
||||
"COMPRESS" : false,
|
||||
"CPU" : false,
|
||||
"CRC_CHECK" : true,
|
||||
"Clock_Route_Order" : 0,
|
||||
"Correct_Hold_Violation" : true,
|
||||
"DONE" : false,
|
||||
"DOWNLOAD_SPEED" : "default",
|
||||
"Disable_Insert_Pad" : false,
|
||||
"ENABLE_CTP" : false,
|
||||
"ENABLE_MERGE_MODE" : false,
|
||||
"ENCRYPTION_KEY" : false,
|
||||
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
|
||||
"ERROR_DECTION_AND_CORRECTION" : false,
|
||||
"ERROR_DECTION_ONLY" : false,
|
||||
"ERROR_INJECTION" : false,
|
||||
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
|
||||
"Enable_DSRM" : false,
|
||||
"FORMAT" : "binary",
|
||||
"FREQUENCY_DIVIDER" : "",
|
||||
"Generate_Constraint_File_of_Ports" : false,
|
||||
"Generate_IBIS_File" : false,
|
||||
"Generate_Plain_Text_Timing_Report" : false,
|
||||
"Generate_Post_PNR_Simulation_Model_File" : false,
|
||||
"Generate_Post_Place_File" : false,
|
||||
"Generate_SDF_File" : false,
|
||||
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
|
||||
"Global_Freq" : "default",
|
||||
"GwSyn_Loop_Limit" : 2000,
|
||||
"HOTBOOT" : false,
|
||||
"I2C" : false,
|
||||
"I2C_SLAVE_ADDR" : "00",
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"Incremental_Compile" : "",
|
||||
"Initialize_Primitives" : false,
|
||||
"JTAG" : false,
|
||||
"MODE_IO" : false,
|
||||
"MSPI" : false,
|
||||
"MSPI_JUMP" : false,
|
||||
"MULTIBOOT_ADDRESS_WIDTH" : "24",
|
||||
"MULTIBOOT_MODE" : "Normal",
|
||||
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
|
||||
"MULTIJUMP_ADDRESS_WIDTH" : "24",
|
||||
"MULTIJUMP_MODE" : "Normal",
|
||||
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
|
||||
"Multi_Boot" : true,
|
||||
"OUTPUT_BASE_NAME" : "lab2",
|
||||
"POWER_ON_RESET_MONITOR" : true,
|
||||
"PRINT_BSRAM_VALUE" : true,
|
||||
"PROGRAM_DONE_BYPASS" : false,
|
||||
"PlaceInRegToIob" : true,
|
||||
"PlaceIoRegToIob" : true,
|
||||
"PlaceOutRegToIob" : true,
|
||||
"Place_Option" : "0",
|
||||
"Process_Configuration_Verion" : "1.0",
|
||||
"Promote_Physical_Constraint_Warning_to_Error" : true,
|
||||
"READY" : false,
|
||||
"RECONFIG_N" : false,
|
||||
"Ram_RW_Check" : false,
|
||||
"Replicate_Resources" : false,
|
||||
"Report_Auto-Placed_Io_Information" : false,
|
||||
"Route_Maxfan" : 23,
|
||||
"Route_Option" : "0",
|
||||
"Run_Timing_Driven" : true,
|
||||
"SECURE_MODE" : false,
|
||||
"SECURITY_BIT" : true,
|
||||
"SEU_HANDLER" : false,
|
||||
"SEU_HANDLER_CHECKSUM" : false,
|
||||
"SEU_HANDLER_MODE" : "auto",
|
||||
"SSPI" : false,
|
||||
"STOP_SEU_HANDLER" : false,
|
||||
"Show_All_Warnings" : false,
|
||||
"Synthesize_tool" : "GowinSyn",
|
||||
"TclPre" : "",
|
||||
"TopModule" : "",
|
||||
"USERCODE" : "default",
|
||||
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
|
||||
"VCCAUX" : 3.3,
|
||||
"VCCX" : "3.3",
|
||||
"VHDL_Standard" : "VHDL_Std_1993",
|
||||
"Verilog_Standard" : "Vlg_Std_2001",
|
||||
"WAKE_UP" : "0",
|
||||
"show_all_warnings" : false,
|
||||
"turn_off_bg" : false
|
||||
}
|
||||
36
lab2/impl/temp/rtl_parser.result
Normal file
36
lab2/impl/temp/rtl_parser.result
Normal file
@ -0,0 +1,36 @@
|
||||
[
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v",
|
||||
"InstLine" : 1,
|
||||
"InstName" : "BitM",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "BitM"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v",
|
||||
"InstLine" : 1,
|
||||
"InstName" : "fullAdder",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "fullAdder"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"InstLine" : 1,
|
||||
"InstName" : "tb",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "tb",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"InstLine" : 6,
|
||||
"InstName" : "uut",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/halfAdder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfAdder"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
29
lab2/impl/temp/rtl_parser_arg.json
Normal file
29
lab2/impl/temp/rtl_parser_arg.json
Normal file
@ -0,0 +1,29 @@
|
||||
{
|
||||
"Device" : "GW2A-18C",
|
||||
"Files" : [
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/halfAdder.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"Type" : "verilog"
|
||||
}
|
||||
],
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"LoopLimit" : 2000,
|
||||
"ResultFile" : "C:/cygwin64/home/koray/verilog/lab2/impl/temp/rtl_parser.result",
|
||||
"Top" : "",
|
||||
"VerilogStd" : "verilog_2001",
|
||||
"VhdlStd" : "vhdl_93"
|
||||
}
|
||||
13
lab2/lab2.gprj
Normal file
13
lab2/lab2.gprj
Normal file
@ -0,0 +1,13 @@
|
||||
<?xml version="1" encoding="UTF-8"?>
|
||||
<!DOCTYPE gowin-fpga-project>
|
||||
<Project>
|
||||
<Template>FPGA</Template>
|
||||
<Version>5</Version>
|
||||
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
|
||||
<FileList>
|
||||
<File path="src/BitM.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/fullAdder.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/halfAdder.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/tb.v" type="file.verilog" enable="1"/>
|
||||
</FileList>
|
||||
</Project>
|
||||
17
lab2/lab2.gprj.user
Normal file
17
lab2/lab2.gprj.user
Normal file
@ -0,0 +1,17 @@
|
||||
<?xml version="1" encoding="UTF-8"?>
|
||||
<!DOCTYPE ProjectUserData>
|
||||
<UserConfig>
|
||||
<Version>1.0</Version>
|
||||
<FlowState>
|
||||
<Process ID="Synthesis" State="4"/>
|
||||
<Process ID="Pnr" State="0"/>
|
||||
<Process ID="Gao" State="0"/>
|
||||
<Process ID="Rtl_Gao" State="2"/>
|
||||
</FlowState>
|
||||
<ResultFileList>
|
||||
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/lab2.vg"/>
|
||||
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/lab2_syn.rpt.html"/>
|
||||
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/lab2_syn_rsc.xml"/>
|
||||
</ResultFileList>
|
||||
<Ui>000000ff00000001fd00000002000000000000010000000130fc0200000001fc00000063000001300000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000050000000121fc0100000001fc00000000000005000000009b00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000009b00ffffff000003f80000013000000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000</Ui>
|
||||
</UserConfig>
|
||||
19
lab2/src/BitM.v
Normal file
19
lab2/src/BitM.v
Normal file
@ -0,0 +1,19 @@
|
||||
module BitM(
|
||||
input A,
|
||||
input B,
|
||||
output AlB,
|
||||
output AeB,
|
||||
output AgB
|
||||
);
|
||||
|
||||
wire An, Bn;
|
||||
|
||||
not n1 (An, A);
|
||||
not n2 (Bn, B);
|
||||
|
||||
and a1 (AlB, An, B);
|
||||
and a2 (AgB, Bn, A);
|
||||
|
||||
nor nor1 (AeB, AlB, AgB);
|
||||
|
||||
endmodule
|
||||
26
lab2/src/BitM_tb.v
Normal file
26
lab2/src/BitM_tb.v
Normal file
@ -0,0 +1,26 @@
|
||||
module BitM_tb();
|
||||
|
||||
reg r1, r2;
|
||||
wire w1, w2, w3;
|
||||
|
||||
BitM uut(
|
||||
.A(r1),
|
||||
.B(r2),
|
||||
.AlB(w1),
|
||||
.AeB(w2),
|
||||
.AgB(w3)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("bdmp.vcd");
|
||||
$dumpvars;
|
||||
r1 = 0; r2 = 0; #10
|
||||
r1 = 0; r2 = 1; #10
|
||||
r1 = 1; r2 = 0; #10
|
||||
r1 = 1; r2 = 1; #10
|
||||
$display(w1);
|
||||
$display(w2);
|
||||
$display(w3);
|
||||
end
|
||||
|
||||
endmodule
|
||||
58
lab2/src/bdmp.vcd
Normal file
58
lab2/src/bdmp.vcd
Normal file
@ -0,0 +1,58 @@
|
||||
$date
|
||||
Thu Apr 11 07:50:26 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module BitM_tb $end
|
||||
$var wire 1 ! w3 $end
|
||||
$var wire 1 " w2 $end
|
||||
$var wire 1 # w1 $end
|
||||
$var reg 1 $ r1 $end
|
||||
$var reg 1 % r2 $end
|
||||
$scope module uut $end
|
||||
$var wire 1 $ A $end
|
||||
$var wire 1 " AeB $end
|
||||
$var wire 1 ! AgB $end
|
||||
$var wire 1 # AlB $end
|
||||
$var wire 1 & An $end
|
||||
$var wire 1 % B $end
|
||||
$var wire 1 ' Bn $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
1'
|
||||
1&
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
1"
|
||||
0!
|
||||
$end
|
||||
#10
|
||||
0"
|
||||
0'
|
||||
1#
|
||||
1%
|
||||
#20
|
||||
1!
|
||||
0"
|
||||
1'
|
||||
0#
|
||||
0&
|
||||
0%
|
||||
1$
|
||||
#30
|
||||
1"
|
||||
0!
|
||||
0'
|
||||
1%
|
||||
#40
|
||||
70
lab2/src/blab2
Normal file
70
lab2/src/blab2
Normal file
@ -0,0 +1,70 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000002114102cad0 .scope module, "BitM_tb" "BitM_tb" 2 1;
|
||||
.timescale 0 0;
|
||||
v0000021140f146e0_0 .var "r1", 0 0;
|
||||
v0000021140f14780_0 .var "r2", 0 0;
|
||||
v0000021140f14820_0 .net "w1", 0 0, L_0000021140ee32f0; 1 drivers
|
||||
v0000021140f148c0_0 .net "w2", 0 0, L_0000021140f14f60; 1 drivers
|
||||
v0000021140f14960_0 .net "w3", 0 0, L_0000021140f14de0; 1 drivers
|
||||
S_000002114102cc60 .scope module, "uut" "BitM" 2 6, 3 1 0, S_000002114102cad0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "AlB";
|
||||
.port_info 3 /OUTPUT 1 "AeB";
|
||||
.port_info 4 /OUTPUT 1 "AgB";
|
||||
L_000002114102af60 .functor NOT 1, v0000021140f146e0_0, C4<0>, C4<0>, C4<0>;
|
||||
L_0000021140ee3190 .functor NOT 1, v0000021140f14780_0, C4<0>, C4<0>, C4<0>;
|
||||
L_0000021140ee32f0 .functor AND 1, L_000002114102af60, v0000021140f14780_0, C4<1>, C4<1>;
|
||||
L_0000021140f14de0 .functor AND 1, L_0000021140ee3190, v0000021140f146e0_0, C4<1>, C4<1>;
|
||||
L_0000021140f14f60 .functor NOR 1, L_0000021140ee32f0, L_0000021140f14de0, C4<0>, C4<0>;
|
||||
v0000021141028fc0_0 .net "A", 0 0, v0000021140f146e0_0; 1 drivers
|
||||
v0000021140ee2ee0_0 .net "AeB", 0 0, L_0000021140f14f60; alias, 1 drivers
|
||||
v000002114102aec0_0 .net "AgB", 0 0, L_0000021140f14de0; alias, 1 drivers
|
||||
v000002114102cdf0_0 .net "AlB", 0 0, L_0000021140ee32f0; alias, 1 drivers
|
||||
v000002114102ce90_0 .net "An", 0 0, L_000002114102af60; 1 drivers
|
||||
v0000021140f145a0_0 .net "B", 0 0, v0000021140f14780_0; 1 drivers
|
||||
v0000021140f14640_0 .net "Bn", 0 0, L_0000021140ee3190; 1 drivers
|
||||
.scope S_000002114102cad0;
|
||||
T_0 ;
|
||||
%vpi_call 2 15 "$dumpfile", "bdmp.vcd" {0 0 0};
|
||||
%vpi_call 2 16 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0000021140f146e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0000021140f14780_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0000021140f146e0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0000021140f14780_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0000021140f146e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0000021140f14780_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0000021140f146e0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0000021140f14780_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 21 "$display", v0000021140f14820_0 {0 0 0};
|
||||
%vpi_call 2 22 "$display", v0000021140f148c0_0 {0 0 0};
|
||||
%vpi_call 2 23 "$display", v0000021140f14960_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"BitM_tb.v";
|
||||
"BitM.v";
|
||||
43
lab2/src/dmp.vcd
Normal file
43
lab2/src/dmp.vcd
Normal file
@ -0,0 +1,43 @@
|
||||
$date
|
||||
Thu Apr 11 06:36:34 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module tb $end
|
||||
$var wire 1 ! w2 $end
|
||||
$var wire 1 " w1 $end
|
||||
$var reg 1 # r1 $end
|
||||
$var reg 1 $ r2 $end
|
||||
$scope module uut $end
|
||||
$var wire 1 # A $end
|
||||
$var wire 1 $ B $end
|
||||
$var wire 1 ! C $end
|
||||
$var wire 1 " S $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
0$
|
||||
0#
|
||||
0"
|
||||
0!
|
||||
$end
|
||||
#20
|
||||
1"
|
||||
1#
|
||||
#40
|
||||
1$
|
||||
0#
|
||||
#60
|
||||
0"
|
||||
1!
|
||||
1#
|
||||
#80
|
||||
75
lab2/src/fdmp.vcd
Normal file
75
lab2/src/fdmp.vcd
Normal file
@ -0,0 +1,75 @@
|
||||
$date
|
||||
Thu Apr 11 07:39:27 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module ftb $end
|
||||
$var wire 1 ! w2 $end
|
||||
$var wire 1 " w1 $end
|
||||
$var reg 1 # r1 $end
|
||||
$var reg 1 $ r2 $end
|
||||
$var reg 1 % r3 $end
|
||||
$scope module uut $end
|
||||
$var wire 1 # A $end
|
||||
$var wire 1 & AB $end
|
||||
$var wire 1 ' ABCin $end
|
||||
$var wire 1 ( AaB $end
|
||||
$var wire 1 $ B $end
|
||||
$var wire 1 % Cin $end
|
||||
$var wire 1 ! Cout $end
|
||||
$var wire 1 " S $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
0(
|
||||
0'
|
||||
0&
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
0"
|
||||
0!
|
||||
$end
|
||||
#10
|
||||
1"
|
||||
1%
|
||||
#20
|
||||
1&
|
||||
0%
|
||||
1$
|
||||
#30
|
||||
1!
|
||||
0"
|
||||
1'
|
||||
1%
|
||||
#40
|
||||
0!
|
||||
1"
|
||||
0'
|
||||
0%
|
||||
0$
|
||||
1#
|
||||
#50
|
||||
1!
|
||||
0"
|
||||
1'
|
||||
1%
|
||||
#60
|
||||
0'
|
||||
0&
|
||||
1(
|
||||
0%
|
||||
1$
|
||||
#70
|
||||
1"
|
||||
1%
|
||||
#80
|
||||
106
lab2/src/flab2
Normal file
106
lab2/src/flab2
Normal file
@ -0,0 +1,106 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000001da0354ad70 .scope module, "ftb" "ftb" 2 1;
|
||||
.timescale 0 0;
|
||||
v000001da035dc840_0 .var "r1", 0 0;
|
||||
v000001da035dc8e0_0 .var "r2", 0 0;
|
||||
v000001da035dc980_0 .var "r3", 0 0;
|
||||
v000001da035dca20_0 .net "w1", 0 0, L_000001da03594080; 1 drivers
|
||||
v000001da035935f0_0 .net "w2", 0 0, L_000001da03594470; 1 drivers
|
||||
S_000001da0354e9e0 .scope module, "uut" "fullAdder" 2 6, 3 1 0, S_000001da0354ad70;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Cin";
|
||||
.port_info 3 /OUTPUT 1 "S";
|
||||
.port_info 4 /OUTPUT 1 "Cout";
|
||||
L_000001da03594010 .functor XOR 1, v000001da035dc840_0, v000001da035dc8e0_0, C4<0>, C4<0>;
|
||||
L_000001da03594080 .functor XOR 1, L_000001da03594010, v000001da035dc980_0, C4<0>, C4<0>;
|
||||
L_000001da03593e50 .functor AND 1, L_000001da03594010, v000001da035dc980_0, C4<1>, C4<1>;
|
||||
L_000001da035940f0 .functor AND 1, v000001da035dc840_0, v000001da035dc8e0_0, C4<1>, C4<1>;
|
||||
L_000001da03594470 .functor OR 1, L_000001da03593e50, L_000001da035940f0, C4<0>, C4<0>;
|
||||
v000001da03563310_0 .net "A", 0 0, v000001da035dc840_0; 1 drivers
|
||||
v000001da03562ee0_0 .net "AB", 0 0, L_000001da03594010; 1 drivers
|
||||
v000001da0354af00_0 .net "ABCin", 0 0, L_000001da03593e50; 1 drivers
|
||||
v000001da03549850_0 .net "AaB", 0 0, L_000001da035940f0; 1 drivers
|
||||
v000001da0354eb70_0 .net "B", 0 0, v000001da035dc8e0_0; 1 drivers
|
||||
v000001da0354ec10_0 .net "Cin", 0 0, v000001da035dc980_0; 1 drivers
|
||||
v000001da0354ecb0_0 .net "Cout", 0 0, L_000001da03594470; alias, 1 drivers
|
||||
v000001da0354ed50_0 .net "S", 0 0, L_000001da03594080; alias, 1 drivers
|
||||
.scope S_000001da0354ad70;
|
||||
T_0 ;
|
||||
%vpi_call 2 15 "$dumpfile", "fdmp.vcd" {0 0 0};
|
||||
%vpi_call 2 16 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 25 "$display", v000001da035dca20_0 {0 0 0};
|
||||
%vpi_call 2 26 "$display", v000001da035935f0_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"ftb.v";
|
||||
"fullAdder.v";
|
||||
29
lab2/src/ftb.v
Normal file
29
lab2/src/ftb.v
Normal file
@ -0,0 +1,29 @@
|
||||
module ftb ();
|
||||
|
||||
reg r1, r2, r3;
|
||||
wire w1, w2;
|
||||
|
||||
fullAdder uut(
|
||||
.A(r1),
|
||||
.B(r2),
|
||||
.Cin(r3),
|
||||
.S(w1),
|
||||
.Cout(w2)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("fdmp.vcd");
|
||||
$dumpvars;
|
||||
r1 = 0; r2 = 0; r3 = 0; #10
|
||||
r1 = 0; r2 = 0; r3 = 1; #10
|
||||
r1 = 0; r2 = 1; r3 = 0; #10
|
||||
r1 = 0; r2 = 1; r3 = 1; #10
|
||||
r1 = 1; r2 = 0; r3 = 0; #10
|
||||
r1 = 1; r2 = 0; r3 = 1; #10
|
||||
r1 = 1; r2 = 1; r3 = 0; #10
|
||||
r1 = 1; r2 = 1; r3 = 1; #10
|
||||
$display(w1);
|
||||
$display(w2);
|
||||
end
|
||||
|
||||
endmodule
|
||||
20
lab2/src/fullAdder.v
Normal file
20
lab2/src/fullAdder.v
Normal file
@ -0,0 +1,20 @@
|
||||
module fullAdder(
|
||||
input A,
|
||||
input B,
|
||||
input Cin,
|
||||
output S,
|
||||
output Cout
|
||||
);
|
||||
|
||||
wire AB;
|
||||
wire ABCin, AaB;
|
||||
|
||||
xor (AB, A, B);
|
||||
xor (S, AB, Cin);
|
||||
|
||||
and (ABCin, AB, Cin);
|
||||
and (AaB, A, B);
|
||||
|
||||
or (Cout, ABCin, AaB);
|
||||
|
||||
endmodule
|
||||
11
lab2/src/halfAdder.v
Normal file
11
lab2/src/halfAdder.v
Normal file
@ -0,0 +1,11 @@
|
||||
module halfAdder(
|
||||
input A,
|
||||
input B,
|
||||
output S,
|
||||
output C
|
||||
);
|
||||
|
||||
xor (S, A, B);
|
||||
and (C, A, B);
|
||||
|
||||
endmodule
|
||||
61
lab2/src/lab2
Normal file
61
lab2/src/lab2
Normal file
@ -0,0 +1,61 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000001b4458eec80 .scope module, "tb" "tb" 2 1;
|
||||
.timescale 0 0;
|
||||
v000001b4458ec1d0_0 .var "r1", 0 0;
|
||||
v000001b4458ec270_0 .var "r2", 0 0;
|
||||
v000001b4458ec310_0 .net "w1", 0 0, L_000001b445783190; 1 drivers
|
||||
v000001b4458ec3b0_0 .net "w2", 0 0, L_000001b4457832f0; 1 drivers
|
||||
S_000001b4458eee10 .scope module, "uut" "halfAdder" 2 6, 3 1 0, S_000001b4458eec80;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_000001b445783190 .functor XOR 1, v000001b4458ec1d0_0, v000001b4458ec270_0, C4<0>, C4<0>;
|
||||
L_000001b4457832f0 .functor AND 1, v000001b4458ec1d0_0, v000001b4458ec270_0, C4<1>, C4<1>;
|
||||
v000001b4458ebff0_0 .net "A", 0 0, v000001b4458ec1d0_0; 1 drivers
|
||||
v000001b445782ee0_0 .net "B", 0 0, v000001b4458ec270_0; 1 drivers
|
||||
v000001b4458ec090_0 .net "C", 0 0, L_000001b4457832f0; alias, 1 drivers
|
||||
v000001b4458ec130_0 .net "S", 0 0, L_000001b445783190; alias, 1 drivers
|
||||
.scope S_000001b4458eec80;
|
||||
T_0 ;
|
||||
%vpi_call 2 14 "$dumpfile", "dmp.vcd" {0 0 0};
|
||||
%vpi_call 2 15 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b4458ec1d0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b4458ec270_0, 0, 1;
|
||||
%delay 20, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001b4458ec1d0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b4458ec270_0, 0, 1;
|
||||
%delay 20, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b4458ec1d0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001b4458ec270_0, 0, 1;
|
||||
%delay 20, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001b4458ec1d0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001b4458ec270_0, 0, 1;
|
||||
%delay 20, 0;
|
||||
%vpi_call 2 20 "$display", v000001b4458ec310_0 {0 0 0};
|
||||
%vpi_call 2 21 "$display", v000001b4458ec3b0_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"tb.v";
|
||||
"halfAdder.v";
|
||||
24
lab2/src/tb.v
Normal file
24
lab2/src/tb.v
Normal file
@ -0,0 +1,24 @@
|
||||
module tb();
|
||||
|
||||
reg r1, r2;
|
||||
wire w1, w2;
|
||||
|
||||
halfAdder uut(
|
||||
.A(r1),
|
||||
.B(r2),
|
||||
.S(w1),
|
||||
.C(w2)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("dmp.vcd");
|
||||
$dumpvars;
|
||||
r1 = 0; r2 = 0; #20
|
||||
r1 = 1; r2 = 0; #20
|
||||
r1 = 0; r2 = 1; #20
|
||||
r1 = 1; r2 = 1; #20
|
||||
$display(w1);
|
||||
$display(w2);
|
||||
end
|
||||
|
||||
endmodule
|
||||
40
lab2_prep/impl/gwsynthesis/lab2.log
Normal file
40
lab2_prep/impl/gwsynthesis/lab2.log
Normal file
@ -0,0 +1,40 @@
|
||||
GowinSynthesis start
|
||||
Running parser ...
|
||||
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\lab2.v'
|
||||
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\tb.v'
|
||||
Compiling module 'tb'("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":1)
|
||||
WARN (EX3858) : System task 'dumpfile' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":17)
|
||||
WARN (EX3858) : System task 'dumpvars' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":18)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":19)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":20)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":21)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":22)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":23)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":24)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":25)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":26)
|
||||
WARN (EX3858) : System task 'display' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":27)
|
||||
WARN (EX3780) : Using initial value of 'r1' since it is never assigned("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":28)
|
||||
Compiling module 'lab2'("C:\cygwin64\home\koray\verilog\lab2\src\lab2.v":1)
|
||||
NOTE (EX0101) : Current top module is "tb"
|
||||
WARN (EX0203) : Top module "tb" has no ports("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":1)
|
||||
[5%] Running netlist conversion ...
|
||||
Running device independent optimization ...
|
||||
[10%] Optimizing Phase 0 completed
|
||||
[15%] Optimizing Phase 1 completed
|
||||
[25%] Optimizing Phase 2 completed
|
||||
Running inference ...
|
||||
[30%] Inferring Phase 0 completed
|
||||
[40%] Inferring Phase 1 completed
|
||||
[50%] Inferring Phase 2 completed
|
||||
[55%] Inferring Phase 3 completed
|
||||
Running technical mapping ...
|
||||
[60%] Tech-Mapping Phase 0 completed
|
||||
[65%] Tech-Mapping Phase 1 completed
|
||||
[75%] Tech-Mapping Phase 2 completed
|
||||
[80%] Tech-Mapping Phase 3 completed
|
||||
[90%] Tech-Mapping Phase 4 completed
|
||||
WARN (NL0002) : The module "lab2" instantiated to "uut" is swept in optimizing("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":12)
|
||||
[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg" completed
|
||||
[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2_syn.rpt.html" completed
|
||||
GowinSynthesis finish
|
||||
20
lab2_prep/impl/gwsynthesis/lab2.prj
Normal file
20
lab2_prep/impl/gwsynthesis/lab2.prj
Normal file
@ -0,0 +1,20 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE gowin-synthesis-project>
|
||||
<Project>
|
||||
<Version>beta</Version>
|
||||
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
|
||||
<FileList>
|
||||
<File path="C:\cygwin64\home\koray\verilog\lab2\src\lab2.v" type="verilog"/>
|
||||
<File path="C:\cygwin64\home\koray\verilog\lab2\src\tb.v" type="verilog"/>
|
||||
</FileList>
|
||||
<OptionList>
|
||||
<Option type="disable_insert_pad" value="0"/>
|
||||
<Option type="global_freq" value="100.000"/>
|
||||
<Option type="looplimit" value="2000"/>
|
||||
<Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg"/>
|
||||
<Option type="print_all_synthesis_warning" value="0"/>
|
||||
<Option type="ram_rw_check" value="0"/>
|
||||
<Option type="verilog_language" value="verilog-2001"/>
|
||||
<Option type="vhdl_language" value="vhdl-1993"/>
|
||||
</OptionList>
|
||||
</Project>
|
||||
25
lab2_prep/impl/gwsynthesis/lab2.vg
Normal file
25
lab2_prep/impl/gwsynthesis/lab2.vg
Normal file
@ -0,0 +1,25 @@
|
||||
//
|
||||
//Written by GowinSynthesis
|
||||
//Tool Version "V1.9.9.02"
|
||||
//Thu Apr 11 06:15:18 2024
|
||||
|
||||
//Source file index table:
|
||||
//file0 "\C:/cygwin64/home/koray/verilog/lab2/src/lab2.v"
|
||||
//file1 "\C:/cygwin64/home/koray/verilog/lab2/src/tb.v"
|
||||
`timescale 100 ps/100 ps
|
||||
module tb (
|
||||
|
||||
)
|
||||
;
|
||||
wire VCC;
|
||||
wire GND;
|
||||
VCC VCC_cZ (
|
||||
.V(VCC)
|
||||
);
|
||||
GND GND_cZ (
|
||||
.G(GND)
|
||||
);
|
||||
GSR GSR (
|
||||
.GSRI(VCC)
|
||||
);
|
||||
endmodule /* tb */
|
||||
144
lab2_prep/impl/gwsynthesis/lab2_syn.rpt.html
Normal file
144
lab2_prep/impl/gwsynthesis/lab2_syn.rpt.html
Normal file
@ -0,0 +1,144 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>synthesis Report</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
div#content { margin-left: 350px; margin-right: 30px; }
|
||||
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
|
||||
div#catalog ul { list-style-type: none; }
|
||||
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
|
||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
|
||||
div#catalog a:visited { color: #0084ff; }
|
||||
div#catalog a:hover { color: #fff; background: #0084ff; }
|
||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
|
||||
h1 {margin-top: 50px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table td.label { min-width: 100px; width: 8%;}
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
|
||||
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
|
||||
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
|
||||
<ul>
|
||||
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
|
||||
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
<div id="content">
|
||||
<h1><a name="about">Synthesis Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>GowinSynthesis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\cygwin64\home\koray\verilog\lab2\src\lab2.v<br>
|
||||
C:\cygwin64\home\koray\verilog\lab2\src\tb.v<br>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">GowinSynthesis Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.9.02</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device Version</td>
|
||||
<td>C</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Thu Apr 11 06:15:18 2024
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="summary">Synthesis Details</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Top Level Module</td>
|
||||
<td>tb</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Synthesis Process</td>
|
||||
<td>Running parser:<br/> CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.148s, Peak memory usage = 184.680MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 184.680MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>Generate output files:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 184.680MB<br/></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
|
||||
<td>CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.208s, Peak memory usage = 184.680MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="resource">Resource</a></h1>
|
||||
<h2><a name="usage">Resource Usage Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="utilization">Resource Utilization Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
<td><b>Utilization</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>0(0 LUT, 0 ALU) / 20736</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Register</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as Latch</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as FF</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BSRAM</td>
|
||||
<td>0 / 46</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
46
lab2_prep/impl/gwsynthesis/lab2_syn_resource.html
Normal file
46
lab2_prep/impl/gwsynthesis/lab2_syn_resource.html
Normal file
@ -0,0 +1,46 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Hierarchy Module Resource</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
h1 {text-align: center; }
|
||||
h1 {margin-top: 36px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { align = "center"; padding: 5px 2px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="content">
|
||||
<h1>Hierarchy Module Resource</h1>
|
||||
<table>
|
||||
<tr>
|
||||
<th class="label">MODULE NAME</th>
|
||||
<th class="label">REG NUMBER</th>
|
||||
<th class="label">ALU NUMBER</th>
|
||||
<th class="label">LUT NUMBER</th>
|
||||
<th class="label">DSP NUMBER</th>
|
||||
<th class="label">BSRAM NUMBER</th>
|
||||
<th class="label">SSRAM NUMBER</th>
|
||||
<th class="label">ROM16 NUMBER</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">tb (C:/cygwin64/home/koray/verilog/lab2/src/tb.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
2
lab2_prep/impl/gwsynthesis/lab2_syn_rsc.xml
Normal file
2
lab2_prep/impl/gwsynthesis/lab2_syn_rsc.xml
Normal file
@ -0,0 +1,2 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Module name="tb"/>
|
||||
88
lab2_prep/impl/lab2_process_config.json
Normal file
88
lab2_prep/impl/lab2_process_config.json
Normal file
@ -0,0 +1,88 @@
|
||||
{
|
||||
"BACKGROUND_PROGRAMMING" : "off",
|
||||
"COMPRESS" : false,
|
||||
"CPU" : false,
|
||||
"CRC_CHECK" : true,
|
||||
"Clock_Route_Order" : 0,
|
||||
"Correct_Hold_Violation" : true,
|
||||
"DONE" : false,
|
||||
"DOWNLOAD_SPEED" : "default",
|
||||
"Disable_Insert_Pad" : false,
|
||||
"ENABLE_CTP" : false,
|
||||
"ENABLE_MERGE_MODE" : false,
|
||||
"ENCRYPTION_KEY" : false,
|
||||
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
|
||||
"ERROR_DECTION_AND_CORRECTION" : false,
|
||||
"ERROR_DECTION_ONLY" : false,
|
||||
"ERROR_INJECTION" : false,
|
||||
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
|
||||
"Enable_DSRM" : false,
|
||||
"FORMAT" : "binary",
|
||||
"FREQUENCY_DIVIDER" : "",
|
||||
"Generate_Constraint_File_of_Ports" : false,
|
||||
"Generate_IBIS_File" : false,
|
||||
"Generate_Plain_Text_Timing_Report" : false,
|
||||
"Generate_Post_PNR_Simulation_Model_File" : false,
|
||||
"Generate_Post_Place_File" : false,
|
||||
"Generate_SDF_File" : false,
|
||||
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
|
||||
"Global_Freq" : "default",
|
||||
"GwSyn_Loop_Limit" : 2000,
|
||||
"HOTBOOT" : false,
|
||||
"I2C" : false,
|
||||
"I2C_SLAVE_ADDR" : "00",
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"Incremental_Compile" : "",
|
||||
"Initialize_Primitives" : false,
|
||||
"JTAG" : false,
|
||||
"MODE_IO" : false,
|
||||
"MSPI" : false,
|
||||
"MSPI_JUMP" : false,
|
||||
"MULTIBOOT_ADDRESS_WIDTH" : "24",
|
||||
"MULTIBOOT_MODE" : "Normal",
|
||||
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
|
||||
"MULTIJUMP_ADDRESS_WIDTH" : "24",
|
||||
"MULTIJUMP_MODE" : "Normal",
|
||||
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
|
||||
"Multi_Boot" : true,
|
||||
"OUTPUT_BASE_NAME" : "lab2",
|
||||
"POWER_ON_RESET_MONITOR" : true,
|
||||
"PRINT_BSRAM_VALUE" : true,
|
||||
"PROGRAM_DONE_BYPASS" : false,
|
||||
"PlaceInRegToIob" : true,
|
||||
"PlaceIoRegToIob" : true,
|
||||
"PlaceOutRegToIob" : true,
|
||||
"Place_Option" : "0",
|
||||
"Process_Configuration_Verion" : "1.0",
|
||||
"Promote_Physical_Constraint_Warning_to_Error" : true,
|
||||
"READY" : false,
|
||||
"RECONFIG_N" : false,
|
||||
"Ram_RW_Check" : false,
|
||||
"Replicate_Resources" : false,
|
||||
"Report_Auto-Placed_Io_Information" : false,
|
||||
"Route_Maxfan" : 23,
|
||||
"Route_Option" : "0",
|
||||
"Run_Timing_Driven" : true,
|
||||
"SECURE_MODE" : false,
|
||||
"SECURITY_BIT" : true,
|
||||
"SEU_HANDLER" : false,
|
||||
"SEU_HANDLER_CHECKSUM" : false,
|
||||
"SEU_HANDLER_MODE" : "auto",
|
||||
"SSPI" : false,
|
||||
"STOP_SEU_HANDLER" : false,
|
||||
"Show_All_Warnings" : false,
|
||||
"Synthesize_tool" : "GowinSyn",
|
||||
"TclPre" : "",
|
||||
"TopModule" : "",
|
||||
"USERCODE" : "default",
|
||||
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
|
||||
"VCCAUX" : 3.3,
|
||||
"VCCX" : "3.3",
|
||||
"VHDL_Standard" : "VHDL_Std_1993",
|
||||
"Verilog_Standard" : "Vlg_Std_2001",
|
||||
"WAKE_UP" : "0",
|
||||
"show_all_warnings" : false,
|
||||
"turn_off_bg" : false
|
||||
}
|
||||
20
lab2_prep/impl/temp/rtl_parser.result
Normal file
20
lab2_prep/impl/temp/rtl_parser.result
Normal file
@ -0,0 +1,20 @@
|
||||
[
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"InstLine" : 1,
|
||||
"InstName" : "tb",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "tb",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"InstLine" : 6,
|
||||
"InstName" : "uut",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/lab2.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "lab2"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
21
lab2_prep/impl/temp/rtl_parser_arg.json
Normal file
21
lab2_prep/impl/temp/rtl_parser_arg.json
Normal file
@ -0,0 +1,21 @@
|
||||
{
|
||||
"Device" : "GW2A-18C",
|
||||
"Files" : [
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/lab2.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"Type" : "verilog"
|
||||
}
|
||||
],
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"LoopLimit" : 2000,
|
||||
"ResultFile" : "C:/cygwin64/home/koray/verilog/lab2/impl/temp/rtl_parser.result",
|
||||
"Top" : "",
|
||||
"VerilogStd" : "verilog_2001",
|
||||
"VhdlStd" : "vhdl_93"
|
||||
}
|
||||
12
lab2_prep/lab2.gprj
Normal file
12
lab2_prep/lab2.gprj
Normal file
@ -0,0 +1,12 @@
|
||||
<?xml version="1" encoding="UTF-8"?>
|
||||
<!DOCTYPE gowin-fpga-project>
|
||||
<Project>
|
||||
<Template>FPGA</Template>
|
||||
<Version>5</Version>
|
||||
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
|
||||
<FileList>
|
||||
<File path="src/lab2.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/tb.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/labwave" type="file.other" enable="1"/>
|
||||
</FileList>
|
||||
</Project>
|
||||
17
lab2_prep/lab2.gprj.user
Normal file
17
lab2_prep/lab2.gprj.user
Normal file
@ -0,0 +1,17 @@
|
||||
<?xml version="1" encoding="UTF-8"?>
|
||||
<!DOCTYPE ProjectUserData>
|
||||
<UserConfig>
|
||||
<Version>1.0</Version>
|
||||
<FlowState>
|
||||
<Process ID="Synthesis" State="2"/>
|
||||
<Process ID="Pnr" State="0"/>
|
||||
<Process ID="Gao" State="0"/>
|
||||
<Process ID="Rtl_Gao" State="2"/>
|
||||
</FlowState>
|
||||
<ResultFileList>
|
||||
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/lab2.vg"/>
|
||||
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/lab2_syn.rpt.html"/>
|
||||
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/lab2_syn_rsc.xml"/>
|
||||
</ResultFileList>
|
||||
<Ui>000000ff00000001fd0000000200000000000001700000013dfc0200000001fc000000630000013d0000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000050000000114fc0100000001fc0000000000000500000000a100fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000007800fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100ffffff000003880000013d00000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000</Ui>
|
||||
</UserConfig>
|
||||
77
lab2_prep/src/dmp.vcd
Normal file
77
lab2_prep/src/dmp.vcd
Normal file
@ -0,0 +1,77 @@
|
||||
$date
|
||||
Thu Apr 11 06:20:47 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module tb $end
|
||||
$var wire 1 ! w1 $end
|
||||
$var reg 1 " r1 $end
|
||||
$var reg 1 # r2 $end
|
||||
$var reg 1 $ r3 $end
|
||||
$var reg 1 % r4 $end
|
||||
$scope module uut $end
|
||||
$var wire 1 " A $end
|
||||
$var wire 1 & AD $end
|
||||
$var wire 1 ' An $end
|
||||
$var wire 1 ( AnBC $end
|
||||
$var wire 1 # B $end
|
||||
$var wire 1 ) Bn $end
|
||||
$var wire 1 $ C $end
|
||||
$var wire 1 * Cn $end
|
||||
$var wire 1 + CnD $end
|
||||
$var wire 1 % D $end
|
||||
$var wire 1 ! F $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
0+
|
||||
1*
|
||||
1)
|
||||
0(
|
||||
1'
|
||||
0&
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
0"
|
||||
1!
|
||||
$end
|
||||
#50
|
||||
1+
|
||||
1%
|
||||
#100
|
||||
0+
|
||||
0*
|
||||
0%
|
||||
1$
|
||||
#150
|
||||
1%
|
||||
#200
|
||||
0!
|
||||
1*
|
||||
0)
|
||||
0%
|
||||
0$
|
||||
1#
|
||||
#250
|
||||
1!
|
||||
1+
|
||||
1%
|
||||
#300
|
||||
0+
|
||||
1(
|
||||
0*
|
||||
0%
|
||||
1$
|
||||
#350
|
||||
1%
|
||||
#400
|
||||
126
lab2_prep/src/lab
Normal file
126
lab2_prep/src/lab
Normal file
@ -0,0 +1,126 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000001e2946aad20 .scope module, "tb" "tb" 2 1;
|
||||
.timescale 0 0;
|
||||
v000001e29475e7f0_0 .var "r1", 0 0;
|
||||
v000001e29475e6b0_0 .var "r2", 0 0;
|
||||
v000001e29475ec50_0 .var "r3", 0 0;
|
||||
v000001e29475e430_0 .var "r4", 0 0;
|
||||
v000001e29475ecf0_0 .net "w1", 0 0, L_000001e29475f0f0; 1 drivers
|
||||
S_000001e294717fc0 .scope module, "uut" "lab2" 2 6, 3 1 0, S_000001e2946aad20;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "C";
|
||||
.port_info 3 /INPUT 1 "D";
|
||||
.port_info 4 /OUTPUT 1 "F";
|
||||
L_000001e2947183d0 .functor NOT 1, v000001e29475e7f0_0, C4<0>, C4<0>, C4<0>;
|
||||
L_000001e2946e2bc0 .functor AND 1, L_000001e2947183d0, v000001e29475e6b0_0, v000001e29475ec50_0, C4<1>;
|
||||
L_000001e2946e2d20 .functor NOT 1, v000001e29475e6b0_0, C4<0>, C4<0>, C4<0>;
|
||||
L_000001e29475f390 .functor AND 1, v000001e29475e7f0_0, v000001e29475e430_0, C4<1>, C4<1>;
|
||||
L_000001e29475f4e0 .functor NOT 1, v000001e29475ec50_0, C4<0>, C4<0>, C4<0>;
|
||||
L_000001e29475f780 .functor AND 1, L_000001e29475f4e0, v000001e29475e430_0, C4<1>, C4<1>;
|
||||
L_000001e29475f0f0 .functor OR 1, L_000001e2946e2bc0, L_000001e2946e2d20, L_000001e29475f390, L_000001e29475f780;
|
||||
v000001e2946e2a40_0 .net "A", 0 0, v000001e29475e7f0_0; 1 drivers
|
||||
v000001e2946e28d0_0 .net "AD", 0 0, L_000001e29475f390; 1 drivers
|
||||
v000001e2946a9e10_0 .net "An", 0 0, L_000001e2947183d0; 1 drivers
|
||||
v000001e2946aaeb0_0 .net "AnBC", 0 0, L_000001e2946e2bc0; 1 drivers
|
||||
v000001e294718150_0 .net "B", 0 0, v000001e29475e6b0_0; 1 drivers
|
||||
v000001e2947181f0_0 .net "Bn", 0 0, L_000001e2946e2d20; 1 drivers
|
||||
v000001e294718290_0 .net "C", 0 0, v000001e29475ec50_0; 1 drivers
|
||||
v000001e294718330_0 .net "Cn", 0 0, L_000001e29475f4e0; 1 drivers
|
||||
v000001e294714e50_0 .net "CnD", 0 0, L_000001e29475f780; 1 drivers
|
||||
v000001e294714ef0_0 .net "D", 0 0, v000001e29475e430_0; 1 drivers
|
||||
v000001e29475e390_0 .net "F", 0 0, L_000001e29475f0f0; alias, 1 drivers
|
||||
.scope S_000001e2946aad20;
|
||||
T_0 ;
|
||||
%vpi_call 2 17 "$dumpfile", "dmp.vcd" {0 0 0};
|
||||
%vpi_call 2 18 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%vpi_call 2 27 "$display", v000001e29475ecf0_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"tb.v";
|
||||
"lab2.v";
|
||||
43
lab2_prep/src/lab2
Normal file
43
lab2_prep/src/lab2
Normal file
@ -0,0 +1,43 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_0000016d6fd625e0 .scope module, "lab2" "lab2" 2 1;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "C";
|
||||
.port_info 3 /INPUT 1 "D";
|
||||
.port_info 4 /OUTPUT 1 "F";
|
||||
o0000016d6fd96f98 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_0000016d6fd62f70 .functor NOT 1, o0000016d6fd96f98, C4<0>, C4<0>, C4<0>;
|
||||
o0000016d6fd97058 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
o0000016d6fd970b8 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_0000016d6fedb7d0 .functor AND 1, L_0000016d6fd62f70, o0000016d6fd97058, o0000016d6fd970b8, C4<1>;
|
||||
L_0000016d6fedb840 .functor NOT 1, o0000016d6fd97058, C4<0>, C4<0>, C4<0>;
|
||||
o0000016d6fd97148 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_0000016d6fedb8b0 .functor AND 1, o0000016d6fd96f98, o0000016d6fd97148, C4<1>, C4<1>;
|
||||
L_0000016d6fedb920 .functor NOT 1, o0000016d6fd970b8, C4<0>, C4<0>, C4<0>;
|
||||
L_0000016d6fedb990 .functor AND 1, L_0000016d6fedb920, o0000016d6fd97148, C4<1>, C4<1>;
|
||||
L_0000016d6fedba00 .functor OR 1, L_0000016d6fedb7d0, L_0000016d6fedb840, L_0000016d6fedb8b0, L_0000016d6fedb990;
|
||||
v0000016d6fd62b30_0 .net "A", 0 0, o0000016d6fd96f98; 0 drivers
|
||||
v0000016d6fd62d50_0 .net "AD", 0 0, L_0000016d6fedb8b0; 1 drivers
|
||||
v0000016d6fd62770_0 .net "An", 0 0, L_0000016d6fd62f70; 1 drivers
|
||||
v0000016d6fd62810_0 .net "AnBC", 0 0, L_0000016d6fedb7d0; 1 drivers
|
||||
v0000016d6fd628b0_0 .net "B", 0 0, o0000016d6fd97058; 0 drivers
|
||||
v0000016d6fededb0_0 .net "Bn", 0 0, L_0000016d6fedb840; 1 drivers
|
||||
v0000016d6fedee50_0 .net "C", 0 0, o0000016d6fd970b8; 0 drivers
|
||||
v0000016d6fedeef0_0 .net "Cn", 0 0, L_0000016d6fedb920; 1 drivers
|
||||
v0000016d6fedb600_0 .net "CnD", 0 0, L_0000016d6fedb990; 1 drivers
|
||||
v0000016d6fedb730_0 .net "D", 0 0, o0000016d6fd97148; 0 drivers
|
||||
v0000016d6fd90c30_0 .net "F", 0 0, L_0000016d6fedba00; 1 drivers
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 3;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"lab2.v";
|
||||
24
lab2_prep/src/lab2.v
Normal file
24
lab2_prep/src/lab2.v
Normal file
@ -0,0 +1,24 @@
|
||||
module lab2(
|
||||
input A,
|
||||
input B,
|
||||
input C,
|
||||
input D,
|
||||
output F
|
||||
);
|
||||
|
||||
wire An, Bn, Cn;
|
||||
wire AnBC, AD, CnD;
|
||||
|
||||
not n1 (An, A);
|
||||
and (AnBC, An, B, C);
|
||||
|
||||
not (Bn, B);
|
||||
and (AD, A, D);
|
||||
|
||||
not (Cn, C);
|
||||
and (CnD, Cn, D);
|
||||
|
||||
or (F, AnBC, Bn, AD, CnD);
|
||||
|
||||
|
||||
endmodule
|
||||
43
lab2_prep/src/labwave
Normal file
43
lab2_prep/src/labwave
Normal file
@ -0,0 +1,43 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000001e0df4625e0 .scope module, "f_lab2" "f_lab2" 2 1;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "C";
|
||||
.port_info 3 /INPUT 1 "D";
|
||||
.port_info 4 /OUTPUT 1 "F";
|
||||
o000001e0df496fd8 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_000001e0df462f70 .functor NOT 1, o000001e0df496fd8, C4<0>, C4<0>, C4<0>;
|
||||
o000001e0df497098 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
o000001e0df4970f8 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_000001e0df64aa10 .functor AND 1, L_000001e0df462f70, o000001e0df497098, o000001e0df4970f8, C4<1>;
|
||||
L_000001e0df64aa80 .functor NOT 1, o000001e0df497098, C4<0>, C4<0>, C4<0>;
|
||||
o000001e0df497188 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_000001e0df64aaf0 .functor AND 1, o000001e0df496fd8, o000001e0df497188, C4<1>, C4<1>;
|
||||
L_000001e0df64ab60 .functor NOT 1, o000001e0df4970f8, C4<0>, C4<0>, C4<0>;
|
||||
L_000001e0df64abd0 .functor AND 1, L_000001e0df64ab60, o000001e0df497188, C4<1>, C4<1>;
|
||||
L_000001e0df64ac40 .functor OR 1, L_000001e0df64aa10, L_000001e0df64aa80, L_000001e0df64aaf0, L_000001e0df64abd0;
|
||||
v000001e0df462b30_0 .net "A", 0 0, o000001e0df496fd8; 0 drivers
|
||||
v000001e0df462d50_0 .net "AD", 0 0, L_000001e0df64aaf0; 1 drivers
|
||||
v000001e0df462770_0 .net "An", 0 0, L_000001e0df462f70; 1 drivers
|
||||
v000001e0df462810_0 .net "AnBC", 0 0, L_000001e0df64aa10; 1 drivers
|
||||
v000001e0df4628b0_0 .net "B", 0 0, o000001e0df497098; 0 drivers
|
||||
v000001e0df64ed90_0 .net "Bn", 0 0, L_000001e0df64aa80; 1 drivers
|
||||
v000001e0df64ee30_0 .net "C", 0 0, o000001e0df4970f8; 0 drivers
|
||||
v000001e0df64eed0_0 .net "Cn", 0 0, L_000001e0df64ab60; 1 drivers
|
||||
v000001e0df64a840_0 .net "CnD", 0 0, L_000001e0df64abd0; 1 drivers
|
||||
v000001e0df64a970_0 .net "D", 0 0, o000001e0df497188; 0 drivers
|
||||
v000001e0df492660_0 .net "F", 0 0, L_000001e0df64ac40; 1 drivers
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 3;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
".\f_lab2.v";
|
||||
32
lab2_prep/src/tb.v
Normal file
32
lab2_prep/src/tb.v
Normal file
@ -0,0 +1,32 @@
|
||||
module tb();
|
||||
|
||||
reg r1, r2, r3, r4;
|
||||
wire w1;
|
||||
|
||||
lab2 uut(
|
||||
.A(r1),
|
||||
.B(r2),
|
||||
.C(r3),
|
||||
.D(r4),
|
||||
.F(w1)
|
||||
);
|
||||
|
||||
// test uut(r1, r2, w1, w2, w3);
|
||||
|
||||
initial begin
|
||||
$dumpfile("dmp.vcd");
|
||||
$dumpvars;
|
||||
r1 = 1'b0; r2 = 1'b0; r3 = 1'b0; r4 = 1'b0; #50;
|
||||
r1 = 1'b0; r2 = 1'b0; r3 = 1'b0; r4 = 1'b1; #50;
|
||||
r1 = 1'b0; r2 = 1'b0; r3 = 1'b1; r4 = 1'b0; #50;
|
||||
r1 = 1'b0; r2 = 1'b0; r3 = 1'b1; r4 = 1'b1; #50;
|
||||
r1 = 1'b0; r2 = 1'b1; r3 = 1'b0; r4 = 1'b0; #50;
|
||||
r1 = 1'b0; r2 = 1'b1; r3 = 1'b0; r4 = 1'b1; #50;
|
||||
r1 = 1'b0; r2 = 1'b1; r3 = 1'b1; r4 = 1'b0; #50;
|
||||
r1 = 1'b0; r2 = 1'b1; r3 = 1'b1; r4 = 1'b1; #50;
|
||||
$display(w1);
|
||||
end
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
23
lab3/impl/gwsynthesis/lab3.log
Normal file
23
lab3/impl/gwsynthesis/lab3.log
Normal file
@ -0,0 +1,23 @@
|
||||
GowinSynthesis start
|
||||
Running parser ...
|
||||
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v'
|
||||
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v'
|
||||
ERROR (EX3615) : '.name implicit port connection' is not allowed in this dialect, use SystemVerilog mode instead("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":7)
|
||||
ERROR (EX3863) : Syntax error near '['("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":7)
|
||||
ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
|
||||
ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
|
||||
ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
|
||||
ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
|
||||
ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
|
||||
ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
|
||||
ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
|
||||
ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
|
||||
ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
|
||||
ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
|
||||
ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
|
||||
ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
|
||||
ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
|
||||
ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
|
||||
ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
|
||||
Sorry, too many errors..
|
||||
GowinSynthesis finish
|
||||
20
lab3/impl/gwsynthesis/lab3.prj
Normal file
20
lab3/impl/gwsynthesis/lab3.prj
Normal file
@ -0,0 +1,20 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE gowin-synthesis-project>
|
||||
<Project>
|
||||
<Version>beta</Version>
|
||||
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
|
||||
<FileList>
|
||||
<File path="C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v" type="verilog"/>
|
||||
<File path="C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v" type="verilog"/>
|
||||
</FileList>
|
||||
<OptionList>
|
||||
<Option type="disable_insert_pad" value="0"/>
|
||||
<Option type="global_freq" value="100.000"/>
|
||||
<Option type="looplimit" value="2000"/>
|
||||
<Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg"/>
|
||||
<Option type="print_all_synthesis_warning" value="0"/>
|
||||
<Option type="ram_rw_check" value="0"/>
|
||||
<Option type="verilog_language" value="verilog-2001"/>
|
||||
<Option type="vhdl_language" value="vhdl-1993"/>
|
||||
</OptionList>
|
||||
</Project>
|
||||
125
lab3/impl/gwsynthesis/lab3.vg
Normal file
125
lab3/impl/gwsynthesis/lab3.vg
Normal file
@ -0,0 +1,125 @@
|
||||
//
|
||||
//Written by GowinSynthesis
|
||||
//Tool Version "V1.9.9.02"
|
||||
//Sat Apr 13 05:09:20 2024
|
||||
|
||||
//Source file index table:
|
||||
//file0 "\C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v"
|
||||
`timescale 100 ps/100 ps
|
||||
module Adder3Bit (
|
||||
num1,
|
||||
num2,
|
||||
Carry,
|
||||
sum
|
||||
)
|
||||
;
|
||||
input [2:0] num1;
|
||||
input [2:0] num2;
|
||||
output [2:0] Carry;
|
||||
output [2:0] sum;
|
||||
wire [2:0] num1_d;
|
||||
wire [2:0] num2_d;
|
||||
wire [2:0] sum_d;
|
||||
wire [2:0] Carry_d;
|
||||
wire VCC;
|
||||
wire GND;
|
||||
IBUF num1_0_ibuf (
|
||||
.O(num1_d[0]),
|
||||
.I(num1[0])
|
||||
);
|
||||
IBUF num1_1_ibuf (
|
||||
.O(num1_d[1]),
|
||||
.I(num1[1])
|
||||
);
|
||||
IBUF num1_2_ibuf (
|
||||
.O(num1_d[2]),
|
||||
.I(num1[2])
|
||||
);
|
||||
IBUF num2_0_ibuf (
|
||||
.O(num2_d[0]),
|
||||
.I(num2[0])
|
||||
);
|
||||
IBUF num2_1_ibuf (
|
||||
.O(num2_d[1]),
|
||||
.I(num2[1])
|
||||
);
|
||||
IBUF num2_2_ibuf (
|
||||
.O(num2_d[2]),
|
||||
.I(num2[2])
|
||||
);
|
||||
OBUF Carry_0_obuf (
|
||||
.O(Carry[0]),
|
||||
.I(Carry_d[0])
|
||||
);
|
||||
OBUF Carry_1_obuf (
|
||||
.O(Carry[1]),
|
||||
.I(Carry_d[1])
|
||||
);
|
||||
OBUF Carry_2_obuf (
|
||||
.O(Carry[2]),
|
||||
.I(Carry_d[2])
|
||||
);
|
||||
OBUF sum_0_obuf (
|
||||
.O(sum[0]),
|
||||
.I(sum_d[0])
|
||||
);
|
||||
OBUF sum_1_obuf (
|
||||
.O(sum[1]),
|
||||
.I(sum_d[1])
|
||||
);
|
||||
OBUF sum_2_obuf (
|
||||
.O(sum[2]),
|
||||
.I(sum_d[2])
|
||||
);
|
||||
LUT2 sum_d_0_s (
|
||||
.F(sum_d[0]),
|
||||
.I0(num1_d[0]),
|
||||
.I1(num2_d[0])
|
||||
);
|
||||
defparam sum_d_0_s.INIT=4'h6;
|
||||
LUT2 Carry_d_0_s (
|
||||
.F(Carry_d[0]),
|
||||
.I0(num1_d[0]),
|
||||
.I1(num2_d[0])
|
||||
);
|
||||
defparam Carry_d_0_s.INIT=4'h8;
|
||||
LUT4 Carry_d_1_s (
|
||||
.F(Carry_d[1]),
|
||||
.I0(num1_d[1]),
|
||||
.I1(num2_d[1]),
|
||||
.I2(num1_d[0]),
|
||||
.I3(num2_d[0])
|
||||
);
|
||||
defparam Carry_d_1_s.INIT=16'hE888;
|
||||
LUT3 sum_d_2_s (
|
||||
.F(sum_d[2]),
|
||||
.I0(Carry_d[1]),
|
||||
.I1(num1_d[2]),
|
||||
.I2(num2_d[2])
|
||||
);
|
||||
defparam sum_d_2_s.INIT=8'h96;
|
||||
LUT3 Carry_d_2_s (
|
||||
.F(Carry_d[2]),
|
||||
.I0(Carry_d[1]),
|
||||
.I1(num1_d[2]),
|
||||
.I2(num2_d[2])
|
||||
);
|
||||
defparam Carry_d_2_s.INIT=8'hE8;
|
||||
LUT4 sum_d_1_s0 (
|
||||
.F(sum_d[1]),
|
||||
.I0(num1_d[0]),
|
||||
.I1(num2_d[0]),
|
||||
.I2(num1_d[1]),
|
||||
.I3(num2_d[1])
|
||||
);
|
||||
defparam sum_d_1_s0.INIT=16'h8778;
|
||||
VCC VCC_cZ (
|
||||
.V(VCC)
|
||||
);
|
||||
GND GND_cZ (
|
||||
.G(GND)
|
||||
);
|
||||
GSR GSR (
|
||||
.GSRI(VCC)
|
||||
);
|
||||
endmodule /* Adder3Bit */
|
||||
175
lab3/impl/gwsynthesis/lab3_syn.rpt.html
Normal file
175
lab3/impl/gwsynthesis/lab3_syn.rpt.html
Normal file
@ -0,0 +1,175 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>synthesis Report</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
div#content { margin-left: 350px; margin-right: 30px; }
|
||||
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
|
||||
div#catalog ul { list-style-type: none; }
|
||||
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
|
||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
|
||||
div#catalog a:visited { color: #0084ff; }
|
||||
div#catalog a:hover { color: #fff; background: #0084ff; }
|
||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
|
||||
h1 {margin-top: 50px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table td.label { min-width: 100px; width: 8%;}
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
|
||||
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
|
||||
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
|
||||
<ul>
|
||||
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
|
||||
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
<div id="content">
|
||||
<h1><a name="about">Synthesis Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>GowinSynthesis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v<br>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">GowinSynthesis Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.9.02</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device Version</td>
|
||||
<td>C</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Sat Apr 13 05:09:20 2024
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="summary">Synthesis Details</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Top Level Module</td>
|
||||
<td>Adder3Bit</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Synthesis Process</td>
|
||||
<td>Running parser:<br/> CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.093s, Peak memory usage = 156.254MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 156.254MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 156.254MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 156.254MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 156.254MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 156.254MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 156.254MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.301s, Peak memory usage = 172.207MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 172.207MB<br/>Generate output files:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 172.207MB<br/></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
|
||||
<td>CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.483s, Peak memory usage = 172.207MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="resource">Resource</a></h1>
|
||||
<h2><a name="usage">Resource Usage Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Port </b></td>
|
||||
<td>12</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Buf </b></td>
|
||||
<td>12</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    IBUF</td>
|
||||
<td>6</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    OBUF</td>
|
||||
<td>6</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>LUT </b></td>
|
||||
<td>6</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT2</td>
|
||||
<td>2</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT3</td>
|
||||
<td>2</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT4</td>
|
||||
<td>2</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="utilization">Resource Utilization Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
<td><b>Utilization</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>6(6 LUT, 0 ALU) / 20736</td>
|
||||
<td><1%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Register</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as Latch</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as FF</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BSRAM</td>
|
||||
<td>0 / 46</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
46
lab3/impl/gwsynthesis/lab3_syn_resource.html
Normal file
46
lab3/impl/gwsynthesis/lab3_syn_resource.html
Normal file
@ -0,0 +1,46 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Hierarchy Module Resource</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
h1 {text-align: center; }
|
||||
h1 {margin-top: 36px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { align = "center"; padding: 5px 2px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="content">
|
||||
<h1>Hierarchy Module Resource</h1>
|
||||
<table>
|
||||
<tr>
|
||||
<th class="label">MODULE NAME</th>
|
||||
<th class="label">REG NUMBER</th>
|
||||
<th class="label">ALU NUMBER</th>
|
||||
<th class="label">LUT NUMBER</th>
|
||||
<th class="label">DSP NUMBER</th>
|
||||
<th class="label">BSRAM NUMBER</th>
|
||||
<th class="label">SSRAM NUMBER</th>
|
||||
<th class="label">ROM16 NUMBER</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Adder3Bit (C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">6</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
2
lab3/impl/gwsynthesis/lab3_syn_rsc.xml
Normal file
2
lab3/impl/gwsynthesis/lab3_syn_rsc.xml
Normal file
@ -0,0 +1,2 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Module name="Adder3Bit" Lut="6" T_Lut="6(6)"/>
|
||||
88
lab3/impl/lab3_process_config.json
Normal file
88
lab3/impl/lab3_process_config.json
Normal file
@ -0,0 +1,88 @@
|
||||
{
|
||||
"BACKGROUND_PROGRAMMING" : "off",
|
||||
"COMPRESS" : false,
|
||||
"CPU" : false,
|
||||
"CRC_CHECK" : true,
|
||||
"Clock_Route_Order" : 0,
|
||||
"Correct_Hold_Violation" : true,
|
||||
"DONE" : false,
|
||||
"DOWNLOAD_SPEED" : "default",
|
||||
"Disable_Insert_Pad" : false,
|
||||
"ENABLE_CTP" : false,
|
||||
"ENABLE_MERGE_MODE" : false,
|
||||
"ENCRYPTION_KEY" : false,
|
||||
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
|
||||
"ERROR_DECTION_AND_CORRECTION" : false,
|
||||
"ERROR_DECTION_ONLY" : false,
|
||||
"ERROR_INJECTION" : false,
|
||||
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
|
||||
"Enable_DSRM" : false,
|
||||
"FORMAT" : "binary",
|
||||
"FREQUENCY_DIVIDER" : "",
|
||||
"Generate_Constraint_File_of_Ports" : false,
|
||||
"Generate_IBIS_File" : false,
|
||||
"Generate_Plain_Text_Timing_Report" : false,
|
||||
"Generate_Post_PNR_Simulation_Model_File" : false,
|
||||
"Generate_Post_Place_File" : false,
|
||||
"Generate_SDF_File" : false,
|
||||
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
|
||||
"Global_Freq" : "default",
|
||||
"GwSyn_Loop_Limit" : 2000,
|
||||
"HOTBOOT" : false,
|
||||
"I2C" : false,
|
||||
"I2C_SLAVE_ADDR" : "00",
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"Incremental_Compile" : "",
|
||||
"Initialize_Primitives" : false,
|
||||
"JTAG" : false,
|
||||
"MODE_IO" : false,
|
||||
"MSPI" : false,
|
||||
"MSPI_JUMP" : false,
|
||||
"MULTIBOOT_ADDRESS_WIDTH" : "24",
|
||||
"MULTIBOOT_MODE" : "Normal",
|
||||
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
|
||||
"MULTIJUMP_ADDRESS_WIDTH" : "24",
|
||||
"MULTIJUMP_MODE" : "Normal",
|
||||
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
|
||||
"Multi_Boot" : true,
|
||||
"OUTPUT_BASE_NAME" : "lab3",
|
||||
"POWER_ON_RESET_MONITOR" : true,
|
||||
"PRINT_BSRAM_VALUE" : true,
|
||||
"PROGRAM_DONE_BYPASS" : false,
|
||||
"PlaceInRegToIob" : true,
|
||||
"PlaceIoRegToIob" : true,
|
||||
"PlaceOutRegToIob" : true,
|
||||
"Place_Option" : "0",
|
||||
"Process_Configuration_Verion" : "1.0",
|
||||
"Promote_Physical_Constraint_Warning_to_Error" : true,
|
||||
"READY" : false,
|
||||
"RECONFIG_N" : false,
|
||||
"Ram_RW_Check" : false,
|
||||
"Replicate_Resources" : false,
|
||||
"Report_Auto-Placed_Io_Information" : false,
|
||||
"Route_Maxfan" : 23,
|
||||
"Route_Option" : "0",
|
||||
"Run_Timing_Driven" : true,
|
||||
"SECURE_MODE" : false,
|
||||
"SECURITY_BIT" : true,
|
||||
"SEU_HANDLER" : false,
|
||||
"SEU_HANDLER_CHECKSUM" : false,
|
||||
"SEU_HANDLER_MODE" : "auto",
|
||||
"SSPI" : false,
|
||||
"STOP_SEU_HANDLER" : false,
|
||||
"Show_All_Warnings" : false,
|
||||
"Synthesize_tool" : "GowinSyn",
|
||||
"TclPre" : "",
|
||||
"TopModule" : "",
|
||||
"USERCODE" : "default",
|
||||
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
|
||||
"VCCAUX" : 3.3,
|
||||
"VCCX" : "3.3",
|
||||
"VHDL_Standard" : "VHDL_Std_1993",
|
||||
"Verilog_Standard" : "Vlg_Std_2001",
|
||||
"WAKE_UP" : "0",
|
||||
"show_all_warnings" : false,
|
||||
"turn_off_bg" : false
|
||||
}
|
||||
10
lab3/impl/temp/rtl_parser.result
Normal file
10
lab3/impl/temp/rtl_parser.result
Normal file
@ -0,0 +1,10 @@
|
||||
[
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
|
||||
"InstLine" : 1,
|
||||
"InstName" : "Adder3Bit",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "Adder3Bit"
|
||||
}
|
||||
]
|
||||
21
lab3/impl/temp/rtl_parser_arg.json
Normal file
21
lab3/impl/temp/rtl_parser_arg.json
Normal file
@ -0,0 +1,21 @@
|
||||
{
|
||||
"Device" : "GW2A-18C",
|
||||
"Files" : [
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab3/src/tbAdder3Bit.v",
|
||||
"Type" : "verilog"
|
||||
}
|
||||
],
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"LoopLimit" : 2000,
|
||||
"ResultFile" : "C:/cygwin64/home/koray/verilog/lab3/impl/temp/rtl_parser.result",
|
||||
"Top" : "",
|
||||
"VerilogStd" : "verilog_2001",
|
||||
"VhdlStd" : "vhdl_93"
|
||||
}
|
||||
11
lab3/lab3.gprj
Normal file
11
lab3/lab3.gprj
Normal file
@ -0,0 +1,11 @@
|
||||
<?xml version="1" encoding="UTF-8"?>
|
||||
<!DOCTYPE gowin-fpga-project>
|
||||
<Project>
|
||||
<Template>FPGA</Template>
|
||||
<Version>5</Version>
|
||||
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
|
||||
<FileList>
|
||||
<File path="src/Adder3Bit.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/tbAdder3Bit.v" type="file.verilog" enable="1"/>
|
||||
</FileList>
|
||||
</Project>
|
||||
13
lab3/lab3.gprj.user
Normal file
13
lab3/lab3.gprj.user
Normal file
@ -0,0 +1,13 @@
|
||||
<?xml version="1" encoding="UTF-8"?>
|
||||
<!DOCTYPE ProjectUserData>
|
||||
<UserConfig>
|
||||
<Version>1.0</Version>
|
||||
<FlowState>
|
||||
<Process ID="Synthesis" State="3"/>
|
||||
<Process ID="Pnr" State="0"/>
|
||||
<Process ID="Gao" State="0"/>
|
||||
<Process ID="Rtl_Gao" State="2"/>
|
||||
</FlowState>
|
||||
<ResultFileList/>
|
||||
<Ui>000000ff00000001fd00000002000000000000017000000281fc0200000001fc00000063000002810000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000078000000121fc0100000001fc0000000000000780000000a100fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000007800fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100ffffff000006080000028100000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000</Ui>
|
||||
</UserConfig>
|
||||
30
lab3/src/Adder3Bit.v
Normal file
30
lab3/src/Adder3Bit.v
Normal file
@ -0,0 +1,30 @@
|
||||
module Adder3Bit (
|
||||
input [2:0] num1,
|
||||
input [2:0] num2,
|
||||
output [2:0] Carry,
|
||||
output [2:0] sum
|
||||
);
|
||||
|
||||
xor (sum[0], num1[0], num2[0]);
|
||||
and (Carry[0], num1[0], num2[0]);
|
||||
|
||||
wire num12[1:0];
|
||||
wire num12Carry[1:0], num1a2[1:0];
|
||||
|
||||
xor (num12[0], num1[1], num2[1]);
|
||||
xor (sum[1], num12[0], Carry[0]);
|
||||
|
||||
and (num12Carry[0], num12[0], Carry[0]);
|
||||
and (num1a2[0], num1[1], num2[1]);
|
||||
|
||||
or (Carry[1], num12Carry[0], num1a2[0]);
|
||||
|
||||
xor (num12[1], num1[2], num2[2]);
|
||||
xor (sum[2], num12[1], Carry[1]);
|
||||
|
||||
and (num12Carry[1], num12[1], Carry[1]);
|
||||
and (num1a2[1], num1[2], num2[2]);
|
||||
|
||||
or (Carry[2], num12Carry[1], num1a2[1]);
|
||||
|
||||
endmodule
|
||||
28
lab3/src/tbAdder3Bit.v
Normal file
28
lab3/src/tbAdder3Bit.v
Normal file
@ -0,0 +1,28 @@
|
||||
module tbAdder3Bit ();
|
||||
|
||||
reg r1[2:0], r2[2:0];
|
||||
wire w1[2:0], w2[2:0];
|
||||
|
||||
Adder3Bit uut(
|
||||
.num1[2:0](r1[2:0]),
|
||||
.num2[2:0](r2[2:0]),
|
||||
.sum[2:0](w1[2:0]),
|
||||
.Carry[2:0](w2[2:0])
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("Admp.vcd");
|
||||
$dumpvars;
|
||||
r1 = 3'b000; r2 = 3'b000; #10
|
||||
r1 = 3'b001; r2 = 3'b001; #10
|
||||
r1 = 3'b010; r2 = 3'b010; #10
|
||||
r1 = 3'b100; r2 = 3'b100; #10
|
||||
r1 = 3'b011; r2 = 3'b011; #10
|
||||
r1 = 3'b101; r2 = 3'b101; #10
|
||||
r1 = 3'b110; r2 = 3'b110; #10
|
||||
r1 = 3'b111; r2 = 3'b111; #10
|
||||
$display(w1[2:0]);
|
||||
$display(w2[2:0]);
|
||||
end
|
||||
|
||||
endmodule
|
||||
65
test/a.out
Normal file
65
test/a.out
Normal file
@ -0,0 +1,65 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000001c04a3a6760 .scope module, "tb" "tb" 2 1;
|
||||
.timescale 0 0;
|
||||
v000001c04a3a6b20_0 .var "r1", 0 0;
|
||||
v000001c04a51ba60_0 .var "r2", 0 0;
|
||||
v000001c04a51bb00_0 .net "w1", 0 0, L_000001c04a518b00; 1 drivers
|
||||
v000001c04a51bba0_0 .net "w2", 0 0, L_000001c04a518d50; 1 drivers
|
||||
v000001c04a51bc40_0 .net "w3", 0 0, L_000001c04a517170; 1 drivers
|
||||
S_000001c04a3a68f0 .scope module, "uut" "test" 2 6, 3 1 0, S_000001c04a3a6760;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "LED1";
|
||||
.port_info 3 /OUTPUT 1 "LED2";
|
||||
.port_info 4 /OUTPUT 1 "LED3";
|
||||
L_000001c04a518b00 .functor BUFZ 1, v000001c04a3a6b20_0, C4<0>, C4<0>, C4<0>;
|
||||
L_000001c04a518d50 .functor BUFZ 1, v000001c04a51ba60_0, C4<0>, C4<0>, C4<0>;
|
||||
L_000001c04a517170 .functor OR 1, v000001c04a3a6b20_0, v000001c04a51ba60_0, C4<0>, C4<0>;
|
||||
v000001c04a519860_0 .net "A", 0 0, v000001c04a3a6b20_0; 1 drivers
|
||||
v000001c04a516ec0_0 .net "B", 0 0, v000001c04a51ba60_0; 1 drivers
|
||||
v000001c04a518cb0_0 .net "LED1", 0 0, L_000001c04a518b00; alias, 1 drivers
|
||||
v000001c04a518a60_0 .net "LED2", 0 0, L_000001c04a518d50; alias, 1 drivers
|
||||
v000001c04a3a6a80_0 .net "LED3", 0 0, L_000001c04a517170; alias, 1 drivers
|
||||
.scope S_000001c04a3a6760;
|
||||
T_0 ;
|
||||
%vpi_call 2 17 "$dumpfile", "dmp.vcd" {0 0 0};
|
||||
%vpi_call 2 18 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001c04a3a6b20_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001c04a51ba60_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001c04a3a6b20_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001c04a51ba60_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001c04a3a6b20_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001c04a51ba60_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 22 "$display", v000001c04a51bc40_0 {0 0 0};
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001c04a3a6b20_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001c04a51ba60_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 24 "$display", v000001c04a51bc40_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"tb.v";
|
||||
"test.v";
|
||||
48
test/dmp.vcd
Normal file
48
test/dmp.vcd
Normal file
@ -0,0 +1,48 @@
|
||||
$date
|
||||
Sat Apr 06 17:45:47 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module tb $end
|
||||
$var wire 1 ! w3 $end
|
||||
$var wire 1 " w2 $end
|
||||
$var wire 1 # w1 $end
|
||||
$var reg 1 $ r1 $end
|
||||
$var reg 1 % r2 $end
|
||||
$scope module uut $end
|
||||
$var wire 1 $ A $end
|
||||
$var wire 1 % B $end
|
||||
$var wire 1 # LED1 $end
|
||||
$var wire 1 " LED2 $end
|
||||
$var wire 1 ! LED3 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
0"
|
||||
0!
|
||||
$end
|
||||
#10
|
||||
1!
|
||||
1"
|
||||
1%
|
||||
#20
|
||||
0"
|
||||
0%
|
||||
1#
|
||||
1$
|
||||
#30
|
||||
1"
|
||||
1%
|
||||
#40
|
||||
29
test/tb.v
Normal file
29
test/tb.v
Normal file
@ -0,0 +1,29 @@
|
||||
module tb();
|
||||
|
||||
reg r1, r2;
|
||||
wire w1, w2, w3;
|
||||
|
||||
test uut(
|
||||
.A(r1),
|
||||
.B(r2),
|
||||
.LED1(w1),
|
||||
.LED2(w2),
|
||||
.LED3(w3)
|
||||
);
|
||||
|
||||
// test uut(r1, r2, w1, w2, w3);
|
||||
|
||||
initial begin
|
||||
$dumpfile("dmp.vcd");
|
||||
$dumpvars;
|
||||
r1 = 0; r2 = 0; #10;
|
||||
r1 = 0; r2 = 1; #10;
|
||||
r1 = 1; r2 = 0; #10;
|
||||
$display(w3);
|
||||
r1 = 1; r2 = 1; #10;
|
||||
$display(w3);
|
||||
end
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
20
test/test.v
Normal file
20
test/test.v
Normal file
@ -0,0 +1,20 @@
|
||||
module test(
|
||||
input A,
|
||||
input B,
|
||||
output LED1,
|
||||
output LED2,
|
||||
output LED3
|
||||
);
|
||||
|
||||
|
||||
assign LED1 = A;
|
||||
assign LED2 = B;
|
||||
assign LED3 = A | B;
|
||||
|
||||
/*
|
||||
buf(LED1, A);
|
||||
buf(LED2, B);
|
||||
and(LED3, A, B);
|
||||
*/
|
||||
|
||||
endmodule
|
||||
Loading…
x
Reference in New Issue
Block a user