verilog/lab3/impl/temp/rtl_parser.result
2024-04-13 05:48:55 +03:00

10 lines
246 B
Plaintext

[
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
"InstLine" : 1,
"InstName" : "Adder3Bit",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
"ModuleLine" : 1,
"ModuleName" : "Adder3Bit"
}
]