32 lines
676 B
Verilog
32 lines
676 B
Verilog
module tb();
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reg r1, r2, r3, r4;
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wire w1;
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lab2 uut(
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.A(r1),
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.B(r2),
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.C(r3),
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.D(r4),
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.F(w1)
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);
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// test uut(r1, r2, w1, w2, w3);
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initial begin
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$dumpfile("dmp.vcd");
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$dumpvars;
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r1 = 1'b0; r2 = 1'b0; r3 = 1'b0; r4 = 1'b0; #50;
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r1 = 1'b0; r2 = 1'b0; r3 = 1'b0; r4 = 1'b1; #50;
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r1 = 1'b0; r2 = 1'b0; r3 = 1'b1; r4 = 1'b0; #50;
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r1 = 1'b0; r2 = 1'b0; r3 = 1'b1; r4 = 1'b1; #50;
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r1 = 1'b0; r2 = 1'b1; r3 = 1'b0; r4 = 1'b0; #50;
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r1 = 1'b0; r2 = 1'b1; r3 = 1'b0; r4 = 1'b1; #50;
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r1 = 1'b0; r2 = 1'b1; r3 = 1'b1; r4 = 1'b0; #50;
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r1 = 1'b0; r2 = 1'b1; r3 = 1'b1; r4 = 1'b1; #50;
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$display(w1);
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end
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endmodule |