126 lines
2.0 KiB
Plaintext
126 lines
2.0 KiB
Plaintext
//
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//Written by GowinSynthesis
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//Tool Version "V1.9.9.02"
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//Sat Apr 13 05:09:20 2024
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//Source file index table:
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//file0 "\C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v"
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`timescale 100 ps/100 ps
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module Adder3Bit (
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num1,
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num2,
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Carry,
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sum
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)
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;
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input [2:0] num1;
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input [2:0] num2;
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output [2:0] Carry;
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output [2:0] sum;
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wire [2:0] num1_d;
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wire [2:0] num2_d;
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wire [2:0] sum_d;
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wire [2:0] Carry_d;
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wire VCC;
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wire GND;
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IBUF num1_0_ibuf (
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.O(num1_d[0]),
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.I(num1[0])
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);
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IBUF num1_1_ibuf (
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.O(num1_d[1]),
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.I(num1[1])
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);
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IBUF num1_2_ibuf (
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.O(num1_d[2]),
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.I(num1[2])
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);
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IBUF num2_0_ibuf (
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.O(num2_d[0]),
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.I(num2[0])
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);
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IBUF num2_1_ibuf (
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.O(num2_d[1]),
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.I(num2[1])
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);
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IBUF num2_2_ibuf (
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.O(num2_d[2]),
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.I(num2[2])
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);
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OBUF Carry_0_obuf (
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.O(Carry[0]),
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.I(Carry_d[0])
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);
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OBUF Carry_1_obuf (
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.O(Carry[1]),
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.I(Carry_d[1])
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);
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OBUF Carry_2_obuf (
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.O(Carry[2]),
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.I(Carry_d[2])
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);
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OBUF sum_0_obuf (
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.O(sum[0]),
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.I(sum_d[0])
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);
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OBUF sum_1_obuf (
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.O(sum[1]),
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.I(sum_d[1])
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);
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OBUF sum_2_obuf (
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.O(sum[2]),
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.I(sum_d[2])
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);
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LUT2 sum_d_0_s (
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.F(sum_d[0]),
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.I0(num1_d[0]),
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.I1(num2_d[0])
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);
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defparam sum_d_0_s.INIT=4'h6;
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LUT2 Carry_d_0_s (
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.F(Carry_d[0]),
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.I0(num1_d[0]),
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.I1(num2_d[0])
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);
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defparam Carry_d_0_s.INIT=4'h8;
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LUT4 Carry_d_1_s (
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.F(Carry_d[1]),
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.I0(num1_d[1]),
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.I1(num2_d[1]),
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.I2(num1_d[0]),
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.I3(num2_d[0])
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);
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defparam Carry_d_1_s.INIT=16'hE888;
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LUT3 sum_d_2_s (
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.F(sum_d[2]),
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.I0(Carry_d[1]),
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.I1(num1_d[2]),
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.I2(num2_d[2])
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);
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defparam sum_d_2_s.INIT=8'h96;
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LUT3 Carry_d_2_s (
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.F(Carry_d[2]),
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.I0(Carry_d[1]),
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.I1(num1_d[2]),
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.I2(num2_d[2])
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);
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defparam Carry_d_2_s.INIT=8'hE8;
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LUT4 sum_d_1_s0 (
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.F(sum_d[1]),
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.I0(num1_d[0]),
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.I1(num2_d[0]),
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.I2(num1_d[1]),
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.I3(num2_d[1])
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);
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defparam sum_d_1_s0.INIT=16'h8778;
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VCC VCC_cZ (
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.V(VCC)
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);
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GND GND_cZ (
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.G(GND)
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);
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GSR GSR (
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.GSRI(VCC)
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);
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endmodule /* Adder3Bit */
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