20 lines
211 B
Verilog
20 lines
211 B
Verilog
module test(
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input A,
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input B,
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output LED1,
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output LED2,
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output LED3
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);
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assign LED1 = A;
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assign LED2 = B;
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assign LED3 = A | B;
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/*
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buf(LED1, A);
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buf(LED2, B);
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and(LED3, A, B);
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*/
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endmodule |