41 lines
2.7 KiB
Plaintext
41 lines
2.7 KiB
Plaintext
GowinSynthesis start
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Running parser ...
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\lab2.v'
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\tb.v'
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Compiling module 'tb'("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":1)
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WARN (EX3858) : System task 'dumpfile' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":17)
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WARN (EX3858) : System task 'dumpvars' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":18)
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WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":19)
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WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":20)
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WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":21)
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WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":22)
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WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":23)
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WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":24)
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WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":25)
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WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":26)
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WARN (EX3858) : System task 'display' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":27)
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WARN (EX3780) : Using initial value of 'r1' since it is never assigned("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":28)
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Compiling module 'lab2'("C:\cygwin64\home\koray\verilog\lab2\src\lab2.v":1)
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NOTE (EX0101) : Current top module is "tb"
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WARN (EX0203) : Top module "tb" has no ports("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":1)
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[5%] Running netlist conversion ...
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Running device independent optimization ...
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[10%] Optimizing Phase 0 completed
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[15%] Optimizing Phase 1 completed
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[25%] Optimizing Phase 2 completed
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Running inference ...
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[30%] Inferring Phase 0 completed
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[40%] Inferring Phase 1 completed
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[50%] Inferring Phase 2 completed
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[55%] Inferring Phase 3 completed
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Running technical mapping ...
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[60%] Tech-Mapping Phase 0 completed
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[65%] Tech-Mapping Phase 1 completed
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[75%] Tech-Mapping Phase 2 completed
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[80%] Tech-Mapping Phase 3 completed
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[90%] Tech-Mapping Phase 4 completed
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WARN (NL0002) : The module "lab2" instantiated to "uut" is swept in optimizing("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":12)
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[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg" completed
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[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2_syn.rpt.html" completed
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GowinSynthesis finish
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