commit ed465dd690ef4beedad8a07703c9011cc86365fe Author: k0rrluna Date: Sat Apr 13 05:48:55 2024 +0300 verilog diff --git a/a.out b/a.out new file mode 100644 index 0000000..c77a3e8 --- /dev/null +++ b/a.out @@ -0,0 +1,60 @@ +#! /c/Source/iverilog-install/bin/vvp +:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "C:\iverilog\lib\ivl\system.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi"; +:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi"; +:vpi_module "C:\iverilog\lib\ivl\va_math.vpi"; +S_0000014670375350 .scope module, "hello" "hello" 2 1; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /INPUT 1 "B"; + .port_info 2 /OUTPUT 1 "C"; + .port_info 3 /OUTPUT 1 "D"; +o0000014670376fd8 .functor BUFZ 1, C4; HiZ drive +o0000014670377008 .functor BUFZ 1, C4; HiZ drive +L_0000014670326ea0 .functor AND 1, o0000014670376fd8, o0000014670377008, C4<1>, C4<1>; +L_0000014670327320 .functor XOR 1, o0000014670376fd8, o0000014670377008, C4<0>, C4<0>; +v00000146703270e0_0 .net "A", 0 0, o0000014670376fd8; 0 drivers +v0000014670375670_0 .net "B", 0 0, o0000014670377008; 0 drivers +v0000014670375710_0 .net "C", 0 0, L_0000014670327320; 1 drivers +v000001467032ee60_0 .net "D", 0 0, L_0000014670326ea0; 1 drivers +S_00000146703754e0 .scope module, "hello_tb" "hello_tb" 3 1; + .timescale 0 0; +v000001467032ef00_0 .var "A", 0 0; +v000001467032b870_0 .var "B", 0 0; + .scope S_00000146703754e0; +T_0 ; + %vpi_call 3 8 "$dumpfile", "dmp.vcd" {0 0 0}; + %vpi_call 3 9 "$dumpvars" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001467032ef00_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001467032b870_0, 0, 1; + %delay 10, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001467032ef00_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001467032b870_0, 0, 1; + %delay 10, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001467032ef00_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001467032b870_0, 0, 1; + %delay 10, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001467032ef00_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001467032b870_0, 0, 1; + %delay 10, 0; + %vpi_call 3 14 "$finish" {0 0 0}; + %end; + .thread T_0; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "hello.v"; + "hello_tb.v"; diff --git a/dmp.vcd b/dmp.vcd new file mode 100644 index 0000000..071bcbc --- /dev/null +++ b/dmp.vcd @@ -0,0 +1,40 @@ +$date + Sat Apr 06 17:40:37 2024 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module hello $end +$var wire 1 ! A $end +$var wire 1 " B $end +$var wire 1 # C $end +$var wire 1 $ D $end +$upscope $end +$scope module hello_tb $end +$var reg 1 % A $end +$var reg 1 & B $end +$upscope $end +$enddefinitions $end +$comment Show the parameter values. $end +$dumpall +$end +#0 +$dumpvars +0& +0% +x$ +x# +z" +z! +$end +#10 +1& +#20 +0& +1% +#30 +1& +#40 diff --git a/hello.v b/hello.v new file mode 100644 index 0000000..36f5671 --- /dev/null +++ b/hello.v @@ -0,0 +1,9 @@ +module hello( + input wire A, B, + output wire C, D +); + +and(D, A, B); +xor(C, A, B); + +endmodule diff --git a/hello_tb.v b/hello_tb.v new file mode 100644 index 0000000..57d3f5e --- /dev/null +++ b/hello_tb.v @@ -0,0 +1,17 @@ +module hello_tb(); + +reg A; +reg B; +wire C, D; + +initial begin + $dumpfile("dmp.vcd"); + $dumpvars; + A = 0; B = 0; #10; + A = 0; B = 1; #10; + A = 1; B = 0; #10; + A = 1; B = 1; #10; + $finish; +end + +endmodule diff --git a/lab2/impl/gwsynthesis/lab2.log b/lab2/impl/gwsynthesis/lab2.log new file mode 100644 index 0000000..1fc9053 --- /dev/null +++ b/lab2/impl/gwsynthesis/lab2.log @@ -0,0 +1,24 @@ +GowinSynthesis start +Running parser ... +Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\BitM.v' +Compiling module 'BitM'("C:\cygwin64\home\koray\verilog\lab2\src\BitM.v":1) +NOTE (EX0101) : Current top module is "BitM" +[5%] Running netlist conversion ... +Running device independent optimization ... +[10%] Optimizing Phase 0 completed +[15%] Optimizing Phase 1 completed +[25%] Optimizing Phase 2 completed +Running inference ... +[30%] Inferring Phase 0 completed +[40%] Inferring Phase 1 completed +[50%] Inferring Phase 2 completed +[55%] Inferring Phase 3 completed +Running technical mapping ... +[60%] Tech-Mapping Phase 0 completed +[65%] Tech-Mapping Phase 1 completed +[75%] Tech-Mapping Phase 2 completed +[80%] Tech-Mapping Phase 3 completed +[90%] Tech-Mapping Phase 4 completed +[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg" completed +[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2_syn.rpt.html" completed +GowinSynthesis finish diff --git a/lab2/impl/gwsynthesis/lab2.prj b/lab2/impl/gwsynthesis/lab2.prj new file mode 100644 index 0000000..91d8fd3 --- /dev/null +++ b/lab2/impl/gwsynthesis/lab2.prj @@ -0,0 +1,19 @@ + + + + beta + + + + + + + diff --git a/lab2/impl/gwsynthesis/lab2.vg b/lab2/impl/gwsynthesis/lab2.vg new file mode 100644 index 0000000..bdc651b --- /dev/null +++ b/lab2/impl/gwsynthesis/lab2.vg @@ -0,0 +1,76 @@ +// +//Written by GowinSynthesis +//Tool Version "V1.9.9.02" +//Thu Apr 11 07:46:56 2024 + +//Source file index table: +//file0 "\C:/cygwin64/home/koray/verilog/lab2/src/BitM.v" +`timescale 100 ps/100 ps +module BitM ( + A, + B, + AlB, + AeB, + AgB +) +; +input A; +input B; +output AlB; +output AeB; +output AgB; +wire A_d; +wire B_d; +wire AlB_d; +wire AgB_d; +wire AeB_d; +wire VCC; +wire GND; + IBUF A_ibuf ( + .O(A_d), + .I(A) +); + IBUF B_ibuf ( + .O(B_d), + .I(B) +); + OBUF AlB_obuf ( + .O(AlB), + .I(AlB_d) +); + OBUF AeB_obuf ( + .O(AeB), + .I(AeB_d) +); + OBUF AgB_obuf ( + .O(AgB), + .I(AgB_d) +); + LUT2 AlB_d_s ( + .F(AlB_d), + .I0(A_d), + .I1(B_d) +); +defparam AlB_d_s.INIT=4'h4; + LUT2 AgB_d_s ( + .F(AgB_d), + .I0(B_d), + .I1(A_d) +); +defparam AgB_d_s.INIT=4'h4; + LUT2 AeB_d_s ( + .F(AeB_d), + .I0(A_d), + .I1(B_d) +); +defparam AeB_d_s.INIT=4'h9; + VCC VCC_cZ ( + .V(VCC) +); + GND GND_cZ ( + .G(GND) +); + GSR GSR ( + .GSRI(VCC) +); +endmodule /* BitM */ diff --git a/lab2/impl/gwsynthesis/lab2_syn.rpt.html b/lab2/impl/gwsynthesis/lab2_syn.rpt.html new file mode 100644 index 0000000..3a652db --- /dev/null +++ b/lab2/impl/gwsynthesis/lab2_syn.rpt.html @@ -0,0 +1,167 @@ + + + +synthesis Report + + + +
+ +
+

Synthesis Messages

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Report TitleGowinSynthesis Report
Design FileC:\cygwin64\home\koray\verilog\lab2\src\BitM.v
+
GowinSynthesis Constraints File---
Tool VersionV1.9.9.02
Part NumberGW2A-LV18PG256C8/I7
DeviceGW2A-18
Device VersionC
Created TimeThu Apr 11 07:46:56 2024 +
Legal AnnouncementCopyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.
+

Synthesis Details

+ + + + + + + + + + + + + +
Top Level ModuleBitM
Synthesis ProcessRunning parser:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 181.887MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.132s, Peak memory usage = 181.887MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 181.887MB
Total Time and Memory UsageCPU time = 0h 0m 0.108s, Elapsed time = 0h 0m 0.221s, Peak memory usage = 181.887MB
+

Resource

+

Resource Usage Summary

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ResourceUsage
I/O Port 5
I/O Buf 5
    IBUF2
    OBUF3
LUT 3
    LUT23
+

Resource Utilization Summary

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ResourceUsageUtilization
Logic3(3 LUT, 0 ALU) / 20736<1%
Register0 / 161730%
  --Register as Latch0 / 161730%
  --Register as FF0 / 161730%
BSRAM0 / 460%
+
+
+ + diff --git a/lab2/impl/gwsynthesis/lab2_syn_resource.html b/lab2/impl/gwsynthesis/lab2_syn_resource.html new file mode 100644 index 0000000..5cfaeb6 --- /dev/null +++ b/lab2/impl/gwsynthesis/lab2_syn_resource.html @@ -0,0 +1,46 @@ + + + +Hierarchy Module Resource + + + +
+
+

Hierarchy Module Resource

+ + + + + + + + + + + + + + + + + + + + + +
MODULE NAMEREG NUMBERALU NUMBERLUT NUMBERDSP NUMBERBSRAM NUMBERSSRAM NUMBERROM16 NUMBER
BitM (C:/cygwin64/home/koray/verilog/lab2/src/BitM.v)--3----
+
+
+ + diff --git a/lab2/impl/gwsynthesis/lab2_syn_rsc.xml b/lab2/impl/gwsynthesis/lab2_syn_rsc.xml new file mode 100644 index 0000000..0303691 --- /dev/null +++ b/lab2/impl/gwsynthesis/lab2_syn_rsc.xml @@ -0,0 +1,2 @@ + + diff --git a/lab2/impl/lab2_process_config.json b/lab2/impl/lab2_process_config.json new file mode 100644 index 0000000..e4d68ba --- /dev/null +++ b/lab2/impl/lab2_process_config.json @@ -0,0 +1,88 @@ +{ + "BACKGROUND_PROGRAMMING" : "off", + "COMPRESS" : false, + "CPU" : false, + "CRC_CHECK" : true, + "Clock_Route_Order" : 0, + "Correct_Hold_Violation" : true, + "DONE" : false, + "DOWNLOAD_SPEED" : "default", + "Disable_Insert_Pad" : false, + "ENABLE_CTP" : false, + "ENABLE_MERGE_MODE" : false, + "ENCRYPTION_KEY" : false, + "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000", + "ERROR_DECTION_AND_CORRECTION" : false, + "ERROR_DECTION_ONLY" : false, + "ERROR_INJECTION" : false, + "EXTERNAL_MASTER_CONFIG_CLOCK" : false, + "Enable_DSRM" : false, + "FORMAT" : "binary", + "FREQUENCY_DIVIDER" : "", + "Generate_Constraint_File_of_Ports" : false, + "Generate_IBIS_File" : false, + "Generate_Plain_Text_Timing_Report" : false, + "Generate_Post_PNR_Simulation_Model_File" : false, + "Generate_Post_Place_File" : false, + "Generate_SDF_File" : false, + "Generate_VHDL_Post_PNR_Simulation_Model_File" : false, + "Global_Freq" : "default", + "GwSyn_Loop_Limit" : 2000, + "HOTBOOT" : false, + "I2C" : false, + "I2C_SLAVE_ADDR" : "00", + "IncludePath" : [ + + ], + "Incremental_Compile" : "", + "Initialize_Primitives" : false, + "JTAG" : false, + "MODE_IO" : false, + "MSPI" : false, + "MSPI_JUMP" : false, + "MULTIBOOT_ADDRESS_WIDTH" : "24", + "MULTIBOOT_MODE" : "Normal", + "MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000", + "MULTIJUMP_ADDRESS_WIDTH" : "24", + "MULTIJUMP_MODE" : "Normal", + "MULTIJUMP_SPI_FLASH_ADDRESS" : "000000", + "Multi_Boot" : true, + "OUTPUT_BASE_NAME" : "lab2", + "POWER_ON_RESET_MONITOR" : true, + "PRINT_BSRAM_VALUE" : true, + "PROGRAM_DONE_BYPASS" : false, + "PlaceInRegToIob" : true, + "PlaceIoRegToIob" : true, + "PlaceOutRegToIob" : true, + "Place_Option" : "0", + "Process_Configuration_Verion" : "1.0", + "Promote_Physical_Constraint_Warning_to_Error" : true, + "READY" : false, + "RECONFIG_N" : false, + "Ram_RW_Check" : false, + "Replicate_Resources" : false, + "Report_Auto-Placed_Io_Information" : false, + "Route_Maxfan" : 23, + "Route_Option" : "0", + "Run_Timing_Driven" : true, + "SECURE_MODE" : false, + "SECURITY_BIT" : true, + "SEU_HANDLER" : false, + "SEU_HANDLER_CHECKSUM" : false, + "SEU_HANDLER_MODE" : "auto", + "SSPI" : false, + "STOP_SEU_HANDLER" : false, + "Show_All_Warnings" : false, + "Synthesize_tool" : "GowinSyn", + "TclPre" : "", + "TopModule" : "", + "USERCODE" : "default", + "Unused_Pin" : "As_input_tri_stated_with_pull_up", + "VCCAUX" : 3.3, + "VCCX" : "3.3", + "VHDL_Standard" : "VHDL_Std_1993", + "Verilog_Standard" : "Vlg_Std_2001", + "WAKE_UP" : "0", + "show_all_warnings" : false, + "turn_off_bg" : false +} \ No newline at end of file diff --git a/lab2/impl/temp/rtl_parser.result b/lab2/impl/temp/rtl_parser.result new file mode 100644 index 0000000..aae5592 --- /dev/null +++ b/lab2/impl/temp/rtl_parser.result @@ -0,0 +1,36 @@ +[ + { + "InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v", + "InstLine" : 1, + "InstName" : "BitM", + "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v", + "ModuleLine" : 1, + "ModuleName" : "BitM" + }, + { + "InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v", + "InstLine" : 1, + "InstName" : "fullAdder", + "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v", + "ModuleLine" : 1, + "ModuleName" : "fullAdder" + }, + { + "InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v", + "InstLine" : 1, + "InstName" : "tb", + "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v", + "ModuleLine" : 1, + "ModuleName" : "tb", + "SubInsts" : [ + { + "InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v", + "InstLine" : 6, + "InstName" : "uut", + "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/halfAdder.v", + "ModuleLine" : 1, + "ModuleName" : "halfAdder" + } + ] + } +] \ No newline at end of file diff --git a/lab2/impl/temp/rtl_parser_arg.json b/lab2/impl/temp/rtl_parser_arg.json new file mode 100644 index 0000000..8e2386e --- /dev/null +++ b/lab2/impl/temp/rtl_parser_arg.json @@ -0,0 +1,29 @@ +{ + "Device" : "GW2A-18C", + "Files" : [ + { + "Path" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v", + "Type" : "verilog" + }, + { + "Path" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v", + "Type" : "verilog" + }, + { + "Path" : "C:/cygwin64/home/koray/verilog/lab2/src/halfAdder.v", + "Type" : "verilog" + }, + { + "Path" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v", + "Type" : "verilog" + } + ], + "IncludePath" : [ + + ], + "LoopLimit" : 2000, + "ResultFile" : "C:/cygwin64/home/koray/verilog/lab2/impl/temp/rtl_parser.result", + "Top" : "", + "VerilogStd" : "verilog_2001", + "VhdlStd" : "vhdl_93" +} \ No newline at end of file diff --git a/lab2/lab2.gprj b/lab2/lab2.gprj new file mode 100644 index 0000000..55fa3ad --- /dev/null +++ b/lab2/lab2.gprj @@ -0,0 +1,13 @@ + + + + + 5 + gw2a18c-011 + + + + + + + diff --git a/lab2/lab2.gprj.user b/lab2/lab2.gprj.user new file mode 100644 index 0000000..57cf46a --- /dev/null +++ b/lab2/lab2.gprj.user @@ -0,0 +1,17 @@ + + + + 1.0 + + + + + + + + + + + + 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+ diff --git a/lab2/src/BitM.v b/lab2/src/BitM.v new file mode 100644 index 0000000..bc5a54c --- /dev/null +++ b/lab2/src/BitM.v @@ -0,0 +1,19 @@ +module BitM( + input A, + input B, + output AlB, + output AeB, + output AgB +); + + wire An, Bn; + + not n1 (An, A); + not n2 (Bn, B); + + and a1 (AlB, An, B); + and a2 (AgB, Bn, A); + + nor nor1 (AeB, AlB, AgB); + +endmodule \ No newline at end of file diff --git a/lab2/src/BitM_tb.v b/lab2/src/BitM_tb.v new file mode 100644 index 0000000..f2f1a41 --- /dev/null +++ b/lab2/src/BitM_tb.v @@ -0,0 +1,26 @@ +module BitM_tb(); + +reg r1, r2; +wire w1, w2, w3; + +BitM uut( + .A(r1), + .B(r2), + .AlB(w1), + .AeB(w2), + .AgB(w3) +); + +initial begin + $dumpfile("bdmp.vcd"); + $dumpvars; + r1 = 0; r2 = 0; #10 + r1 = 0; r2 = 1; #10 + r1 = 1; r2 = 0; #10 + r1 = 1; r2 = 1; #10 + $display(w1); + $display(w2); + $display(w3); +end + +endmodule \ No newline at end of file diff --git a/lab2/src/bdmp.vcd b/lab2/src/bdmp.vcd new file mode 100644 index 0000000..09a289a --- /dev/null +++ b/lab2/src/bdmp.vcd @@ -0,0 +1,58 @@ +$date + Thu Apr 11 07:50:26 2024 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module BitM_tb $end +$var wire 1 ! w3 $end +$var wire 1 " w2 $end +$var wire 1 # w1 $end +$var reg 1 $ r1 $end +$var reg 1 % r2 $end +$scope module uut $end +$var wire 1 $ A $end +$var wire 1 " AeB $end +$var wire 1 ! AgB $end +$var wire 1 # AlB $end +$var wire 1 & An $end +$var wire 1 % B $end +$var wire 1 ' Bn $end +$upscope $end +$upscope $end +$enddefinitions $end +$comment Show the parameter values. $end +$dumpall +$end +#0 +$dumpvars +1' +1& +0% +0$ +0# +1" +0! +$end +#10 +0" +0' +1# +1% +#20 +1! +0" +1' +0# +0& +0% +1$ +#30 +1" +0! +0' +1% +#40 diff --git a/lab2/src/blab2 b/lab2/src/blab2 new file mode 100644 index 0000000..82a77fd --- /dev/null +++ b/lab2/src/blab2 @@ -0,0 +1,70 @@ +#! /c/Source/iverilog-install/bin/vvp +:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "C:\iverilog\lib\ivl\system.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi"; +:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi"; +:vpi_module "C:\iverilog\lib\ivl\va_math.vpi"; +S_000002114102cad0 .scope module, "BitM_tb" "BitM_tb" 2 1; + .timescale 0 0; +v0000021140f146e0_0 .var "r1", 0 0; +v0000021140f14780_0 .var "r2", 0 0; +v0000021140f14820_0 .net "w1", 0 0, L_0000021140ee32f0; 1 drivers +v0000021140f148c0_0 .net "w2", 0 0, L_0000021140f14f60; 1 drivers +v0000021140f14960_0 .net "w3", 0 0, L_0000021140f14de0; 1 drivers +S_000002114102cc60 .scope module, "uut" "BitM" 2 6, 3 1 0, S_000002114102cad0; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /INPUT 1 "B"; + .port_info 2 /OUTPUT 1 "AlB"; + .port_info 3 /OUTPUT 1 "AeB"; + .port_info 4 /OUTPUT 1 "AgB"; +L_000002114102af60 .functor NOT 1, v0000021140f146e0_0, C4<0>, C4<0>, C4<0>; +L_0000021140ee3190 .functor NOT 1, v0000021140f14780_0, C4<0>, C4<0>, C4<0>; +L_0000021140ee32f0 .functor AND 1, L_000002114102af60, v0000021140f14780_0, C4<1>, C4<1>; +L_0000021140f14de0 .functor AND 1, L_0000021140ee3190, v0000021140f146e0_0, C4<1>, C4<1>; +L_0000021140f14f60 .functor NOR 1, L_0000021140ee32f0, L_0000021140f14de0, C4<0>, C4<0>; +v0000021141028fc0_0 .net "A", 0 0, v0000021140f146e0_0; 1 drivers +v0000021140ee2ee0_0 .net "AeB", 0 0, L_0000021140f14f60; alias, 1 drivers +v000002114102aec0_0 .net "AgB", 0 0, L_0000021140f14de0; alias, 1 drivers +v000002114102cdf0_0 .net "AlB", 0 0, L_0000021140ee32f0; alias, 1 drivers +v000002114102ce90_0 .net "An", 0 0, L_000002114102af60; 1 drivers +v0000021140f145a0_0 .net "B", 0 0, v0000021140f14780_0; 1 drivers +v0000021140f14640_0 .net "Bn", 0 0, L_0000021140ee3190; 1 drivers + .scope S_000002114102cad0; +T_0 ; + %vpi_call 2 15 "$dumpfile", "bdmp.vcd" {0 0 0}; + %vpi_call 2 16 "$dumpvars" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0000021140f146e0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0000021140f14780_0, 0, 1; + %delay 10, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0000021140f146e0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0000021140f14780_0, 0, 1; + %delay 10, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0000021140f146e0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0000021140f14780_0, 0, 1; + %delay 10, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0000021140f146e0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0000021140f14780_0, 0, 1; + %delay 10, 0; + %vpi_call 2 21 "$display", v0000021140f14820_0 {0 0 0}; + %vpi_call 2 22 "$display", v0000021140f148c0_0 {0 0 0}; + %vpi_call 2 23 "$display", v0000021140f14960_0 {0 0 0}; + %end; + .thread T_0; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "BitM_tb.v"; + "BitM.v"; diff --git a/lab2/src/dmp.vcd b/lab2/src/dmp.vcd new file mode 100644 index 0000000..bb252c0 --- /dev/null +++ b/lab2/src/dmp.vcd @@ -0,0 +1,43 @@ +$date + Thu Apr 11 06:36:34 2024 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module tb $end +$var wire 1 ! w2 $end +$var wire 1 " w1 $end +$var reg 1 # r1 $end +$var reg 1 $ r2 $end +$scope module uut $end +$var wire 1 # A $end +$var wire 1 $ B $end +$var wire 1 ! C $end +$var wire 1 " S $end +$upscope $end +$upscope $end +$enddefinitions $end +$comment Show the parameter values. $end +$dumpall +$end +#0 +$dumpvars +0$ +0# +0" +0! +$end +#20 +1" +1# +#40 +1$ +0# +#60 +0" +1! +1# +#80 diff --git a/lab2/src/fdmp.vcd b/lab2/src/fdmp.vcd new file mode 100644 index 0000000..888908c --- /dev/null +++ b/lab2/src/fdmp.vcd @@ -0,0 +1,75 @@ +$date + Thu Apr 11 07:39:27 2024 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module ftb $end +$var wire 1 ! w2 $end +$var wire 1 " w1 $end +$var reg 1 # r1 $end +$var reg 1 $ r2 $end +$var reg 1 % r3 $end +$scope module uut $end +$var wire 1 # A $end +$var wire 1 & AB $end +$var wire 1 ' ABCin $end +$var wire 1 ( AaB $end +$var wire 1 $ B $end +$var wire 1 % Cin $end +$var wire 1 ! Cout $end +$var wire 1 " S $end +$upscope $end +$upscope $end +$enddefinitions $end +$comment Show the parameter values. $end +$dumpall +$end +#0 +$dumpvars +0( +0' +0& +0% +0$ +0# +0" +0! +$end +#10 +1" +1% +#20 +1& +0% +1$ +#30 +1! +0" +1' +1% +#40 +0! +1" +0' +0% +0$ +1# +#50 +1! +0" +1' +1% +#60 +0' +0& +1( +0% +1$ +#70 +1" +1% +#80 diff --git a/lab2/src/flab2 b/lab2/src/flab2 new file mode 100644 index 0000000..294d47f --- /dev/null +++ b/lab2/src/flab2 @@ -0,0 +1,106 @@ +#! /c/Source/iverilog-install/bin/vvp +:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "C:\iverilog\lib\ivl\system.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi"; +:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi"; +:vpi_module "C:\iverilog\lib\ivl\va_math.vpi"; +S_000001da0354ad70 .scope module, "ftb" "ftb" 2 1; + .timescale 0 0; +v000001da035dc840_0 .var "r1", 0 0; +v000001da035dc8e0_0 .var "r2", 0 0; +v000001da035dc980_0 .var "r3", 0 0; +v000001da035dca20_0 .net "w1", 0 0, L_000001da03594080; 1 drivers +v000001da035935f0_0 .net "w2", 0 0, L_000001da03594470; 1 drivers +S_000001da0354e9e0 .scope module, "uut" "fullAdder" 2 6, 3 1 0, S_000001da0354ad70; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /INPUT 1 "B"; + .port_info 2 /INPUT 1 "Cin"; + .port_info 3 /OUTPUT 1 "S"; + .port_info 4 /OUTPUT 1 "Cout"; +L_000001da03594010 .functor XOR 1, v000001da035dc840_0, v000001da035dc8e0_0, C4<0>, C4<0>; +L_000001da03594080 .functor XOR 1, L_000001da03594010, v000001da035dc980_0, C4<0>, C4<0>; +L_000001da03593e50 .functor AND 1, L_000001da03594010, v000001da035dc980_0, C4<1>, C4<1>; +L_000001da035940f0 .functor AND 1, v000001da035dc840_0, v000001da035dc8e0_0, C4<1>, C4<1>; +L_000001da03594470 .functor OR 1, L_000001da03593e50, L_000001da035940f0, C4<0>, C4<0>; +v000001da03563310_0 .net "A", 0 0, v000001da035dc840_0; 1 drivers +v000001da03562ee0_0 .net "AB", 0 0, L_000001da03594010; 1 drivers +v000001da0354af00_0 .net "ABCin", 0 0, L_000001da03593e50; 1 drivers +v000001da03549850_0 .net "AaB", 0 0, L_000001da035940f0; 1 drivers +v000001da0354eb70_0 .net "B", 0 0, v000001da035dc8e0_0; 1 drivers +v000001da0354ec10_0 .net "Cin", 0 0, v000001da035dc980_0; 1 drivers +v000001da0354ecb0_0 .net "Cout", 0 0, L_000001da03594470; alias, 1 drivers +v000001da0354ed50_0 .net "S", 0 0, L_000001da03594080; alias, 1 drivers + .scope S_000001da0354ad70; +T_0 ; + %vpi_call 2 15 "$dumpfile", "fdmp.vcd" {0 0 0}; + %vpi_call 2 16 "$dumpvars" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001da035dc840_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001da035dc8e0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001da035dc980_0, 0, 1; + %delay 10, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001da035dc840_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001da035dc8e0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001da035dc980_0, 0, 1; + %delay 10, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001da035dc840_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001da035dc8e0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001da035dc980_0, 0, 1; + %delay 10, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001da035dc840_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001da035dc8e0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001da035dc980_0, 0, 1; + %delay 10, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001da035dc840_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001da035dc8e0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001da035dc980_0, 0, 1; + %delay 10, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001da035dc840_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001da035dc8e0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001da035dc980_0, 0, 1; + %delay 10, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001da035dc840_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001da035dc8e0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001da035dc980_0, 0, 1; + %delay 10, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001da035dc840_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001da035dc8e0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001da035dc980_0, 0, 1; + %delay 10, 0; + %vpi_call 2 25 "$display", v000001da035dca20_0 {0 0 0}; + %vpi_call 2 26 "$display", v000001da035935f0_0 {0 0 0}; + %end; + .thread T_0; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "ftb.v"; + "fullAdder.v"; diff --git a/lab2/src/ftb.v b/lab2/src/ftb.v new file mode 100644 index 0000000..febad75 --- /dev/null +++ b/lab2/src/ftb.v @@ -0,0 +1,29 @@ +module ftb (); + +reg r1, r2, r3; +wire w1, w2; + +fullAdder uut( + .A(r1), + .B(r2), + .Cin(r3), + .S(w1), + .Cout(w2) +); + +initial begin + $dumpfile("fdmp.vcd"); + $dumpvars; + r1 = 0; r2 = 0; r3 = 0; #10 + r1 = 0; r2 = 0; r3 = 1; #10 + r1 = 0; r2 = 1; r3 = 0; #10 + r1 = 0; r2 = 1; r3 = 1; #10 + r1 = 1; r2 = 0; r3 = 0; #10 + r1 = 1; r2 = 0; r3 = 1; #10 + r1 = 1; r2 = 1; r3 = 0; #10 + r1 = 1; r2 = 1; r3 = 1; #10 + $display(w1); + $display(w2); +end + +endmodule \ No newline at end of file diff --git a/lab2/src/fullAdder.v b/lab2/src/fullAdder.v new file mode 100644 index 0000000..ffe6ea7 --- /dev/null +++ b/lab2/src/fullAdder.v @@ -0,0 +1,20 @@ +module fullAdder( + input A, + input B, + input Cin, + output S, + output Cout +); + + wire AB; + wire ABCin, AaB; + + xor (AB, A, B); + xor (S, AB, Cin); + + and (ABCin, AB, Cin); + and (AaB, A, B); + + or (Cout, ABCin, AaB); + +endmodule \ No newline at end of file diff --git a/lab2/src/halfAdder.v b/lab2/src/halfAdder.v new file mode 100644 index 0000000..0333461 --- /dev/null +++ b/lab2/src/halfAdder.v @@ -0,0 +1,11 @@ +module halfAdder( + input A, + input B, + output S, + output C +); + + xor (S, A, B); + and (C, A, B); + +endmodule \ No newline at end of file diff --git a/lab2/src/lab2 b/lab2/src/lab2 new file mode 100644 index 0000000..2dbe485 --- /dev/null +++ b/lab2/src/lab2 @@ -0,0 +1,61 @@ +#! /c/Source/iverilog-install/bin/vvp +:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "C:\iverilog\lib\ivl\system.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi"; +:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi"; +:vpi_module "C:\iverilog\lib\ivl\va_math.vpi"; +S_000001b4458eec80 .scope module, "tb" "tb" 2 1; + .timescale 0 0; +v000001b4458ec1d0_0 .var "r1", 0 0; +v000001b4458ec270_0 .var "r2", 0 0; +v000001b4458ec310_0 .net "w1", 0 0, L_000001b445783190; 1 drivers +v000001b4458ec3b0_0 .net "w2", 0 0, L_000001b4457832f0; 1 drivers +S_000001b4458eee10 .scope module, "uut" "halfAdder" 2 6, 3 1 0, S_000001b4458eec80; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /INPUT 1 "B"; + .port_info 2 /OUTPUT 1 "S"; + .port_info 3 /OUTPUT 1 "C"; +L_000001b445783190 .functor XOR 1, v000001b4458ec1d0_0, v000001b4458ec270_0, C4<0>, C4<0>; +L_000001b4457832f0 .functor AND 1, v000001b4458ec1d0_0, v000001b4458ec270_0, C4<1>, C4<1>; +v000001b4458ebff0_0 .net "A", 0 0, v000001b4458ec1d0_0; 1 drivers +v000001b445782ee0_0 .net "B", 0 0, v000001b4458ec270_0; 1 drivers +v000001b4458ec090_0 .net "C", 0 0, L_000001b4457832f0; alias, 1 drivers +v000001b4458ec130_0 .net "S", 0 0, L_000001b445783190; alias, 1 drivers + .scope S_000001b4458eec80; +T_0 ; + %vpi_call 2 14 "$dumpfile", "dmp.vcd" {0 0 0}; + %vpi_call 2 15 "$dumpvars" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001b4458ec1d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001b4458ec270_0, 0, 1; + %delay 20, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001b4458ec1d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001b4458ec270_0, 0, 1; + %delay 20, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001b4458ec1d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001b4458ec270_0, 0, 1; + %delay 20, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001b4458ec1d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001b4458ec270_0, 0, 1; + %delay 20, 0; + %vpi_call 2 20 "$display", v000001b4458ec310_0 {0 0 0}; + %vpi_call 2 21 "$display", v000001b4458ec3b0_0 {0 0 0}; + %end; + .thread T_0; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "tb.v"; + "halfAdder.v"; diff --git a/lab2/src/tb.v b/lab2/src/tb.v new file mode 100644 index 0000000..2ef7bfa --- /dev/null +++ b/lab2/src/tb.v @@ -0,0 +1,24 @@ +module tb(); + +reg r1, r2; +wire w1, w2; + +halfAdder uut( + .A(r1), + .B(r2), + .S(w1), + .C(w2) +); + +initial begin + $dumpfile("dmp.vcd"); + $dumpvars; + r1 = 0; r2 = 0; #20 + r1 = 1; r2 = 0; #20 + r1 = 0; r2 = 1; #20 + r1 = 1; r2 = 1; #20 + $display(w1); + $display(w2); +end + +endmodule \ No newline at end of file diff --git a/lab2_prep/impl/gwsynthesis/lab2.log b/lab2_prep/impl/gwsynthesis/lab2.log new file mode 100644 index 0000000..ccab26f --- /dev/null +++ b/lab2_prep/impl/gwsynthesis/lab2.log @@ -0,0 +1,40 @@ +GowinSynthesis start +Running parser ... +Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\lab2.v' +Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\tb.v' +Compiling module 'tb'("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":1) +WARN (EX3858) : System task 'dumpfile' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":17) +WARN (EX3858) : System task 'dumpvars' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":18) +WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":19) +WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":20) +WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":21) +WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":22) +WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":23) +WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":24) +WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":25) +WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":26) +WARN (EX3858) : System task 'display' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":27) +WARN (EX3780) : Using initial value of 'r1' since it is never assigned("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":28) +Compiling module 'lab2'("C:\cygwin64\home\koray\verilog\lab2\src\lab2.v":1) +NOTE (EX0101) : Current top module is "tb" +WARN (EX0203) : Top module "tb" has no ports("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":1) +[5%] Running netlist conversion ... +Running device independent optimization ... +[10%] Optimizing Phase 0 completed +[15%] Optimizing Phase 1 completed +[25%] Optimizing Phase 2 completed +Running inference ... +[30%] Inferring Phase 0 completed +[40%] Inferring Phase 1 completed +[50%] Inferring Phase 2 completed +[55%] Inferring Phase 3 completed +Running technical mapping ... +[60%] Tech-Mapping Phase 0 completed +[65%] Tech-Mapping Phase 1 completed +[75%] Tech-Mapping Phase 2 completed +[80%] Tech-Mapping Phase 3 completed +[90%] Tech-Mapping Phase 4 completed +WARN (NL0002) : The module "lab2" instantiated to "uut" is swept in optimizing("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":12) +[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg" completed +[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2_syn.rpt.html" completed +GowinSynthesis finish diff --git a/lab2_prep/impl/gwsynthesis/lab2.prj b/lab2_prep/impl/gwsynthesis/lab2.prj new file mode 100644 index 0000000..c5de982 --- /dev/null +++ b/lab2_prep/impl/gwsynthesis/lab2.prj @@ -0,0 +1,20 @@ + + + + beta + + + + + + + + diff --git a/lab2_prep/impl/gwsynthesis/lab2.vg b/lab2_prep/impl/gwsynthesis/lab2.vg new file mode 100644 index 0000000..d6a6bbb --- /dev/null +++ b/lab2_prep/impl/gwsynthesis/lab2.vg @@ -0,0 +1,25 @@ +// +//Written by GowinSynthesis +//Tool Version "V1.9.9.02" +//Thu Apr 11 06:15:18 2024 + +//Source file index table: +//file0 "\C:/cygwin64/home/koray/verilog/lab2/src/lab2.v" +//file1 "\C:/cygwin64/home/koray/verilog/lab2/src/tb.v" +`timescale 100 ps/100 ps +module tb ( + +) +; +wire VCC; +wire GND; + VCC VCC_cZ ( + .V(VCC) +); + GND GND_cZ ( + .G(GND) +); + GSR GSR ( + .GSRI(VCC) +); +endmodule /* tb */ diff --git a/lab2_prep/impl/gwsynthesis/lab2_syn.rpt.html b/lab2_prep/impl/gwsynthesis/lab2_syn.rpt.html new file mode 100644 index 0000000..00eb19a --- /dev/null +++ b/lab2_prep/impl/gwsynthesis/lab2_syn.rpt.html @@ -0,0 +1,144 @@ + + + +synthesis Report + + + +
+ +
+

Synthesis Messages

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Report TitleGowinSynthesis Report
Design FileC:\cygwin64\home\koray\verilog\lab2\src\lab2.v
+C:\cygwin64\home\koray\verilog\lab2\src\tb.v
+
GowinSynthesis Constraints File---
Tool VersionV1.9.9.02
Part NumberGW2A-LV18PG256C8/I7
DeviceGW2A-18
Device VersionC
Created TimeThu Apr 11 06:15:18 2024 +
Legal AnnouncementCopyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.
+

Synthesis Details

+ + + + + + + + + + + + + +
Top Level Moduletb
Synthesis ProcessRunning parser:
    CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.148s, Peak memory usage = 184.680MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 184.680MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 184.680MB
Total Time and Memory UsageCPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.208s, Peak memory usage = 184.680MB
+

Resource

+

Resource Usage Summary

+ + + + + +
ResourceUsage
+

Resource Utilization Summary

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ResourceUsageUtilization
Logic0(0 LUT, 0 ALU) / 207360%
Register0 / 161730%
  --Register as Latch0 / 161730%
  --Register as FF0 / 161730%
BSRAM0 / 460%
+
+
+ + diff --git a/lab2_prep/impl/gwsynthesis/lab2_syn_resource.html b/lab2_prep/impl/gwsynthesis/lab2_syn_resource.html new file mode 100644 index 0000000..c02cf8c --- /dev/null +++ b/lab2_prep/impl/gwsynthesis/lab2_syn_resource.html @@ -0,0 +1,46 @@ + + + +Hierarchy Module Resource + + + +
+
+

Hierarchy Module Resource

+ + + + + + + + + + + + + + + + + + + + + +
MODULE NAMEREG NUMBERALU NUMBERLUT NUMBERDSP NUMBERBSRAM NUMBERSSRAM NUMBERROM16 NUMBER
tb (C:/cygwin64/home/koray/verilog/lab2/src/tb.v)-------
+
+
+ + diff --git a/lab2_prep/impl/gwsynthesis/lab2_syn_rsc.xml b/lab2_prep/impl/gwsynthesis/lab2_syn_rsc.xml new file mode 100644 index 0000000..45e8e3b --- /dev/null +++ b/lab2_prep/impl/gwsynthesis/lab2_syn_rsc.xml @@ -0,0 +1,2 @@ + + diff --git a/lab2_prep/impl/lab2_process_config.json b/lab2_prep/impl/lab2_process_config.json new file mode 100644 index 0000000..e4d68ba --- /dev/null +++ b/lab2_prep/impl/lab2_process_config.json @@ -0,0 +1,88 @@ +{ + "BACKGROUND_PROGRAMMING" : "off", + "COMPRESS" : false, + "CPU" : false, + "CRC_CHECK" : true, + "Clock_Route_Order" : 0, + "Correct_Hold_Violation" : true, + "DONE" : false, + "DOWNLOAD_SPEED" : "default", + "Disable_Insert_Pad" : false, + "ENABLE_CTP" : false, + "ENABLE_MERGE_MODE" : false, + "ENCRYPTION_KEY" : false, + "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000", + "ERROR_DECTION_AND_CORRECTION" : false, + "ERROR_DECTION_ONLY" : false, + "ERROR_INJECTION" : false, + "EXTERNAL_MASTER_CONFIG_CLOCK" : false, + "Enable_DSRM" : false, + "FORMAT" : "binary", + "FREQUENCY_DIVIDER" : "", + "Generate_Constraint_File_of_Ports" : false, + "Generate_IBIS_File" : false, + "Generate_Plain_Text_Timing_Report" : false, + "Generate_Post_PNR_Simulation_Model_File" : false, + "Generate_Post_Place_File" : false, + "Generate_SDF_File" : false, + "Generate_VHDL_Post_PNR_Simulation_Model_File" : false, + "Global_Freq" : "default", + "GwSyn_Loop_Limit" : 2000, + "HOTBOOT" : false, + "I2C" : false, + "I2C_SLAVE_ADDR" : "00", + "IncludePath" : [ + + ], + "Incremental_Compile" : "", + "Initialize_Primitives" : false, + "JTAG" : false, + "MODE_IO" : false, + "MSPI" : false, + "MSPI_JUMP" : false, + "MULTIBOOT_ADDRESS_WIDTH" : "24", + "MULTIBOOT_MODE" : "Normal", + "MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000", + "MULTIJUMP_ADDRESS_WIDTH" : "24", + "MULTIJUMP_MODE" : "Normal", + "MULTIJUMP_SPI_FLASH_ADDRESS" : "000000", + "Multi_Boot" : true, + "OUTPUT_BASE_NAME" : "lab2", + "POWER_ON_RESET_MONITOR" : true, + "PRINT_BSRAM_VALUE" : true, + "PROGRAM_DONE_BYPASS" : false, + "PlaceInRegToIob" : true, + "PlaceIoRegToIob" : true, + "PlaceOutRegToIob" : true, + "Place_Option" : "0", + "Process_Configuration_Verion" : "1.0", + "Promote_Physical_Constraint_Warning_to_Error" : true, + "READY" : false, + "RECONFIG_N" : false, + "Ram_RW_Check" : false, + "Replicate_Resources" : false, + "Report_Auto-Placed_Io_Information" : false, + "Route_Maxfan" : 23, + "Route_Option" : "0", + "Run_Timing_Driven" : true, + "SECURE_MODE" : false, + "SECURITY_BIT" : true, + "SEU_HANDLER" : false, + "SEU_HANDLER_CHECKSUM" : false, + "SEU_HANDLER_MODE" : "auto", + "SSPI" : false, + "STOP_SEU_HANDLER" : false, + "Show_All_Warnings" : false, + "Synthesize_tool" : "GowinSyn", + "TclPre" : "", + "TopModule" : "", + "USERCODE" : "default", + "Unused_Pin" : "As_input_tri_stated_with_pull_up", + "VCCAUX" : 3.3, + "VCCX" : "3.3", + "VHDL_Standard" : "VHDL_Std_1993", + "Verilog_Standard" : "Vlg_Std_2001", + "WAKE_UP" : "0", + "show_all_warnings" : false, + "turn_off_bg" : false +} \ No newline at end of file diff --git a/lab2_prep/impl/temp/rtl_parser.result b/lab2_prep/impl/temp/rtl_parser.result new file mode 100644 index 0000000..d1dc97e --- /dev/null +++ b/lab2_prep/impl/temp/rtl_parser.result @@ -0,0 +1,20 @@ +[ + { + "InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v", + "InstLine" : 1, + "InstName" : "tb", + "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v", + "ModuleLine" : 1, + "ModuleName" : "tb", + "SubInsts" : [ + { + "InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v", + "InstLine" : 6, + "InstName" : "uut", + "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/lab2.v", + "ModuleLine" : 1, + "ModuleName" : "lab2" + } + ] + } +] \ No newline at end of file diff --git a/lab2_prep/impl/temp/rtl_parser_arg.json b/lab2_prep/impl/temp/rtl_parser_arg.json new file mode 100644 index 0000000..78a8e8d --- /dev/null +++ b/lab2_prep/impl/temp/rtl_parser_arg.json @@ -0,0 +1,21 @@ +{ + "Device" : "GW2A-18C", + "Files" : [ + { + "Path" : "C:/cygwin64/home/koray/verilog/lab2/src/lab2.v", + "Type" : "verilog" + }, + { + "Path" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v", + "Type" : "verilog" + } + ], + "IncludePath" : [ + + ], + "LoopLimit" : 2000, + "ResultFile" : "C:/cygwin64/home/koray/verilog/lab2/impl/temp/rtl_parser.result", + "Top" : "", + "VerilogStd" : "verilog_2001", + "VhdlStd" : "vhdl_93" +} \ No newline at end of file diff --git a/lab2_prep/lab2.gprj b/lab2_prep/lab2.gprj new file mode 100644 index 0000000..d98a08b --- /dev/null +++ b/lab2_prep/lab2.gprj @@ -0,0 +1,12 @@ + + + + + 5 + gw2a18c-011 + + + + + + diff --git a/lab2_prep/lab2.gprj.user b/lab2_prep/lab2.gprj.user new file mode 100644 index 0000000..f890b01 --- /dev/null +++ b/lab2_prep/lab2.gprj.user @@ -0,0 +1,17 @@ + + + + 1.0 + + + + + + + + + + + + 000000ff00000001fd0000000200000000000001700000013dfc0200000001fc000000630000013d0000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000050000000114fc0100000001fc0000000000000500000000a100fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000007800fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100ffffff000003880000013d00000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000 + diff --git a/lab2_prep/src/dmp.vcd b/lab2_prep/src/dmp.vcd new file mode 100644 index 0000000..5e081c7 --- /dev/null +++ b/lab2_prep/src/dmp.vcd @@ -0,0 +1,77 @@ +$date + Thu Apr 11 06:20:47 2024 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module tb $end +$var wire 1 ! w1 $end +$var reg 1 " r1 $end +$var reg 1 # r2 $end +$var reg 1 $ r3 $end +$var reg 1 % r4 $end +$scope module uut $end +$var wire 1 " A $end +$var wire 1 & AD $end +$var wire 1 ' An $end +$var wire 1 ( AnBC $end +$var wire 1 # B $end +$var wire 1 ) Bn $end +$var wire 1 $ C $end +$var wire 1 * Cn $end +$var wire 1 + CnD $end +$var wire 1 % D $end +$var wire 1 ! F $end +$upscope $end +$upscope $end +$enddefinitions $end +$comment Show the parameter values. $end +$dumpall +$end +#0 +$dumpvars +0+ +1* +1) +0( +1' +0& +0% +0$ +0# +0" +1! +$end +#50 +1+ +1% +#100 +0+ +0* +0% +1$ +#150 +1% +#200 +0! +1* +0) +0% +0$ +1# +#250 +1! +1+ +1% +#300 +0+ +1( +0* +0% +1$ +#350 +1% +#400 diff --git a/lab2_prep/src/lab b/lab2_prep/src/lab new file mode 100644 index 0000000..3548100 --- /dev/null +++ b/lab2_prep/src/lab @@ -0,0 +1,126 @@ +#! /c/Source/iverilog-install/bin/vvp +:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "C:\iverilog\lib\ivl\system.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi"; +:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi"; +:vpi_module "C:\iverilog\lib\ivl\va_math.vpi"; +S_000001e2946aad20 .scope module, "tb" "tb" 2 1; + .timescale 0 0; +v000001e29475e7f0_0 .var "r1", 0 0; +v000001e29475e6b0_0 .var "r2", 0 0; +v000001e29475ec50_0 .var "r3", 0 0; +v000001e29475e430_0 .var "r4", 0 0; +v000001e29475ecf0_0 .net "w1", 0 0, L_000001e29475f0f0; 1 drivers +S_000001e294717fc0 .scope module, "uut" "lab2" 2 6, 3 1 0, S_000001e2946aad20; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /INPUT 1 "B"; + .port_info 2 /INPUT 1 "C"; + .port_info 3 /INPUT 1 "D"; + .port_info 4 /OUTPUT 1 "F"; +L_000001e2947183d0 .functor NOT 1, v000001e29475e7f0_0, C4<0>, C4<0>, C4<0>; +L_000001e2946e2bc0 .functor AND 1, L_000001e2947183d0, v000001e29475e6b0_0, v000001e29475ec50_0, C4<1>; +L_000001e2946e2d20 .functor NOT 1, v000001e29475e6b0_0, C4<0>, C4<0>, C4<0>; +L_000001e29475f390 .functor AND 1, v000001e29475e7f0_0, v000001e29475e430_0, C4<1>, C4<1>; +L_000001e29475f4e0 .functor NOT 1, v000001e29475ec50_0, C4<0>, C4<0>, C4<0>; +L_000001e29475f780 .functor AND 1, L_000001e29475f4e0, v000001e29475e430_0, C4<1>, C4<1>; +L_000001e29475f0f0 .functor OR 1, L_000001e2946e2bc0, L_000001e2946e2d20, L_000001e29475f390, L_000001e29475f780; +v000001e2946e2a40_0 .net "A", 0 0, v000001e29475e7f0_0; 1 drivers +v000001e2946e28d0_0 .net "AD", 0 0, L_000001e29475f390; 1 drivers +v000001e2946a9e10_0 .net "An", 0 0, L_000001e2947183d0; 1 drivers +v000001e2946aaeb0_0 .net "AnBC", 0 0, L_000001e2946e2bc0; 1 drivers +v000001e294718150_0 .net "B", 0 0, v000001e29475e6b0_0; 1 drivers +v000001e2947181f0_0 .net "Bn", 0 0, L_000001e2946e2d20; 1 drivers +v000001e294718290_0 .net "C", 0 0, v000001e29475ec50_0; 1 drivers +v000001e294718330_0 .net "Cn", 0 0, L_000001e29475f4e0; 1 drivers +v000001e294714e50_0 .net "CnD", 0 0, L_000001e29475f780; 1 drivers +v000001e294714ef0_0 .net "D", 0 0, v000001e29475e430_0; 1 drivers +v000001e29475e390_0 .net "F", 0 0, L_000001e29475f0f0; alias, 1 drivers + .scope S_000001e2946aad20; +T_0 ; + %vpi_call 2 17 "$dumpfile", "dmp.vcd" {0 0 0}; + %vpi_call 2 18 "$dumpvars" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475e7f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475e6b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475ec50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475e430_0, 0, 1; + %delay 50, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475e7f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475e6b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475ec50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001e29475e430_0, 0, 1; + %delay 50, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475e7f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475e6b0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001e29475ec50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475e430_0, 0, 1; + %delay 50, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475e7f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475e6b0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001e29475ec50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001e29475e430_0, 0, 1; + %delay 50, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475e7f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001e29475e6b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475ec50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475e430_0, 0, 1; + %delay 50, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475e7f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001e29475e6b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475ec50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001e29475e430_0, 0, 1; + %delay 50, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475e7f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001e29475e6b0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001e29475ec50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475e430_0, 0, 1; + %delay 50, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001e29475e7f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001e29475e6b0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001e29475ec50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001e29475e430_0, 0, 1; + %delay 50, 0; + %vpi_call 2 27 "$display", v000001e29475ecf0_0 {0 0 0}; + %end; + .thread T_0; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "tb.v"; + "lab2.v"; diff --git a/lab2_prep/src/lab2 b/lab2_prep/src/lab2 new file mode 100644 index 0000000..2ee5299 --- /dev/null +++ b/lab2_prep/src/lab2 @@ -0,0 +1,43 @@ +#! /c/Source/iverilog-install/bin/vvp +:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "C:\iverilog\lib\ivl\system.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi"; +:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi"; +:vpi_module "C:\iverilog\lib\ivl\va_math.vpi"; +S_0000016d6fd625e0 .scope module, "lab2" "lab2" 2 1; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /INPUT 1 "B"; + .port_info 2 /INPUT 1 "C"; + .port_info 3 /INPUT 1 "D"; + .port_info 4 /OUTPUT 1 "F"; +o0000016d6fd96f98 .functor BUFZ 1, C4; HiZ drive +L_0000016d6fd62f70 .functor NOT 1, o0000016d6fd96f98, C4<0>, C4<0>, C4<0>; +o0000016d6fd97058 .functor BUFZ 1, C4; HiZ drive +o0000016d6fd970b8 .functor BUFZ 1, C4; HiZ drive +L_0000016d6fedb7d0 .functor AND 1, L_0000016d6fd62f70, o0000016d6fd97058, o0000016d6fd970b8, C4<1>; +L_0000016d6fedb840 .functor NOT 1, o0000016d6fd97058, C4<0>, C4<0>, C4<0>; +o0000016d6fd97148 .functor BUFZ 1, C4; HiZ drive +L_0000016d6fedb8b0 .functor AND 1, o0000016d6fd96f98, o0000016d6fd97148, C4<1>, C4<1>; +L_0000016d6fedb920 .functor NOT 1, o0000016d6fd970b8, C4<0>, C4<0>, C4<0>; +L_0000016d6fedb990 .functor AND 1, L_0000016d6fedb920, o0000016d6fd97148, C4<1>, C4<1>; +L_0000016d6fedba00 .functor OR 1, L_0000016d6fedb7d0, L_0000016d6fedb840, L_0000016d6fedb8b0, L_0000016d6fedb990; +v0000016d6fd62b30_0 .net "A", 0 0, o0000016d6fd96f98; 0 drivers +v0000016d6fd62d50_0 .net "AD", 0 0, L_0000016d6fedb8b0; 1 drivers +v0000016d6fd62770_0 .net "An", 0 0, L_0000016d6fd62f70; 1 drivers +v0000016d6fd62810_0 .net "AnBC", 0 0, L_0000016d6fedb7d0; 1 drivers +v0000016d6fd628b0_0 .net "B", 0 0, o0000016d6fd97058; 0 drivers +v0000016d6fededb0_0 .net "Bn", 0 0, L_0000016d6fedb840; 1 drivers +v0000016d6fedee50_0 .net "C", 0 0, o0000016d6fd970b8; 0 drivers +v0000016d6fedeef0_0 .net "Cn", 0 0, L_0000016d6fedb920; 1 drivers +v0000016d6fedb600_0 .net "CnD", 0 0, L_0000016d6fedb990; 1 drivers +v0000016d6fedb730_0 .net "D", 0 0, o0000016d6fd97148; 0 drivers +v0000016d6fd90c30_0 .net "F", 0 0, L_0000016d6fedba00; 1 drivers +# The file index is used to find the file name in the following table. +:file_names 3; + "N/A"; + ""; + "lab2.v"; diff --git a/lab2_prep/src/lab2.v b/lab2_prep/src/lab2.v new file mode 100644 index 0000000..60e374d --- /dev/null +++ b/lab2_prep/src/lab2.v @@ -0,0 +1,24 @@ +module lab2( + input A, + input B, + input C, + input D, + output F + ); + + wire An, Bn, Cn; + wire AnBC, AD, CnD; + + not n1 (An, A); + and (AnBC, An, B, C); + + not (Bn, B); + and (AD, A, D); + + not (Cn, C); + and (CnD, Cn, D); + + or (F, AnBC, Bn, AD, CnD); + + +endmodule \ No newline at end of file diff --git a/lab2_prep/src/labwave b/lab2_prep/src/labwave new file mode 100644 index 0000000..9fe3497 --- /dev/null +++ b/lab2_prep/src/labwave @@ -0,0 +1,43 @@ +#! /c/Source/iverilog-install/bin/vvp +:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "C:\iverilog\lib\ivl\system.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi"; +:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi"; +:vpi_module "C:\iverilog\lib\ivl\va_math.vpi"; +S_000001e0df4625e0 .scope module, "f_lab2" "f_lab2" 2 1; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /INPUT 1 "B"; + .port_info 2 /INPUT 1 "C"; + .port_info 3 /INPUT 1 "D"; + .port_info 4 /OUTPUT 1 "F"; +o000001e0df496fd8 .functor BUFZ 1, C4; HiZ drive +L_000001e0df462f70 .functor NOT 1, o000001e0df496fd8, C4<0>, C4<0>, C4<0>; +o000001e0df497098 .functor BUFZ 1, C4; HiZ drive +o000001e0df4970f8 .functor BUFZ 1, C4; HiZ drive +L_000001e0df64aa10 .functor AND 1, L_000001e0df462f70, o000001e0df497098, o000001e0df4970f8, C4<1>; +L_000001e0df64aa80 .functor NOT 1, o000001e0df497098, C4<0>, C4<0>, C4<0>; +o000001e0df497188 .functor BUFZ 1, C4; HiZ drive +L_000001e0df64aaf0 .functor AND 1, o000001e0df496fd8, o000001e0df497188, C4<1>, C4<1>; +L_000001e0df64ab60 .functor NOT 1, o000001e0df4970f8, C4<0>, C4<0>, C4<0>; +L_000001e0df64abd0 .functor AND 1, L_000001e0df64ab60, o000001e0df497188, C4<1>, C4<1>; +L_000001e0df64ac40 .functor OR 1, L_000001e0df64aa10, L_000001e0df64aa80, L_000001e0df64aaf0, L_000001e0df64abd0; +v000001e0df462b30_0 .net "A", 0 0, o000001e0df496fd8; 0 drivers +v000001e0df462d50_0 .net "AD", 0 0, L_000001e0df64aaf0; 1 drivers +v000001e0df462770_0 .net "An", 0 0, L_000001e0df462f70; 1 drivers +v000001e0df462810_0 .net "AnBC", 0 0, L_000001e0df64aa10; 1 drivers +v000001e0df4628b0_0 .net "B", 0 0, o000001e0df497098; 0 drivers +v000001e0df64ed90_0 .net "Bn", 0 0, L_000001e0df64aa80; 1 drivers +v000001e0df64ee30_0 .net "C", 0 0, o000001e0df4970f8; 0 drivers +v000001e0df64eed0_0 .net "Cn", 0 0, L_000001e0df64ab60; 1 drivers +v000001e0df64a840_0 .net "CnD", 0 0, L_000001e0df64abd0; 1 drivers +v000001e0df64a970_0 .net "D", 0 0, o000001e0df497188; 0 drivers +v000001e0df492660_0 .net "F", 0 0, L_000001e0df64ac40; 1 drivers +# The file index is used to find the file name in the following table. +:file_names 3; + "N/A"; + ""; + ".\f_lab2.v"; diff --git a/lab2_prep/src/tb.v b/lab2_prep/src/tb.v new file mode 100644 index 0000000..6a0a219 --- /dev/null +++ b/lab2_prep/src/tb.v @@ -0,0 +1,32 @@ +module tb(); + +reg r1, r2, r3, r4; +wire w1; + +lab2 uut( + .A(r1), + .B(r2), + .C(r3), + .D(r4), + .F(w1) +); + +// test uut(r1, r2, w1, w2, w3); + +initial begin + $dumpfile("dmp.vcd"); + $dumpvars; + r1 = 1'b0; r2 = 1'b0; r3 = 1'b0; r4 = 1'b0; #50; + r1 = 1'b0; r2 = 1'b0; r3 = 1'b0; r4 = 1'b1; #50; + r1 = 1'b0; r2 = 1'b0; r3 = 1'b1; r4 = 1'b0; #50; + r1 = 1'b0; r2 = 1'b0; r3 = 1'b1; r4 = 1'b1; #50; + r1 = 1'b0; r2 = 1'b1; r3 = 1'b0; r4 = 1'b0; #50; + r1 = 1'b0; r2 = 1'b1; r3 = 1'b0; r4 = 1'b1; #50; + r1 = 1'b0; r2 = 1'b1; r3 = 1'b1; r4 = 1'b0; #50; + r1 = 1'b0; r2 = 1'b1; r3 = 1'b1; r4 = 1'b1; #50; + $display(w1); +end + + + +endmodule \ No newline at end of file diff --git a/lab3/impl/gwsynthesis/lab3.log b/lab3/impl/gwsynthesis/lab3.log new file mode 100644 index 0000000..6712f17 --- /dev/null +++ b/lab3/impl/gwsynthesis/lab3.log @@ -0,0 +1,23 @@ +GowinSynthesis start +Running parser ... +Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v' +Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v' +ERROR (EX3615) : '.name implicit port connection' is not allowed in this dialect, use SystemVerilog mode instead("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":7) +ERROR (EX3863) : Syntax error near '['("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":7) +ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16) +ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16) +ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16) +ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16) +ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16) +ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17) +ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17) +ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17) +ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17) +ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17) +ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18) +ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18) +ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18) +ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18) +ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18) +Sorry, too many errors.. +GowinSynthesis finish diff --git a/lab3/impl/gwsynthesis/lab3.prj b/lab3/impl/gwsynthesis/lab3.prj new file mode 100644 index 0000000..0e53b35 --- /dev/null +++ b/lab3/impl/gwsynthesis/lab3.prj @@ -0,0 +1,20 @@ + + + + beta + + + + + + + + diff --git a/lab3/impl/gwsynthesis/lab3.vg b/lab3/impl/gwsynthesis/lab3.vg new file mode 100644 index 0000000..6c95254 --- /dev/null +++ b/lab3/impl/gwsynthesis/lab3.vg @@ -0,0 +1,125 @@ +// +//Written by GowinSynthesis +//Tool Version "V1.9.9.02" +//Sat Apr 13 05:09:20 2024 + +//Source file index table: +//file0 "\C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v" +`timescale 100 ps/100 ps +module Adder3Bit ( + num1, + num2, + Carry, + sum +) +; +input [2:0] num1; +input [2:0] num2; +output [2:0] Carry; +output [2:0] sum; +wire [2:0] num1_d; +wire [2:0] num2_d; +wire [2:0] sum_d; +wire [2:0] Carry_d; +wire VCC; +wire GND; + IBUF num1_0_ibuf ( + .O(num1_d[0]), + .I(num1[0]) +); + IBUF num1_1_ibuf ( + .O(num1_d[1]), + .I(num1[1]) +); + IBUF num1_2_ibuf ( + .O(num1_d[2]), + .I(num1[2]) +); + IBUF num2_0_ibuf ( + .O(num2_d[0]), + .I(num2[0]) +); + IBUF num2_1_ibuf ( + .O(num2_d[1]), + .I(num2[1]) +); + IBUF num2_2_ibuf ( + .O(num2_d[2]), + .I(num2[2]) +); + OBUF Carry_0_obuf ( + .O(Carry[0]), + .I(Carry_d[0]) +); + OBUF Carry_1_obuf ( + .O(Carry[1]), + .I(Carry_d[1]) +); + OBUF Carry_2_obuf ( + .O(Carry[2]), + .I(Carry_d[2]) +); + OBUF sum_0_obuf ( + .O(sum[0]), + .I(sum_d[0]) +); + OBUF sum_1_obuf ( + .O(sum[1]), + .I(sum_d[1]) +); + OBUF sum_2_obuf ( + .O(sum[2]), + .I(sum_d[2]) +); + LUT2 sum_d_0_s ( + .F(sum_d[0]), + .I0(num1_d[0]), + .I1(num2_d[0]) +); +defparam sum_d_0_s.INIT=4'h6; + LUT2 Carry_d_0_s ( + .F(Carry_d[0]), + .I0(num1_d[0]), + .I1(num2_d[0]) +); +defparam Carry_d_0_s.INIT=4'h8; + LUT4 Carry_d_1_s ( + .F(Carry_d[1]), + .I0(num1_d[1]), + .I1(num2_d[1]), + .I2(num1_d[0]), + .I3(num2_d[0]) +); +defparam Carry_d_1_s.INIT=16'hE888; + LUT3 sum_d_2_s ( + .F(sum_d[2]), + .I0(Carry_d[1]), + .I1(num1_d[2]), + .I2(num2_d[2]) +); +defparam sum_d_2_s.INIT=8'h96; + LUT3 Carry_d_2_s ( + .F(Carry_d[2]), + .I0(Carry_d[1]), + .I1(num1_d[2]), + .I2(num2_d[2]) +); +defparam Carry_d_2_s.INIT=8'hE8; + LUT4 sum_d_1_s0 ( + .F(sum_d[1]), + .I0(num1_d[0]), + .I1(num2_d[0]), + .I2(num1_d[1]), + .I3(num2_d[1]) +); +defparam sum_d_1_s0.INIT=16'h8778; + VCC VCC_cZ ( + .V(VCC) +); + GND GND_cZ ( + .G(GND) +); + GSR GSR ( + .GSRI(VCC) +); +endmodule /* Adder3Bit */ diff --git a/lab3/impl/gwsynthesis/lab3_syn.rpt.html b/lab3/impl/gwsynthesis/lab3_syn.rpt.html new file mode 100644 index 0000000..df7f4a6 --- /dev/null +++ b/lab3/impl/gwsynthesis/lab3_syn.rpt.html @@ -0,0 +1,175 @@ + + + +synthesis Report + + + +
+ +
+

Synthesis Messages

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Report TitleGowinSynthesis Report
Design FileC:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v
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GowinSynthesis Constraints File---
Tool VersionV1.9.9.02
Part NumberGW2A-LV18PG256C8/I7
DeviceGW2A-18
Device VersionC
Created TimeSat Apr 13 05:09:20 2024 +
Legal AnnouncementCopyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.
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Synthesis Details

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Top Level ModuleAdder3Bit
Synthesis ProcessRunning parser:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.093s, Peak memory usage = 156.254MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 156.254MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 156.254MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 156.254MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 156.254MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 156.254MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 156.254MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.301s, Peak memory usage = 172.207MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 172.207MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 172.207MB
Total Time and Memory UsageCPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.483s, Peak memory usage = 172.207MB
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Resource

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Resource Usage Summary

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ResourceUsage
I/O Port 12
I/O Buf 12
    IBUF6
    OBUF6
LUT 6
    LUT22
    LUT32
    LUT42
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Resource Utilization Summary

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ResourceUsageUtilization
Logic6(6 LUT, 0 ALU) / 20736<1%
Register0 / 161730%
  --Register as Latch0 / 161730%
  --Register as FF0 / 161730%
BSRAM0 / 460%
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+ + diff --git a/lab3/impl/gwsynthesis/lab3_syn_resource.html b/lab3/impl/gwsynthesis/lab3_syn_resource.html new file mode 100644 index 0000000..7f620ee --- /dev/null +++ b/lab3/impl/gwsynthesis/lab3_syn_resource.html @@ -0,0 +1,46 @@ + + + +Hierarchy Module Resource + + + +
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Hierarchy Module Resource

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MODULE NAMEREG NUMBERALU NUMBERLUT NUMBERDSP NUMBERBSRAM NUMBERSSRAM NUMBERROM16 NUMBER
Adder3Bit (C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v)--6----
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+ + diff --git a/lab3/impl/gwsynthesis/lab3_syn_rsc.xml b/lab3/impl/gwsynthesis/lab3_syn_rsc.xml new file mode 100644 index 0000000..c7626f3 --- /dev/null +++ b/lab3/impl/gwsynthesis/lab3_syn_rsc.xml @@ -0,0 +1,2 @@ + + diff --git a/lab3/impl/lab3_process_config.json b/lab3/impl/lab3_process_config.json new file mode 100644 index 0000000..fc2e964 --- /dev/null +++ b/lab3/impl/lab3_process_config.json @@ -0,0 +1,88 @@ +{ + "BACKGROUND_PROGRAMMING" : "off", + "COMPRESS" : false, + "CPU" : false, + "CRC_CHECK" : true, + "Clock_Route_Order" : 0, + "Correct_Hold_Violation" : true, + "DONE" : false, + "DOWNLOAD_SPEED" : "default", + "Disable_Insert_Pad" : false, + "ENABLE_CTP" : false, + "ENABLE_MERGE_MODE" : false, + "ENCRYPTION_KEY" : false, + "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000", + "ERROR_DECTION_AND_CORRECTION" : false, + "ERROR_DECTION_ONLY" : false, + "ERROR_INJECTION" : false, + "EXTERNAL_MASTER_CONFIG_CLOCK" : false, + "Enable_DSRM" : false, + "FORMAT" : "binary", + "FREQUENCY_DIVIDER" : "", + "Generate_Constraint_File_of_Ports" : false, + "Generate_IBIS_File" : false, + "Generate_Plain_Text_Timing_Report" : false, + "Generate_Post_PNR_Simulation_Model_File" : false, + "Generate_Post_Place_File" : false, + "Generate_SDF_File" : false, + "Generate_VHDL_Post_PNR_Simulation_Model_File" : false, + "Global_Freq" : "default", + "GwSyn_Loop_Limit" : 2000, + "HOTBOOT" : false, + "I2C" : false, + "I2C_SLAVE_ADDR" : "00", + "IncludePath" : [ + + ], + "Incremental_Compile" : "", + "Initialize_Primitives" : false, + "JTAG" : false, + "MODE_IO" : false, + "MSPI" : false, + "MSPI_JUMP" : false, + "MULTIBOOT_ADDRESS_WIDTH" : "24", + "MULTIBOOT_MODE" : "Normal", + "MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000", + "MULTIJUMP_ADDRESS_WIDTH" : "24", + "MULTIJUMP_MODE" : "Normal", + "MULTIJUMP_SPI_FLASH_ADDRESS" : "000000", + "Multi_Boot" : true, + "OUTPUT_BASE_NAME" : "lab3", + "POWER_ON_RESET_MONITOR" : true, + "PRINT_BSRAM_VALUE" : true, + "PROGRAM_DONE_BYPASS" : false, + "PlaceInRegToIob" : true, + "PlaceIoRegToIob" : true, + "PlaceOutRegToIob" : true, + "Place_Option" : "0", + "Process_Configuration_Verion" : "1.0", + "Promote_Physical_Constraint_Warning_to_Error" : true, + "READY" : false, + "RECONFIG_N" : false, + "Ram_RW_Check" : false, + "Replicate_Resources" : false, + "Report_Auto-Placed_Io_Information" : false, + "Route_Maxfan" : 23, + "Route_Option" : "0", + "Run_Timing_Driven" : true, + "SECURE_MODE" : false, + "SECURITY_BIT" : true, + "SEU_HANDLER" : false, + "SEU_HANDLER_CHECKSUM" : false, + "SEU_HANDLER_MODE" : "auto", + "SSPI" : false, + "STOP_SEU_HANDLER" : false, + "Show_All_Warnings" : false, + "Synthesize_tool" : "GowinSyn", + "TclPre" : "", + "TopModule" : "", + "USERCODE" : "default", + "Unused_Pin" : "As_input_tri_stated_with_pull_up", + "VCCAUX" : 3.3, + "VCCX" : "3.3", + "VHDL_Standard" : "VHDL_Std_1993", + "Verilog_Standard" : "Vlg_Std_2001", + "WAKE_UP" : "0", + "show_all_warnings" : false, + "turn_off_bg" : false +} \ No newline at end of file diff --git a/lab3/impl/temp/rtl_parser.result b/lab3/impl/temp/rtl_parser.result new file mode 100644 index 0000000..7a4dd2f --- /dev/null +++ b/lab3/impl/temp/rtl_parser.result @@ -0,0 +1,10 @@ +[ + { + "InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v", + "InstLine" : 1, + "InstName" : "Adder3Bit", + "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v", + "ModuleLine" : 1, + "ModuleName" : "Adder3Bit" + } +] \ No newline at end of file diff --git a/lab3/impl/temp/rtl_parser_arg.json b/lab3/impl/temp/rtl_parser_arg.json new file mode 100644 index 0000000..039dd82 --- /dev/null +++ b/lab3/impl/temp/rtl_parser_arg.json @@ -0,0 +1,21 @@ +{ + "Device" : "GW2A-18C", + "Files" : [ + { + "Path" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v", + "Type" : "verilog" + }, + { + "Path" : "C:/cygwin64/home/koray/verilog/lab3/src/tbAdder3Bit.v", + "Type" : "verilog" + } + ], + "IncludePath" : [ + + ], + "LoopLimit" : 2000, + "ResultFile" : "C:/cygwin64/home/koray/verilog/lab3/impl/temp/rtl_parser.result", + "Top" : "", + "VerilogStd" : "verilog_2001", + "VhdlStd" : "vhdl_93" +} \ No newline at end of file diff --git a/lab3/lab3.gprj b/lab3/lab3.gprj new file mode 100644 index 0000000..942c8a5 --- /dev/null +++ b/lab3/lab3.gprj @@ -0,0 +1,11 @@ + + + + + 5 + gw2a18c-011 + + + + + diff --git a/lab3/lab3.gprj.user b/lab3/lab3.gprj.user new file mode 100644 index 0000000..9f1741c --- /dev/null +++ b/lab3/lab3.gprj.user @@ -0,0 +1,13 @@ + + + + 1.0 + + + + + + + + 000000ff00000001fd00000002000000000000017000000281fc0200000001fc00000063000002810000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000078000000121fc0100000001fc0000000000000780000000a100fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000007800fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100ffffff000006080000028100000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000 + diff --git a/lab3/src/Adder3Bit.v b/lab3/src/Adder3Bit.v new file mode 100644 index 0000000..15899ae --- /dev/null +++ b/lab3/src/Adder3Bit.v @@ -0,0 +1,30 @@ +module Adder3Bit ( + input [2:0] num1, + input [2:0] num2, + output [2:0] Carry, + output [2:0] sum +); + + xor (sum[0], num1[0], num2[0]); + and (Carry[0], num1[0], num2[0]); + + wire num12[1:0]; + wire num12Carry[1:0], num1a2[1:0]; + + xor (num12[0], num1[1], num2[1]); + xor (sum[1], num12[0], Carry[0]); + + and (num12Carry[0], num12[0], Carry[0]); + and (num1a2[0], num1[1], num2[1]); + + or (Carry[1], num12Carry[0], num1a2[0]); + + xor (num12[1], num1[2], num2[2]); + xor (sum[2], num12[1], Carry[1]); + + and (num12Carry[1], num12[1], Carry[1]); + and (num1a2[1], num1[2], num2[2]); + + or (Carry[2], num12Carry[1], num1a2[1]); + +endmodule \ No newline at end of file diff --git a/lab3/src/tbAdder3Bit.v b/lab3/src/tbAdder3Bit.v new file mode 100644 index 0000000..8bd6b52 --- /dev/null +++ b/lab3/src/tbAdder3Bit.v @@ -0,0 +1,28 @@ +module tbAdder3Bit (); + +reg r1[2:0], r2[2:0]; +wire w1[2:0], w2[2:0]; + +Adder3Bit uut( + .num1[2:0](r1[2:0]), + .num2[2:0](r2[2:0]), + .sum[2:0](w1[2:0]), + .Carry[2:0](w2[2:0]) +); + +initial begin + $dumpfile("Admp.vcd"); + $dumpvars; + r1 = 3'b000; r2 = 3'b000; #10 + r1 = 3'b001; r2 = 3'b001; #10 + r1 = 3'b010; r2 = 3'b010; #10 + r1 = 3'b100; r2 = 3'b100; #10 + r1 = 3'b011; r2 = 3'b011; #10 + r1 = 3'b101; r2 = 3'b101; #10 + r1 = 3'b110; r2 = 3'b110; #10 + r1 = 3'b111; r2 = 3'b111; #10 + $display(w1[2:0]); + $display(w2[2:0]); +end + +endmodule \ No newline at end of file diff --git a/test/a.out b/test/a.out new file mode 100644 index 0000000..9c0424d --- /dev/null +++ b/test/a.out @@ -0,0 +1,65 @@ +#! /c/Source/iverilog-install/bin/vvp +:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "C:\iverilog\lib\ivl\system.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi"; +:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi"; +:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi"; +:vpi_module "C:\iverilog\lib\ivl\va_math.vpi"; +S_000001c04a3a6760 .scope module, "tb" "tb" 2 1; + .timescale 0 0; +v000001c04a3a6b20_0 .var "r1", 0 0; +v000001c04a51ba60_0 .var "r2", 0 0; +v000001c04a51bb00_0 .net "w1", 0 0, L_000001c04a518b00; 1 drivers +v000001c04a51bba0_0 .net "w2", 0 0, L_000001c04a518d50; 1 drivers +v000001c04a51bc40_0 .net "w3", 0 0, L_000001c04a517170; 1 drivers +S_000001c04a3a68f0 .scope module, "uut" "test" 2 6, 3 1 0, S_000001c04a3a6760; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /INPUT 1 "B"; + .port_info 2 /OUTPUT 1 "LED1"; + .port_info 3 /OUTPUT 1 "LED2"; + .port_info 4 /OUTPUT 1 "LED3"; +L_000001c04a518b00 .functor BUFZ 1, v000001c04a3a6b20_0, C4<0>, C4<0>, C4<0>; +L_000001c04a518d50 .functor BUFZ 1, v000001c04a51ba60_0, C4<0>, C4<0>, C4<0>; +L_000001c04a517170 .functor OR 1, v000001c04a3a6b20_0, v000001c04a51ba60_0, C4<0>, C4<0>; +v000001c04a519860_0 .net "A", 0 0, v000001c04a3a6b20_0; 1 drivers +v000001c04a516ec0_0 .net "B", 0 0, v000001c04a51ba60_0; 1 drivers +v000001c04a518cb0_0 .net "LED1", 0 0, L_000001c04a518b00; alias, 1 drivers +v000001c04a518a60_0 .net "LED2", 0 0, L_000001c04a518d50; alias, 1 drivers +v000001c04a3a6a80_0 .net "LED3", 0 0, L_000001c04a517170; alias, 1 drivers + .scope S_000001c04a3a6760; +T_0 ; + %vpi_call 2 17 "$dumpfile", "dmp.vcd" {0 0 0}; + %vpi_call 2 18 "$dumpvars" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001c04a3a6b20_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001c04a51ba60_0, 0, 1; + %delay 10, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001c04a3a6b20_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001c04a51ba60_0, 0, 1; + %delay 10, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001c04a3a6b20_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001c04a51ba60_0, 0, 1; + %delay 10, 0; + %vpi_call 2 22 "$display", v000001c04a51bc40_0 {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001c04a3a6b20_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001c04a51ba60_0, 0, 1; + %delay 10, 0; + %vpi_call 2 24 "$display", v000001c04a51bc40_0 {0 0 0}; + %end; + .thread T_0; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "tb.v"; + "test.v"; diff --git a/test/dmp.vcd b/test/dmp.vcd new file mode 100644 index 0000000..3afd5f0 --- /dev/null +++ b/test/dmp.vcd @@ -0,0 +1,48 @@ +$date + Sat Apr 06 17:45:47 2024 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module tb $end +$var wire 1 ! w3 $end +$var wire 1 " w2 $end +$var wire 1 # w1 $end +$var reg 1 $ r1 $end +$var reg 1 % r2 $end +$scope module uut $end +$var wire 1 $ A $end +$var wire 1 % B $end +$var wire 1 # LED1 $end +$var wire 1 " LED2 $end +$var wire 1 ! LED3 $end +$upscope $end +$upscope $end +$enddefinitions $end +$comment Show the parameter values. $end +$dumpall +$end +#0 +$dumpvars +0% +0$ +0# +0" +0! +$end +#10 +1! +1" +1% +#20 +0" +0% +1# +1$ +#30 +1" +1% +#40 diff --git a/test/tb.v b/test/tb.v new file mode 100644 index 0000000..21f7e1f --- /dev/null +++ b/test/tb.v @@ -0,0 +1,29 @@ +module tb(); + +reg r1, r2; +wire w1, w2, w3; + +test uut( + .A(r1), + .B(r2), + .LED1(w1), + .LED2(w2), + .LED3(w3) +); + +// test uut(r1, r2, w1, w2, w3); + +initial begin + $dumpfile("dmp.vcd"); + $dumpvars; + r1 = 0; r2 = 0; #10; + r1 = 0; r2 = 1; #10; + r1 = 1; r2 = 0; #10; + $display(w3); + r1 = 1; r2 = 1; #10; + $display(w3); +end + + + +endmodule \ No newline at end of file diff --git a/test/test.v b/test/test.v new file mode 100644 index 0000000..3492cb6 --- /dev/null +++ b/test/test.v @@ -0,0 +1,20 @@ +module test( + input A, + input B, + output LED1, + output LED2, + output LED3 +); + + +assign LED1 = A; +assign LED2 = B; +assign LED3 = A | B; + +/* +buf(LED1, A); +buf(LED2, B); +and(LED3, A, B); +*/ + +endmodule \ No newline at end of file