36 lines
954 B
Plaintext
36 lines
954 B
Plaintext
[
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{
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"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v",
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"InstLine" : 1,
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"InstName" : "BitM",
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"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v",
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"ModuleLine" : 1,
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"ModuleName" : "BitM"
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},
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{
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"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v",
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"InstLine" : 1,
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"InstName" : "fullAdder",
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"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v",
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"ModuleLine" : 1,
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"ModuleName" : "fullAdder"
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},
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{
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"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
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"InstLine" : 1,
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"InstName" : "tb",
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"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
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"ModuleLine" : 1,
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"ModuleName" : "tb",
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"SubInsts" : [
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{
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"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
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"InstLine" : 6,
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"InstName" : "uut",
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"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/halfAdder.v",
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"ModuleLine" : 1,
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"ModuleName" : "halfAdder"
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}
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]
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}
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] |