verilog/test/dmp.vcd
2024-04-13 05:48:55 +03:00

49 lines
534 B
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$date
Sat Apr 06 17:45:47 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module tb $end
$var wire 1 ! w3 $end
$var wire 1 " w2 $end
$var wire 1 # w1 $end
$var reg 1 $ r1 $end
$var reg 1 % r2 $end
$scope module uut $end
$var wire 1 $ A $end
$var wire 1 % B $end
$var wire 1 # LED1 $end
$var wire 1 " LED2 $end
$var wire 1 ! LED3 $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
0%
0$
0#
0"
0!
$end
#10
1!
1"
1%
#20
0"
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1#
1$
#30
1"
1%
#40