nand2tetris
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kaltinsoy committed
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@@ -7,45 +7,45 @@
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
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S_0x563ba96be200 .scope module, "andGateTB" "andGateTB" 2 1;
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S_0x56317b794200 .scope module, "andGateTB" "andGateTB" 2 1;
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.timescale 0 0;
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v0x563ba96cf140_0 .var "A_i", 0 0;
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v0x563ba96cf210_0 .var "B_i", 0 0;
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v0x563ba96cf2e0_0 .net "Y_o", 0 0, L_0x563ba96cf520; 1 drivers
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S_0x563ba96be390 .scope module, "uut" "andGate" 2 5, 3 1 0, S_0x563ba96be200;
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v0x56317b7a5140_0 .var "A_i", 0 0;
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v0x56317b7a5210_0 .var "B_i", 0 0;
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v0x56317b7a52e0_0 .net "Y_o", 0 0, L_0x56317b7a5520; 1 drivers
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S_0x56317b794390 .scope module, "uut" "andGate" 2 5, 3 1 0, S_0x56317b794200;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A_i";
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.port_info 1 /INPUT 1 "B_i";
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.port_info 2 /OUTPUT 1 "Y_o";
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L_0x563ba96cf3e0 .functor NAND 1, v0x563ba96cf140_0, v0x563ba96cf210_0, C4<1>, C4<1>;
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L_0x563ba96cf520 .functor NAND 1, L_0x563ba96cf3e0, L_0x563ba96cf3e0, C4<1>, C4<1>;
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v0x563ba9686c00_0 .net "A_i", 0 0, v0x563ba96cf140_0; 1 drivers
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v0x563ba96ceea0_0 .net "B_i", 0 0, v0x563ba96cf210_0; 1 drivers
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v0x563ba96cef60_0 .net "Y_o", 0 0, L_0x563ba96cf520; alias, 1 drivers
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v0x563ba96cf000_0 .net "nand_out", 0 0, L_0x563ba96cf3e0; 1 drivers
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.scope S_0x563ba96be200;
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L_0x56317b7a53e0 .functor NAND 1, v0x56317b7a5140_0, v0x56317b7a5210_0, C4<1>, C4<1>;
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L_0x56317b7a5520 .functor NAND 1, L_0x56317b7a53e0, L_0x56317b7a53e0, C4<1>, C4<1>;
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v0x56317b75cc00_0 .net "A_i", 0 0, v0x56317b7a5140_0; 1 drivers
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v0x56317b7a4ea0_0 .net "B_i", 0 0, v0x56317b7a5210_0; 1 drivers
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v0x56317b7a4f60_0 .net "Y_o", 0 0, L_0x56317b7a5520; alias, 1 drivers
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v0x56317b7a5000_0 .net "nand_out", 0 0, L_0x56317b7a53e0; 1 drivers
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.scope S_0x56317b794200;
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T_0 ;
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%vpi_call 2 12 "$dumpfile", "andGate.vcd" {0 0 0};
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%vpi_call 2 13 "$dumpvars" {0 0 0};
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x563ba96cf140_0, 0, 1;
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%store/vec4 v0x56317b7a5140_0, 0, 1;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x563ba96cf210_0, 0, 1;
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%store/vec4 v0x56317b7a5210_0, 0, 1;
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%delay 10, 0;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x563ba96cf140_0, 0, 1;
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%store/vec4 v0x56317b7a5140_0, 0, 1;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x563ba96cf210_0, 0, 1;
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%store/vec4 v0x56317b7a5210_0, 0, 1;
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%delay 10, 0;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x563ba96cf140_0, 0, 1;
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%store/vec4 v0x56317b7a5140_0, 0, 1;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x563ba96cf210_0, 0, 1;
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%store/vec4 v0x56317b7a5210_0, 0, 1;
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%delay 10, 0;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x563ba96cf140_0, 0, 1;
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%store/vec4 v0x56317b7a5140_0, 0, 1;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x563ba96cf210_0, 0, 1;
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%store/vec4 v0x56317b7a5210_0, 0, 1;
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%delay 10, 0;
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%vpi_call 2 26 "$finish" {0 0 0};
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%end;
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@@ -1,7 +1,7 @@
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module andGate (
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input wire A_i,
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input wire B_i,
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output wire Y_o
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input A_i,
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input B_i,
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output Y_o
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);
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wire nand_out;
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@@ -1,5 +1,5 @@
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$date
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Mon Dec 9 22:41:40 2024
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Mon Dec 9 23:49:40 2024
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$end
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$version
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Icarus Verilog
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File renamed without changes.
@@ -0,0 +1,58 @@
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#! /usr/bin/vvp
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:ivl_version "11.0 (stable)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
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S_0x56317b794200 .scope module, "andGateTB" "andGateTB" 2 1;
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.timescale 0 0;
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v0x56317b7a5140_0 .var "A_i", 0 0;
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v0x56317b7a5210_0 .var "B_i", 0 0;
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v0x56317b7a52e0_0 .net "Y_o", 0 0, L_0x56317b7a5520; 1 drivers
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S_0x56317b794390 .scope module, "uut" "andGate" 2 5, 3 1 0, S_0x56317b794200;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A_i";
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.port_info 1 /INPUT 1 "B_i";
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.port_info 2 /OUTPUT 1 "Y_o";
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L_0x56317b7a53e0 .functor NAND 1, v0x56317b7a5140_0, v0x56317b7a5210_0, C4<1>, C4<1>;
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L_0x56317b7a5520 .functor NAND 1, L_0x56317b7a53e0, L_0x56317b7a53e0, C4<1>, C4<1>;
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v0x56317b75cc00_0 .net "A_i", 0 0, v0x56317b7a5140_0; 1 drivers
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v0x56317b7a4ea0_0 .net "B_i", 0 0, v0x56317b7a5210_0; 1 drivers
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v0x56317b7a4f60_0 .net "Y_o", 0 0, L_0x56317b7a5520; alias, 1 drivers
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v0x56317b7a5000_0 .net "nand_out", 0 0, L_0x56317b7a53e0; 1 drivers
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.scope S_0x56317b794200;
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T_0 ;
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%vpi_call 2 12 "$dumpfile", "andGate.vcd" {0 0 0};
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%vpi_call 2 13 "$dumpvars" {0 0 0};
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x56317b7a5140_0, 0, 1;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x56317b7a5210_0, 0, 1;
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%delay 10, 0;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x56317b7a5140_0, 0, 1;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x56317b7a5210_0, 0, 1;
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%delay 10, 0;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x56317b7a5140_0, 0, 1;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x56317b7a5210_0, 0, 1;
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%delay 10, 0;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x56317b7a5140_0, 0, 1;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x56317b7a5210_0, 0, 1;
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%delay 10, 0;
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%vpi_call 2 26 "$finish" {0 0 0};
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%end;
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.thread T_0;
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# The file index is used to find the file name in the following table.
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:file_names 4;
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"N/A";
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"<interactive>";
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"andGateTB.v";
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"andGate.v";
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@@ -0,0 +1,3 @@
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We're going to use 1-bit andGate module for this 16-bit module.
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We already have andGate module made with nands.
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@@ -0,0 +1,12 @@
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module andGate (
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input A_i,
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input B_i,
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output Y_o
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);
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wire nand_out;
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nand nand1 (nand_out, A_i, B_i);
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nand nand2 (Y_o, nand_out, nand_out);
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endmodule
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@@ -0,0 +1,289 @@
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#! /usr/bin/vvp
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:ivl_version "11.0 (stable)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
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S_0x5603be4ff5a0 .scope module, "andSixTGateTB" "andSixTGateTB" 2 1;
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.timescale 0 0;
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v0x5603be521e40_0 .var "A_i", 15 0;
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v0x5603be521f30_0 .var "B_i", 15 0;
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v0x5603be522000_0 .net "Y_o", 15 0, L_0x5603be5261b0; 1 drivers
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S_0x5603be4fe770 .scope module, "uut" "andSixTGate" 2 6, 3 1 0, S_0x5603be4ff5a0;
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.timescale 0 0;
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.port_info 0 /INPUT 16 "A_i";
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.port_info 1 /INPUT 16 "B_i";
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.port_info 2 /OUTPUT 16 "Y_o";
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v0x5603be521b10_0 .net "A_i", 15 0, v0x5603be521e40_0; 1 drivers
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v0x5603be521bf0_0 .net "B_i", 15 0, v0x5603be521f30_0; 1 drivers
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v0x5603be521cd0_0 .net "Y_o", 15 0, L_0x5603be5261b0; alias, 1 drivers
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L_0x5603be5222f0 .part v0x5603be521e40_0, 0, 1;
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L_0x5603be522430 .part v0x5603be521f30_0, 0, 1;
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L_0x5603be5226a0 .part v0x5603be521e40_0, 1, 1;
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L_0x5603be522790 .part v0x5603be521f30_0, 1, 1;
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L_0x5603be5229e0 .part v0x5603be521e40_0, 2, 1;
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L_0x5603be522ad0 .part v0x5603be521f30_0, 2, 1;
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L_0x5603be522d20 .part v0x5603be521e40_0, 3, 1;
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L_0x5603be522e10 .part v0x5603be521f30_0, 3, 1;
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L_0x5603be5230b0 .part v0x5603be521e40_0, 4, 1;
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L_0x5603be5231a0 .part v0x5603be521f30_0, 4, 1;
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L_0x5603be523400 .part v0x5603be521e40_0, 5, 1;
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L_0x5603be5234f0 .part v0x5603be521f30_0, 5, 1;
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L_0x5603be5237b0 .part v0x5603be521e40_0, 6, 1;
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L_0x5603be5238a0 .part v0x5603be521f30_0, 6, 1;
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L_0x5603be523b00 .part v0x5603be521e40_0, 7, 1;
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L_0x5603be523bf0 .part v0x5603be521f30_0, 7, 1;
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L_0x5603be523ed0 .part v0x5603be521e40_0, 8, 1;
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L_0x5603be523fc0 .part v0x5603be521f30_0, 8, 1;
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L_0x5603be5242b0 .part v0x5603be521e40_0, 9, 1;
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L_0x5603be5243a0 .part v0x5603be521f30_0, 9, 1;
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L_0x5603be5240b0 .part v0x5603be521e40_0, 10, 1;
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L_0x5603be5246f0 .part v0x5603be521f30_0, 10, 1;
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L_0x5603be524a00 .part v0x5603be521e40_0, 11, 1;
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L_0x5603be524af0 .part v0x5603be521f30_0, 11, 1;
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L_0x5603be524e10 .part v0x5603be521e40_0, 12, 1;
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L_0x5603be524f00 .part v0x5603be521f30_0, 12, 1;
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L_0x5603be525230 .part v0x5603be521e40_0, 13, 1;
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L_0x5603be525320 .part v0x5603be521f30_0, 13, 1;
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L_0x5603be525660 .part v0x5603be521e40_0, 14, 1;
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L_0x5603be525960 .part v0x5603be521f30_0, 14, 1;
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L_0x5603be525ec0 .part v0x5603be521e40_0, 15, 1;
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L_0x5603be525fb0 .part v0x5603be521f30_0, 15, 1;
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LS_0x5603be5261b0_0_0 .concat8 [ 1 1 1 1], L_0x5603be522200, L_0x5603be5225e0, L_0x5603be522920, L_0x5603be522cb0;
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LS_0x5603be5261b0_0_4 .concat8 [ 1 1 1 1], L_0x5603be522fc0, L_0x5603be523360, L_0x5603be5236c0, L_0x5603be523a10;
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LS_0x5603be5261b0_0_8 .concat8 [ 1 1 1 1], L_0x5603be523de0, L_0x5603be5241c0, L_0x5603be5245b0, L_0x5603be524910;
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LS_0x5603be5261b0_0_12 .concat8 [ 1 1 1 1], L_0x5603be524d20, L_0x5603be525140, L_0x5603be525570, L_0x5603be525dd0;
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L_0x5603be5261b0 .concat8 [ 4 4 4 4], LS_0x5603be5261b0_0_0, LS_0x5603be5261b0_0_4, LS_0x5603be5261b0_0_8, LS_0x5603be5261b0_0_12;
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S_0x5603be4fd940 .scope module, "a0" "andGate" 3 7, 4 1 0, S_0x5603be4fe770;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A_i";
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.port_info 1 /INPUT 1 "B_i";
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.port_info 2 /OUTPUT 1 "Y_o";
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L_0x5603be522100 .functor NAND 1, L_0x5603be5222f0, L_0x5603be522430, C4<1>, C4<1>;
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L_0x5603be522200 .functor NAND 1, L_0x5603be522100, L_0x5603be522100, C4<1>, C4<1>;
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v0x5603be4ec5f0_0 .net "A_i", 0 0, L_0x5603be5222f0; 1 drivers
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v0x5603be4eb7c0_0 .net "B_i", 0 0, L_0x5603be522430; 1 drivers
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v0x5603be4ea990_0 .net "Y_o", 0 0, L_0x5603be522200; 1 drivers
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v0x5603be4e9b60_0 .net "nand_out", 0 0, L_0x5603be522100; 1 drivers
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S_0x5603be51c5b0 .scope module, "a1" "andGate" 3 8, 4 1 0, S_0x5603be4fe770;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A_i";
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.port_info 1 /INPUT 1 "B_i";
|
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.port_info 2 /OUTPUT 1 "Y_o";
|
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L_0x5603be522570 .functor NAND 1, L_0x5603be5226a0, L_0x5603be522790, C4<1>, C4<1>;
|
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L_0x5603be5225e0 .functor NAND 1, L_0x5603be522570, L_0x5603be522570, C4<1>, C4<1>;
|
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v0x5603be4e8d30_0 .net "A_i", 0 0, L_0x5603be5226a0; 1 drivers
|
||||
v0x5603be4e7f00_0 .net "B_i", 0 0, L_0x5603be522790; 1 drivers
|
||||
v0x5603be4e70a0_0 .net "Y_o", 0 0, L_0x5603be5225e0; 1 drivers
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v0x5603be51c840_0 .net "nand_out", 0 0, L_0x5603be522570; 1 drivers
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S_0x5603be51c980 .scope module, "a10" "andGate" 3 17, 4 1 0, S_0x5603be4fe770;
|
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.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A_i";
|
||||
.port_info 1 /INPUT 1 "B_i";
|
||||
.port_info 2 /OUTPUT 1 "Y_o";
|
||||
L_0x5603be524540 .functor NAND 1, L_0x5603be5240b0, L_0x5603be5246f0, C4<1>, C4<1>;
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L_0x5603be5245b0 .functor NAND 1, L_0x5603be524540, L_0x5603be524540, C4<1>, C4<1>;
|
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v0x5603be51cbb0_0 .net "A_i", 0 0, L_0x5603be5240b0; 1 drivers
|
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v0x5603be51cc70_0 .net "B_i", 0 0, L_0x5603be5246f0; 1 drivers
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v0x5603be51cd30_0 .net "Y_o", 0 0, L_0x5603be5245b0; 1 drivers
|
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v0x5603be51cdd0_0 .net "nand_out", 0 0, L_0x5603be524540; 1 drivers
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S_0x5603be51cf10 .scope module, "a11" "andGate" 3 18, 4 1 0, S_0x5603be4fe770;
|
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.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A_i";
|
||||
.port_info 1 /INPUT 1 "B_i";
|
||||
.port_info 2 /OUTPUT 1 "Y_o";
|
||||
L_0x5603be5248a0 .functor NAND 1, L_0x5603be524a00, L_0x5603be524af0, C4<1>, C4<1>;
|
||||
L_0x5603be524910 .functor NAND 1, L_0x5603be5248a0, L_0x5603be5248a0, C4<1>, C4<1>;
|
||||
v0x5603be51d140_0 .net "A_i", 0 0, L_0x5603be524a00; 1 drivers
|
||||
v0x5603be51d220_0 .net "B_i", 0 0, L_0x5603be524af0; 1 drivers
|
||||
v0x5603be51d2e0_0 .net "Y_o", 0 0, L_0x5603be524910; 1 drivers
|
||||
v0x5603be51d380_0 .net "nand_out", 0 0, L_0x5603be5248a0; 1 drivers
|
||||
S_0x5603be51d4c0 .scope module, "a12" "andGate" 3 19, 4 1 0, S_0x5603be4fe770;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A_i";
|
||||
.port_info 1 /INPUT 1 "B_i";
|
||||
.port_info 2 /OUTPUT 1 "Y_o";
|
||||
L_0x5603be524cb0 .functor NAND 1, L_0x5603be524e10, L_0x5603be524f00, C4<1>, C4<1>;
|
||||
L_0x5603be524d20 .functor NAND 1, L_0x5603be524cb0, L_0x5603be524cb0, C4<1>, C4<1>;
|
||||
v0x5603be51d740_0 .net "A_i", 0 0, L_0x5603be524e10; 1 drivers
|
||||
v0x5603be51d820_0 .net "B_i", 0 0, L_0x5603be524f00; 1 drivers
|
||||
v0x5603be51d8e0_0 .net "Y_o", 0 0, L_0x5603be524d20; 1 drivers
|
||||
v0x5603be51d980_0 .net "nand_out", 0 0, L_0x5603be524cb0; 1 drivers
|
||||
S_0x5603be51dac0 .scope module, "a13" "andGate" 3 20, 4 1 0, S_0x5603be4fe770;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A_i";
|
||||
.port_info 1 /INPUT 1 "B_i";
|
||||
.port_info 2 /OUTPUT 1 "Y_o";
|
||||
L_0x5603be5250d0 .functor NAND 1, L_0x5603be525230, L_0x5603be525320, C4<1>, C4<1>;
|
||||
L_0x5603be525140 .functor NAND 1, L_0x5603be5250d0, L_0x5603be5250d0, C4<1>, C4<1>;
|
||||
v0x5603be51dcf0_0 .net "A_i", 0 0, L_0x5603be525230; 1 drivers
|
||||
v0x5603be51ddd0_0 .net "B_i", 0 0, L_0x5603be525320; 1 drivers
|
||||
v0x5603be51de90_0 .net "Y_o", 0 0, L_0x5603be525140; 1 drivers
|
||||
v0x5603be51df60_0 .net "nand_out", 0 0, L_0x5603be5250d0; 1 drivers
|
||||
S_0x5603be51e0a0 .scope module, "a14" "andGate" 3 21, 4 1 0, S_0x5603be4fe770;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A_i";
|
||||
.port_info 1 /INPUT 1 "B_i";
|
||||
.port_info 2 /OUTPUT 1 "Y_o";
|
||||
L_0x5603be525500 .functor NAND 1, L_0x5603be525660, L_0x5603be525960, C4<1>, C4<1>;
|
||||
L_0x5603be525570 .functor NAND 1, L_0x5603be525500, L_0x5603be525500, C4<1>, C4<1>;
|
||||
v0x5603be51e2d0_0 .net "A_i", 0 0, L_0x5603be525660; 1 drivers
|
||||
v0x5603be51e3b0_0 .net "B_i", 0 0, L_0x5603be525960; 1 drivers
|
||||
v0x5603be51e470_0 .net "Y_o", 0 0, L_0x5603be525570; 1 drivers
|
||||
v0x5603be51e540_0 .net "nand_out", 0 0, L_0x5603be525500; 1 drivers
|
||||
S_0x5603be51e680 .scope module, "a15" "andGate" 3 22, 4 1 0, S_0x5603be4fe770;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A_i";
|
||||
.port_info 1 /INPUT 1 "B_i";
|
||||
.port_info 2 /OUTPUT 1 "Y_o";
|
||||
L_0x5603be525d60 .functor NAND 1, L_0x5603be525ec0, L_0x5603be525fb0, C4<1>, C4<1>;
|
||||
L_0x5603be525dd0 .functor NAND 1, L_0x5603be525d60, L_0x5603be525d60, C4<1>, C4<1>;
|
||||
v0x5603be51e8b0_0 .net "A_i", 0 0, L_0x5603be525ec0; 1 drivers
|
||||
v0x5603be51e990_0 .net "B_i", 0 0, L_0x5603be525fb0; 1 drivers
|
||||
v0x5603be51ea50_0 .net "Y_o", 0 0, L_0x5603be525dd0; 1 drivers
|
||||
v0x5603be51eb20_0 .net "nand_out", 0 0, L_0x5603be525d60; 1 drivers
|
||||
S_0x5603be51ec60 .scope module, "a2" "andGate" 3 9, 4 1 0, S_0x5603be4fe770;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A_i";
|
||||
.port_info 1 /INPUT 1 "B_i";
|
||||
.port_info 2 /OUTPUT 1 "Y_o";
|
||||
L_0x5603be5228b0 .functor NAND 1, L_0x5603be5229e0, L_0x5603be522ad0, C4<1>, C4<1>;
|
||||
L_0x5603be522920 .functor NAND 1, L_0x5603be5228b0, L_0x5603be5228b0, C4<1>, C4<1>;
|
||||
v0x5603be51ee40_0 .net "A_i", 0 0, L_0x5603be5229e0; 1 drivers
|
||||
v0x5603be51ef20_0 .net "B_i", 0 0, L_0x5603be522ad0; 1 drivers
|
||||
v0x5603be51efe0_0 .net "Y_o", 0 0, L_0x5603be522920; 1 drivers
|
||||
v0x5603be51f0b0_0 .net "nand_out", 0 0, L_0x5603be5228b0; 1 drivers
|
||||
S_0x5603be51f1f0 .scope module, "a3" "andGate" 3 10, 4 1 0, S_0x5603be4fe770;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A_i";
|
||||
.port_info 1 /INPUT 1 "B_i";
|
||||
.port_info 2 /OUTPUT 1 "Y_o";
|
||||
L_0x5603be522c40 .functor NAND 1, L_0x5603be522d20, L_0x5603be522e10, C4<1>, C4<1>;
|
||||
L_0x5603be522cb0 .functor NAND 1, L_0x5603be522c40, L_0x5603be522c40, C4<1>, C4<1>;
|
||||
v0x5603be51f420_0 .net "A_i", 0 0, L_0x5603be522d20; 1 drivers
|
||||
v0x5603be51f500_0 .net "B_i", 0 0, L_0x5603be522e10; 1 drivers
|
||||
v0x5603be51f5c0_0 .net "Y_o", 0 0, L_0x5603be522cb0; 1 drivers
|
||||
v0x5603be51f690_0 .net "nand_out", 0 0, L_0x5603be522c40; 1 drivers
|
||||
S_0x5603be51f7d0 .scope module, "a4" "andGate" 3 11, 4 1 0, S_0x5603be4fe770;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A_i";
|
||||
.port_info 1 /INPUT 1 "B_i";
|
||||
.port_info 2 /OUTPUT 1 "Y_o";
|
||||
L_0x5603be522f50 .functor NAND 1, L_0x5603be5230b0, L_0x5603be5231a0, C4<1>, C4<1>;
|
||||
L_0x5603be522fc0 .functor NAND 1, L_0x5603be522f50, L_0x5603be522f50, C4<1>, C4<1>;
|
||||
v0x5603be51fa00_0 .net "A_i", 0 0, L_0x5603be5230b0; 1 drivers
|
||||
v0x5603be51fae0_0 .net "B_i", 0 0, L_0x5603be5231a0; 1 drivers
|
||||
v0x5603be51fba0_0 .net "Y_o", 0 0, L_0x5603be522fc0; 1 drivers
|
||||
v0x5603be51fc70_0 .net "nand_out", 0 0, L_0x5603be522f50; 1 drivers
|
||||
S_0x5603be51fdb0 .scope module, "a5" "andGate" 3 12, 4 1 0, S_0x5603be4fe770;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A_i";
|
||||
.port_info 1 /INPUT 1 "B_i";
|
||||
.port_info 2 /OUTPUT 1 "Y_o";
|
||||
L_0x5603be5232f0 .functor NAND 1, L_0x5603be523400, L_0x5603be5234f0, C4<1>, C4<1>;
|
||||
L_0x5603be523360 .functor NAND 1, L_0x5603be5232f0, L_0x5603be5232f0, C4<1>, C4<1>;
|
||||
v0x5603be51ffe0_0 .net "A_i", 0 0, L_0x5603be523400; 1 drivers
|
||||
v0x5603be5200c0_0 .net "B_i", 0 0, L_0x5603be5234f0; 1 drivers
|
||||
v0x5603be520180_0 .net "Y_o", 0 0, L_0x5603be523360; 1 drivers
|
||||
v0x5603be520250_0 .net "nand_out", 0 0, L_0x5603be5232f0; 1 drivers
|
||||
S_0x5603be520390 .scope module, "a6" "andGate" 3 13, 4 1 0, S_0x5603be4fe770;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A_i";
|
||||
.port_info 1 /INPUT 1 "B_i";
|
||||
.port_info 2 /OUTPUT 1 "Y_o";
|
||||
L_0x5603be523650 .functor NAND 1, L_0x5603be5237b0, L_0x5603be5238a0, C4<1>, C4<1>;
|
||||
L_0x5603be5236c0 .functor NAND 1, L_0x5603be523650, L_0x5603be523650, C4<1>, C4<1>;
|
||||
v0x5603be5205c0_0 .net "A_i", 0 0, L_0x5603be5237b0; 1 drivers
|
||||
v0x5603be5206a0_0 .net "B_i", 0 0, L_0x5603be5238a0; 1 drivers
|
||||
v0x5603be520760_0 .net "Y_o", 0 0, L_0x5603be5236c0; 1 drivers
|
||||
v0x5603be520830_0 .net "nand_out", 0 0, L_0x5603be523650; 1 drivers
|
||||
S_0x5603be520970 .scope module, "a7" "andGate" 3 14, 4 1 0, S_0x5603be4fe770;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A_i";
|
||||
.port_info 1 /INPUT 1 "B_i";
|
||||
.port_info 2 /OUTPUT 1 "Y_o";
|
||||
L_0x5603be5235e0 .functor NAND 1, L_0x5603be523b00, L_0x5603be523bf0, C4<1>, C4<1>;
|
||||
L_0x5603be523a10 .functor NAND 1, L_0x5603be5235e0, L_0x5603be5235e0, C4<1>, C4<1>;
|
||||
v0x5603be520ba0_0 .net "A_i", 0 0, L_0x5603be523b00; 1 drivers
|
||||
v0x5603be520c80_0 .net "B_i", 0 0, L_0x5603be523bf0; 1 drivers
|
||||
v0x5603be520d40_0 .net "Y_o", 0 0, L_0x5603be523a10; 1 drivers
|
||||
v0x5603be520e10_0 .net "nand_out", 0 0, L_0x5603be5235e0; 1 drivers
|
||||
S_0x5603be520f50 .scope module, "a8" "andGate" 3 15, 4 1 0, S_0x5603be4fe770;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A_i";
|
||||
.port_info 1 /INPUT 1 "B_i";
|
||||
.port_info 2 /OUTPUT 1 "Y_o";
|
||||
L_0x5603be523d70 .functor NAND 1, L_0x5603be523ed0, L_0x5603be523fc0, C4<1>, C4<1>;
|
||||
L_0x5603be523de0 .functor NAND 1, L_0x5603be523d70, L_0x5603be523d70, C4<1>, C4<1>;
|
||||
v0x5603be521180_0 .net "A_i", 0 0, L_0x5603be523ed0; 1 drivers
|
||||
v0x5603be521260_0 .net "B_i", 0 0, L_0x5603be523fc0; 1 drivers
|
||||
v0x5603be521320_0 .net "Y_o", 0 0, L_0x5603be523de0; 1 drivers
|
||||
v0x5603be5213f0_0 .net "nand_out", 0 0, L_0x5603be523d70; 1 drivers
|
||||
S_0x5603be521530 .scope module, "a9" "andGate" 3 16, 4 1 0, S_0x5603be4fe770;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A_i";
|
||||
.port_info 1 /INPUT 1 "B_i";
|
||||
.port_info 2 /OUTPUT 1 "Y_o";
|
||||
L_0x5603be524150 .functor NAND 1, L_0x5603be5242b0, L_0x5603be5243a0, C4<1>, C4<1>;
|
||||
L_0x5603be5241c0 .functor NAND 1, L_0x5603be524150, L_0x5603be524150, C4<1>, C4<1>;
|
||||
v0x5603be521760_0 .net "A_i", 0 0, L_0x5603be5242b0; 1 drivers
|
||||
v0x5603be521840_0 .net "B_i", 0 0, L_0x5603be5243a0; 1 drivers
|
||||
v0x5603be521900_0 .net "Y_o", 0 0, L_0x5603be5241c0; 1 drivers
|
||||
v0x5603be5219d0_0 .net "nand_out", 0 0, L_0x5603be524150; 1 drivers
|
||||
.scope S_0x5603be4ff5a0;
|
||||
T_0 ;
|
||||
%vpi_call 2 13 "$dumpfile", "andSixTGate.vcd" {0 0 0};
|
||||
%vpi_call 2 14 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%store/vec4 v0x5603be521e40_0, 0, 16;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%store/vec4 v0x5603be521f30_0, 0, 16;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%store/vec4 v0x5603be521e40_0, 0, 16;
|
||||
%pushi/vec4 1, 0, 16;
|
||||
%store/vec4 v0x5603be521f30_0, 0, 16;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 16;
|
||||
%store/vec4 v0x5603be521e40_0, 0, 16;
|
||||
%pushi/vec4 1, 0, 16;
|
||||
%store/vec4 v0x5603be521f30_0, 0, 16;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 64, 0, 16;
|
||||
%store/vec4 v0x5603be521e40_0, 0, 16;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%store/vec4 v0x5603be521f30_0, 0, 16;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 64, 0, 16;
|
||||
%store/vec4 v0x5603be521e40_0, 0, 16;
|
||||
%pushi/vec4 64, 0, 16;
|
||||
%store/vec4 v0x5603be521f30_0, 0, 16;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%store/vec4 v0x5603be521e40_0, 0, 16;
|
||||
%pushi/vec4 512, 0, 16;
|
||||
%store/vec4 v0x5603be521f30_0, 0, 16;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 512, 0, 16;
|
||||
%store/vec4 v0x5603be521e40_0, 0, 16;
|
||||
%pushi/vec4 512, 0, 16;
|
||||
%store/vec4 v0x5603be521f30_0, 0, 16;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 65535, 0, 16;
|
||||
%store/vec4 v0x5603be521e40_0, 0, 16;
|
||||
%pushi/vec4 65535, 0, 16;
|
||||
%store/vec4 v0x5603be521f30_0, 0, 16;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 23 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 5;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"andSixTGateTB.v";
|
||||
"andSixTGate.v";
|
||||
"andGate.v";
|
||||
@@ -0,0 +1,24 @@
|
||||
module andSixTGate(
|
||||
input [15:0] A_i,
|
||||
input [15:0] B_i,
|
||||
output [15:0] Y_o
|
||||
);
|
||||
|
||||
andGate a0(A_i[0], B_i[0], Y_o[0]);
|
||||
andGate a1(A_i[1], B_i[1], Y_o[1]);
|
||||
andGate a2(A_i[2], B_i[2], Y_o[2]);
|
||||
andGate a3(A_i[3], B_i[3], Y_o[3]);
|
||||
andGate a4(A_i[4], B_i[4], Y_o[4]);
|
||||
andGate a5(A_i[5], B_i[5], Y_o[5]);
|
||||
andGate a6(A_i[6], B_i[6], Y_o[6]);
|
||||
andGate a7(A_i[7], B_i[7], Y_o[7]);
|
||||
andGate a8(A_i[8], B_i[8], Y_o[8]);
|
||||
andGate a9(A_i[9], B_i[9], Y_o[9]);
|
||||
andGate a10(A_i[10], B_i[10], Y_o[10]);
|
||||
andGate a11(A_i[11], B_i[11], Y_o[11]);
|
||||
andGate a12(A_i[12], B_i[12], Y_o[12]);
|
||||
andGate a13(A_i[13], B_i[13], Y_o[13]);
|
||||
andGate a14(A_i[14], B_i[14], Y_o[14]);
|
||||
andGate a15(A_i[15], B_i[15], Y_o[15]);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,309 @@
|
||||
$date
|
||||
Tue Dec 10 00:39:27 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module andSixTGateTB $end
|
||||
$var wire 16 ! Y_o [15:0] $end
|
||||
$var reg 16 " A_i [15:0] $end
|
||||
$var reg 16 # B_i [15:0] $end
|
||||
$scope module uut $end
|
||||
$var wire 16 $ A_i [15:0] $end
|
||||
$var wire 16 % B_i [15:0] $end
|
||||
$var wire 16 & Y_o [15:0] $end
|
||||
$scope module a0 $end
|
||||
$var wire 1 ' A_i $end
|
||||
$var wire 1 ( B_i $end
|
||||
$var wire 1 ) Y_o $end
|
||||
$var wire 1 * nand_out $end
|
||||
$upscope $end
|
||||
$scope module a1 $end
|
||||
$var wire 1 + A_i $end
|
||||
$var wire 1 , B_i $end
|
||||
$var wire 1 - Y_o $end
|
||||
$var wire 1 . nand_out $end
|
||||
$upscope $end
|
||||
$scope module a10 $end
|
||||
$var wire 1 / A_i $end
|
||||
$var wire 1 0 B_i $end
|
||||
$var wire 1 1 Y_o $end
|
||||
$var wire 1 2 nand_out $end
|
||||
$upscope $end
|
||||
$scope module a11 $end
|
||||
$var wire 1 3 A_i $end
|
||||
$var wire 1 4 B_i $end
|
||||
$var wire 1 5 Y_o $end
|
||||
$var wire 1 6 nand_out $end
|
||||
$upscope $end
|
||||
$scope module a12 $end
|
||||
$var wire 1 7 A_i $end
|
||||
$var wire 1 8 B_i $end
|
||||
$var wire 1 9 Y_o $end
|
||||
$var wire 1 : nand_out $end
|
||||
$upscope $end
|
||||
$scope module a13 $end
|
||||
$var wire 1 ; A_i $end
|
||||
$var wire 1 < B_i $end
|
||||
$var wire 1 = Y_o $end
|
||||
$var wire 1 > nand_out $end
|
||||
$upscope $end
|
||||
$scope module a14 $end
|
||||
$var wire 1 ? A_i $end
|
||||
$var wire 1 @ B_i $end
|
||||
$var wire 1 A Y_o $end
|
||||
$var wire 1 B nand_out $end
|
||||
$upscope $end
|
||||
$scope module a15 $end
|
||||
$var wire 1 C A_i $end
|
||||
$var wire 1 D B_i $end
|
||||
$var wire 1 E Y_o $end
|
||||
$var wire 1 F nand_out $end
|
||||
$upscope $end
|
||||
$scope module a2 $end
|
||||
$var wire 1 G A_i $end
|
||||
$var wire 1 H B_i $end
|
||||
$var wire 1 I Y_o $end
|
||||
$var wire 1 J nand_out $end
|
||||
$upscope $end
|
||||
$scope module a3 $end
|
||||
$var wire 1 K A_i $end
|
||||
$var wire 1 L B_i $end
|
||||
$var wire 1 M Y_o $end
|
||||
$var wire 1 N nand_out $end
|
||||
$upscope $end
|
||||
$scope module a4 $end
|
||||
$var wire 1 O A_i $end
|
||||
$var wire 1 P B_i $end
|
||||
$var wire 1 Q Y_o $end
|
||||
$var wire 1 R nand_out $end
|
||||
$upscope $end
|
||||
$scope module a5 $end
|
||||
$var wire 1 S A_i $end
|
||||
$var wire 1 T B_i $end
|
||||
$var wire 1 U Y_o $end
|
||||
$var wire 1 V nand_out $end
|
||||
$upscope $end
|
||||
$scope module a6 $end
|
||||
$var wire 1 W A_i $end
|
||||
$var wire 1 X B_i $end
|
||||
$var wire 1 Y Y_o $end
|
||||
$var wire 1 Z nand_out $end
|
||||
$upscope $end
|
||||
$scope module a7 $end
|
||||
$var wire 1 [ A_i $end
|
||||
$var wire 1 \ B_i $end
|
||||
$var wire 1 ] Y_o $end
|
||||
$var wire 1 ^ nand_out $end
|
||||
$upscope $end
|
||||
$scope module a8 $end
|
||||
$var wire 1 _ A_i $end
|
||||
$var wire 1 ` B_i $end
|
||||
$var wire 1 a Y_o $end
|
||||
$var wire 1 b nand_out $end
|
||||
$upscope $end
|
||||
$scope module a9 $end
|
||||
$var wire 1 c A_i $end
|
||||
$var wire 1 d B_i $end
|
||||
$var wire 1 e Y_o $end
|
||||
$var wire 1 f nand_out $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
1f
|
||||
0e
|
||||
0d
|
||||
0c
|
||||
1b
|
||||
0a
|
||||
0`
|
||||
0_
|
||||
1^
|
||||
0]
|
||||
0\
|
||||
0[
|
||||
1Z
|
||||
0Y
|
||||
0X
|
||||
0W
|
||||
1V
|
||||
0U
|
||||
0T
|
||||
0S
|
||||
1R
|
||||
0Q
|
||||
0P
|
||||
0O
|
||||
1N
|
||||
0M
|
||||
0L
|
||||
0K
|
||||
1J
|
||||
0I
|
||||
0H
|
||||
0G
|
||||
1F
|
||||
0E
|
||||
0D
|
||||
0C
|
||||
1B
|
||||
0A
|
||||
0@
|
||||
0?
|
||||
1>
|
||||
0=
|
||||
0<
|
||||
0;
|
||||
1:
|
||||
09
|
||||
08
|
||||
07
|
||||
16
|
||||
05
|
||||
04
|
||||
03
|
||||
12
|
||||
01
|
||||
00
|
||||
0/
|
||||
1.
|
||||
0-
|
||||
0,
|
||||
0+
|
||||
1*
|
||||
0)
|
||||
0(
|
||||
0'
|
||||
b0 &
|
||||
b0 %
|
||||
b0 $
|
||||
b0 #
|
||||
b0 "
|
||||
b0 !
|
||||
$end
|
||||
#10
|
||||
1(
|
||||
b1 #
|
||||
b1 %
|
||||
#20
|
||||
b1 !
|
||||
b1 &
|
||||
1)
|
||||
0*
|
||||
1'
|
||||
b1 "
|
||||
b1 $
|
||||
#30
|
||||
b0 !
|
||||
b0 &
|
||||
0)
|
||||
1*
|
||||
0(
|
||||
0'
|
||||
1W
|
||||
b0 #
|
||||
b0 %
|
||||
b1000000 "
|
||||
b1000000 $
|
||||
#40
|
||||
b1000000 !
|
||||
b1000000 &
|
||||
1Y
|
||||
0Z
|
||||
1X
|
||||
b1000000 #
|
||||
b1000000 %
|
||||
#50
|
||||
b0 !
|
||||
b0 &
|
||||
0Y
|
||||
1Z
|
||||
0X
|
||||
1d
|
||||
0W
|
||||
b1000000000 #
|
||||
b1000000000 %
|
||||
b0 "
|
||||
b0 $
|
||||
#60
|
||||
b1000000000 !
|
||||
b1000000000 &
|
||||
1e
|
||||
0f
|
||||
1c
|
||||
b1000000000 "
|
||||
b1000000000 $
|
||||
#70
|
||||
1)
|
||||
1-
|
||||
1I
|
||||
1M
|
||||
1Q
|
||||
1U
|
||||
1Y
|
||||
1]
|
||||
1a
|
||||
11
|
||||
15
|
||||
19
|
||||
1=
|
||||
1A
|
||||
b1111111111111111 !
|
||||
b1111111111111111 &
|
||||
1E
|
||||
0*
|
||||
0.
|
||||
0J
|
||||
0N
|
||||
0R
|
||||
0V
|
||||
0Z
|
||||
0^
|
||||
0b
|
||||
02
|
||||
06
|
||||
0:
|
||||
0>
|
||||
0B
|
||||
0F
|
||||
1(
|
||||
1,
|
||||
1H
|
||||
1L
|
||||
1P
|
||||
1T
|
||||
1X
|
||||
1\
|
||||
1`
|
||||
10
|
||||
14
|
||||
18
|
||||
1<
|
||||
1@
|
||||
1D
|
||||
1'
|
||||
1+
|
||||
1G
|
||||
1K
|
||||
1O
|
||||
1S
|
||||
1W
|
||||
1[
|
||||
1_
|
||||
1/
|
||||
13
|
||||
17
|
||||
1;
|
||||
1?
|
||||
1C
|
||||
b1111111111111111 #
|
||||
b1111111111111111 %
|
||||
b1111111111111111 "
|
||||
b1111111111111111 $
|
||||
#80
|
||||
@@ -0,0 +1,26 @@
|
||||
module andSixTGateTB();
|
||||
reg [15:0] A_i;
|
||||
reg [15:0] B_i;
|
||||
wire [15:0] Y_o;
|
||||
|
||||
andSixTGate uut(
|
||||
.A_i(A_i),
|
||||
.B_i(B_i),
|
||||
.Y_o(Y_o)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("andSixTGate.vcd");
|
||||
$dumpvars;
|
||||
A_i = 16'b0000_0000_0000_0000; B_i = 16'b0000_0000_0000_0000; #10;
|
||||
A_i = 16'b0000_0000_0000_0000; B_i = 16'b0000_0000_0000_0001; #10;
|
||||
A_i = 16'b0000_0000_0000_0001; B_i = 16'b0000_0000_0000_0001; #10;
|
||||
A_i = 16'b0000_0000_0100_0000; B_i = 16'b0000_0000_0000_0000; #10;
|
||||
A_i = 16'b0000_0000_0100_0000; B_i = 16'b0000_0000_0100_0000; #10;
|
||||
A_i = 16'b0000_0000_0000_0000; B_i = 16'b0000_0010_0000_0000; #10;
|
||||
A_i = 16'b0000_0010_0000_0000; B_i = 16'b0000_0010_0000_0000; #10;
|
||||
A_i = 16'b1111_1111_1111_1111; B_i = 16'b1111_1111_1111_1111; #10;
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,66 @@
|
||||
#! /usr/bin/vvp
|
||||
:ivl_version "11.0 (stable)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||
S_0x55e3e0602d50 .scope module, "dmuxGateTB" "dmuxGateTB" 2 1;
|
||||
.timescale 0 0;
|
||||
v0x55e3e0628ba0_0 .var "A_i", 0 0;
|
||||
v0x55e3e0628c60_0 .var "S_i", 0 0;
|
||||
v0x55e3e0628d30_0 .net "Y0_o", 0 0, L_0x55e3e0629100; 1 drivers
|
||||
v0x55e3e0628e30_0 .net "Y1_o", 0 0, L_0x55e3e06292b0; 1 drivers
|
||||
S_0x55e3e0617050 .scope module, "uut" "dmuxGate" 2 5, 3 1 0, S_0x55e3e0602d50;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A_i";
|
||||
.port_info 1 /INPUT 1 "S_i";
|
||||
.port_info 2 /OUTPUT 1 "Y0_o";
|
||||
.port_info 3 /OUTPUT 1 "Y1_o";
|
||||
L_0x55e3e0628f00 .functor NAND 1, v0x55e3e0628c60_0, v0x55e3e0628c60_0, C4<1>, C4<1>;
|
||||
L_0x55e3e0628ff0 .functor NAND 1, L_0x55e3e0628f00, v0x55e3e0628ba0_0, C4<1>, C4<1>;
|
||||
L_0x55e3e0629100 .functor NAND 1, L_0x55e3e0628ff0, L_0x55e3e0628ff0, C4<1>, C4<1>;
|
||||
L_0x55e3e0629210 .functor NAND 1, v0x55e3e0628c60_0, v0x55e3e0628ba0_0, C4<1>, C4<1>;
|
||||
L_0x55e3e06292b0 .functor NAND 1, L_0x55e3e0629210, L_0x55e3e0629210, C4<1>, C4<1>;
|
||||
v0x55e3e06172a0_0 .net "A_i", 0 0, v0x55e3e0628ba0_0; 1 drivers
|
||||
v0x55e3e0628640_0 .net "S_i", 0 0, v0x55e3e0628c60_0; 1 drivers
|
||||
v0x55e3e0628700_0 .net "Y0_o", 0 0, L_0x55e3e0629100; alias, 1 drivers
|
||||
v0x55e3e06287d0_0 .net "Y1_o", 0 0, L_0x55e3e06292b0; alias, 1 drivers
|
||||
v0x55e3e0628890_0 .net "nand2_out", 0 0, L_0x55e3e0628ff0; 1 drivers
|
||||
v0x55e3e06289a0_0 .net "nand4_out", 0 0, L_0x55e3e0629210; 1 drivers
|
||||
v0x55e3e0628a60_0 .net "notS", 0 0, L_0x55e3e0628f00; 1 drivers
|
||||
.scope S_0x55e3e0602d50;
|
||||
T_0 ;
|
||||
%vpi_call 2 13 "$dumpfile", "dmuxGate.vcd" {0 0 0};
|
||||
%vpi_call 2 14 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55e3e0628ba0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55e3e0628c60_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x55e3e0628ba0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55e3e0628c60_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55e3e0628ba0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x55e3e0628c60_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x55e3e0628ba0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x55e3e0628c60_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 20 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"dmuxGateTB.v";
|
||||
"dmuxGate.v";
|
||||
@@ -0,0 +1,16 @@
|
||||
module dmuxGate(
|
||||
input A_i, S_i,
|
||||
output Y0_o, Y1_o
|
||||
);
|
||||
|
||||
wire notS, nand2_out, nand4_out;
|
||||
|
||||
nand nand1(notS, S_i, S_i);
|
||||
|
||||
nand nand2(nand2_out, notS, A_i);
|
||||
nand nand3(Y0_o, nand2_out, nand2_out);
|
||||
|
||||
nand nand4(nand4_out, S_i, A_i);
|
||||
nand nand5(Y1_o, nand4_out, nand4_out);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,50 @@
|
||||
$date
|
||||
Tue Dec 10 00:15:58 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module dmuxGateTB $end
|
||||
$var wire 1 ! Y1_o $end
|
||||
$var wire 1 " Y0_o $end
|
||||
$var reg 1 # A_i $end
|
||||
$var reg 1 $ S_i $end
|
||||
$scope module uut $end
|
||||
$var wire 1 # A_i $end
|
||||
$var wire 1 $ S_i $end
|
||||
$var wire 1 " Y0_o $end
|
||||
$var wire 1 ! Y1_o $end
|
||||
$var wire 1 % nand2_out $end
|
||||
$var wire 1 & nand4_out $end
|
||||
$var wire 1 ' notS $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
1'
|
||||
1&
|
||||
1%
|
||||
0$
|
||||
0#
|
||||
0"
|
||||
0!
|
||||
$end
|
||||
#10
|
||||
1"
|
||||
0%
|
||||
1#
|
||||
#20
|
||||
0"
|
||||
0'
|
||||
1%
|
||||
1$
|
||||
0#
|
||||
#30
|
||||
1!
|
||||
0&
|
||||
1#
|
||||
#40
|
||||
@@ -0,0 +1,23 @@
|
||||
module dmuxGateTB();
|
||||
reg A_i, S_i;
|
||||
wire Y0_o, Y1_o;
|
||||
|
||||
dmuxGate uut(
|
||||
.A_i(A_i),
|
||||
.S_i(S_i),
|
||||
.Y0_o(Y0_o),
|
||||
.Y1_o(Y1_o)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("dmuxGate.vcd");
|
||||
$dumpvars;
|
||||
A_i = 1'b0; S_i = 1'b0; #10;
|
||||
A_i = 1'b1; S_i = 1'b0; #10;
|
||||
|
||||
A_i = 1'b0; S_i = 1'b1; #10;
|
||||
A_i = 1'b1; S_i = 1'b1; #10;
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,73 @@
|
||||
#! /usr/bin/vvp
|
||||
:ivl_version "11.0 (stable)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||
S_0x55620be3ed30 .scope module, "muxGateTB" "muxGateTB" 2 1;
|
||||
.timescale 0 0;
|
||||
v0x55620be51410_0 .var "A_i", 0 0;
|
||||
v0x55620be514d0_0 .var "B_i", 0 0;
|
||||
v0x55620be515a0_0 .var "S_i", 0 0;
|
||||
v0x55620be516a0_0 .net "Y_o", 0 0, L_0x55620be519e0; 1 drivers
|
||||
S_0x55620be3eec0 .scope module, "uut" "muxGate" 2 5, 3 1 0, S_0x55620be3ed30;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A_i";
|
||||
.port_info 1 /INPUT 1 "B_i";
|
||||
.port_info 2 /INPUT 1 "S_i";
|
||||
.port_info 3 /OUTPUT 1 "Y_o";
|
||||
L_0x55620be51770 .functor NAND 1, v0x55620be515a0_0, v0x55620be515a0_0, C4<1>, C4<1>;
|
||||
L_0x55620be51860 .functor NAND 1, v0x55620be51410_0, v0x55620be515a0_0, C4<1>, C4<1>;
|
||||
L_0x55620be51920 .functor NAND 1, v0x55620be514d0_0, L_0x55620be51770, C4<1>, C4<1>;
|
||||
L_0x55620be519e0 .functor NAND 1, L_0x55620be51860, L_0x55620be51920, C4<1>, C4<1>;
|
||||
v0x55620be2c2e0_0 .net "A_i", 0 0, v0x55620be51410_0; 1 drivers
|
||||
v0x55620be50eb0_0 .net "B_i", 0 0, v0x55620be514d0_0; 1 drivers
|
||||
v0x55620be50f70_0 .net "S_i", 0 0, v0x55620be515a0_0; 1 drivers
|
||||
v0x55620be51040_0 .net "Y_o", 0 0, L_0x55620be519e0; alias, 1 drivers
|
||||
v0x55620be51100_0 .net "nand2_out", 0 0, L_0x55620be51860; 1 drivers
|
||||
v0x55620be51210_0 .net "nand3_out", 0 0, L_0x55620be51920; 1 drivers
|
||||
v0x55620be512d0_0 .net "notS", 0 0, L_0x55620be51770; 1 drivers
|
||||
.scope S_0x55620be3ed30;
|
||||
T_0 ;
|
||||
%vpi_call 2 13 "$dumpfile", "muxGate.vcd" {0 0 0};
|
||||
%vpi_call 2 14 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55620be51410_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x55620be514d0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55620be515a0_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x55620be51410_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55620be514d0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55620be515a0_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55620be51410_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x55620be514d0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x55620be515a0_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55620be51410_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x55620be514d0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x55620be515a0_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 19 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"muxGateTB.v";
|
||||
"muxGate.v";
|
||||
@@ -0,0 +1,15 @@
|
||||
module muxGate (
|
||||
input A_i, B_i, S_i,
|
||||
output Y_o
|
||||
);
|
||||
|
||||
wire notS,nand2_out,nand3_out;
|
||||
|
||||
nand nand1(notS, S_i, S_i);
|
||||
|
||||
nand nand2(nand2_out, A_i, S_i);
|
||||
nand nand3(nand3_out, B_i, notS);
|
||||
|
||||
nand nand4(Y_o, nand2_out, nand3_out);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,48 @@
|
||||
$date
|
||||
Tue Dec 10 00:01:05 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module muxGateTB $end
|
||||
$var wire 1 ! Y_o $end
|
||||
$var reg 1 " A_i $end
|
||||
$var reg 1 # B_i $end
|
||||
$var reg 1 $ S_i $end
|
||||
$scope module uut $end
|
||||
$var wire 1 " A_i $end
|
||||
$var wire 1 # B_i $end
|
||||
$var wire 1 $ S_i $end
|
||||
$var wire 1 ! Y_o $end
|
||||
$var wire 1 % nand2_out $end
|
||||
$var wire 1 & nand3_out $end
|
||||
$var wire 1 ' notS $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
1'
|
||||
0&
|
||||
1%
|
||||
0$
|
||||
1#
|
||||
0"
|
||||
1!
|
||||
$end
|
||||
#10
|
||||
0!
|
||||
1&
|
||||
0#
|
||||
1"
|
||||
#20
|
||||
0!
|
||||
0'
|
||||
1&
|
||||
1$
|
||||
1#
|
||||
0"
|
||||
#40
|
||||
@@ -0,0 +1,22 @@
|
||||
module muxGateTB();
|
||||
reg A_i, B_i, S_i;
|
||||
wire Y_o;
|
||||
|
||||
muxGate uut(
|
||||
.A_i(A_i),
|
||||
.B_i(B_i),
|
||||
.S_i(S_i),
|
||||
.Y_o(Y_o)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("muxGate.vcd");
|
||||
$dumpvars;
|
||||
A_i = 1'b0; B_i = 1'b1; S_i = 1'b0; #10;
|
||||
A_i = 1'b1; B_i = 1'b0; S_i = 1'b0; #10;
|
||||
A_i = 1'b0; B_i = 1'b1; S_i = 1'b1; #10;
|
||||
A_i = 1'b0; B_i = 1'b1; S_i = 1'b1; #10;
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
Reference in new issue
Block a user