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xorGate

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This commit is contained in:
k0rrluna 2024-12-09 22:57:42 +03:00
parent 6f6f491135
commit 2acbfd9d8d
29 changed files with 1478 additions and 1231 deletions
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436
bit3-ledTest/bit3 → gowin/OldBit3-ledTest/bit3
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@ -1,218 +1,218 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55f4b1a88210 .scope module, "bit3Tb" "bit3Tb" 2 1;
.timescale 0 0;
v0x55f4b1aba170_0 .var "r1", 2 0;
v0x55f4b1aba230_0 .var "r2", 2 0;
v0x55f4b1aba300_0 .net "w1", 3 0, L_0x55f4b1abb700; 1 drivers
S_0x55f4b1a81ef0 .scope module, "uut" "bit3adder" 2 6, 3 1 0, S_0x55f4b1a88210;
.timescale 0 0;
.port_info 0 /INPUT 3 "A";
.port_info 1 /INPUT 3 "B";
.port_info 2 /OUTPUT 4 "C";
v0x55f4b1ab9cc0_0 .net "A", 2 0, v0x55f4b1aba170_0; 1 drivers
v0x55f4b1ab9dc0_0 .net "B", 2 0, v0x55f4b1aba230_0; 1 drivers
v0x55f4b1ab9ea0_0 .net "C", 3 0, L_0x55f4b1abb700; alias, 1 drivers
v0x55f4b1ab9f60_0 .net "c1", 0 0, L_0x55f4b1aba500; 1 drivers
v0x55f4b1aba000_0 .net "c2", 0 0, L_0x55f4b1ababd0; 1 drivers
L_0x55f4b1aba5c0 .part v0x55f4b1aba170_0, 0, 1;
L_0x55f4b1aba6b0 .part v0x55f4b1aba230_0, 0, 1;
L_0x55f4b1abad10 .part v0x55f4b1aba170_0, 1, 1;
L_0x55f4b1abae40 .part v0x55f4b1aba230_0, 1, 1;
L_0x55f4b1abb340 .part v0x55f4b1aba170_0, 2, 1;
L_0x55f4b1abb500 .part v0x55f4b1aba230_0, 2, 1;
L_0x55f4b1abb700 .concat8 [ 1 1 1 1], L_0x55f4b1aba400, L_0x55f4b1aba9b0, L_0x55f4b1abb090, L_0x55f4b1abb2b0;
S_0x55f4b1a81d10 .scope module, "fa0" "fulladder" 3 10, 4 1 0, S_0x55f4b1a81ef0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C0";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "C";
L_0x55f4b1ababd0 .functor OR 1, L_0x55f4b1abab40, L_0x55f4b1aba8d0, C4<0>, C4<0>;
v0x55f4b1ab7ae0_0 .net "A", 0 0, L_0x55f4b1abad10; 1 drivers
v0x55f4b1ab7ba0_0 .net "B", 0 0, L_0x55f4b1abae40; 1 drivers
v0x55f4b1ab7c70_0 .net "C", 0 0, L_0x55f4b1ababd0; alias, 1 drivers
v0x55f4b1ab7d40_0 .net "C0", 0 0, L_0x55f4b1aba500; alias, 1 drivers
v0x55f4b1ab7e10_0 .net "C1", 0 0, L_0x55f4b1aba8d0; 1 drivers
v0x55f4b1ab7f00_0 .net "C2", 0 0, L_0x55f4b1abab40; 1 drivers
v0x55f4b1ab7fd0_0 .net "S", 0 0, L_0x55f4b1aba9b0; 1 drivers
v0x55f4b1ab80a0_0 .net "S1", 0 0, L_0x55f4b1aba7a0; 1 drivers
S_0x55f4b1a98e60 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x55f4b1a81d10;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x55f4b1aba7a0 .functor XOR 1, L_0x55f4b1abad10, L_0x55f4b1abae40, C4<0>, C4<0>;
L_0x55f4b1aba8d0 .functor AND 1, L_0x55f4b1abad10, L_0x55f4b1abae40, C4<1>, C4<1>;
v0x55f4b1a89ba0_0 .net "A", 0 0, L_0x55f4b1abad10; alias, 1 drivers
v0x55f4b1a89950_0 .net "B", 0 0, L_0x55f4b1abae40; alias, 1 drivers
v0x55f4b1a885d0_0 .net "C", 0 0, L_0x55f4b1aba8d0; alias, 1 drivers
v0x55f4b1a87200_0 .net "S", 0 0, L_0x55f4b1aba7a0; alias, 1 drivers
S_0x55f4b1ab74f0 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x55f4b1a81d10;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x55f4b1aba9b0 .functor XOR 1, L_0x55f4b1aba7a0, L_0x55f4b1aba500, C4<0>, C4<0>;
L_0x55f4b1abab40 .functor AND 1, L_0x55f4b1aba7a0, L_0x55f4b1aba500, C4<1>, C4<1>;
v0x55f4b1ab7760_0 .net "A", 0 0, L_0x55f4b1aba7a0; alias, 1 drivers
v0x55f4b1ab7800_0 .net "B", 0 0, L_0x55f4b1aba500; alias, 1 drivers
v0x55f4b1ab78a0_0 .net "C", 0 0, L_0x55f4b1abab40; alias, 1 drivers
v0x55f4b1ab7970_0 .net "S", 0 0, L_0x55f4b1aba9b0; alias, 1 drivers
S_0x55f4b1ab8190 .scope module, "fa1" "fulladder" 3 11, 4 1 0, S_0x55f4b1a81ef0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C0";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "C";
L_0x55f4b1abb2b0 .functor OR 1, L_0x55f4b1abb220, L_0x55f4b1abb000, C4<0>, C4<0>;
v0x55f4b1ab8fe0_0 .net "A", 0 0, L_0x55f4b1abb340; 1 drivers
v0x55f4b1ab90a0_0 .net "B", 0 0, L_0x55f4b1abb500; 1 drivers
v0x55f4b1ab9170_0 .net "C", 0 0, L_0x55f4b1abb2b0; 1 drivers
v0x55f4b1ab9240_0 .net "C0", 0 0, L_0x55f4b1ababd0; alias, 1 drivers
v0x55f4b1ab9330_0 .net "C1", 0 0, L_0x55f4b1abb000; 1 drivers
v0x55f4b1ab9420_0 .net "C2", 0 0, L_0x55f4b1abb220; 1 drivers
v0x55f4b1ab94c0_0 .net "S", 0 0, L_0x55f4b1abb090; 1 drivers
v0x55f4b1ab9590_0 .net "S1", 0 0, L_0x55f4b1abaf70; 1 drivers
S_0x55f4b1ab8370 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x55f4b1ab8190;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x55f4b1abaf70 .functor XOR 1, L_0x55f4b1abb340, L_0x55f4b1abb500, C4<0>, C4<0>;
L_0x55f4b1abb000 .functor AND 1, L_0x55f4b1abb340, L_0x55f4b1abb500, C4<1>, C4<1>;
v0x55f4b1ab85f0_0 .net "A", 0 0, L_0x55f4b1abb340; alias, 1 drivers
v0x55f4b1ab86d0_0 .net "B", 0 0, L_0x55f4b1abb500; alias, 1 drivers
v0x55f4b1ab8790_0 .net "C", 0 0, L_0x55f4b1abb000; alias, 1 drivers
v0x55f4b1ab8860_0 .net "S", 0 0, L_0x55f4b1abaf70; alias, 1 drivers
S_0x55f4b1ab89d0 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x55f4b1ab8190;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x55f4b1abb090 .functor XOR 1, L_0x55f4b1abaf70, L_0x55f4b1ababd0, C4<0>, C4<0>;
L_0x55f4b1abb220 .functor AND 1, L_0x55f4b1abaf70, L_0x55f4b1ababd0, C4<1>, C4<1>;
v0x55f4b1ab8c40_0 .net "A", 0 0, L_0x55f4b1abaf70; alias, 1 drivers
v0x55f4b1ab8d10_0 .net "B", 0 0, L_0x55f4b1ababd0; alias, 1 drivers
v0x55f4b1ab8de0_0 .net "C", 0 0, L_0x55f4b1abb220; alias, 1 drivers
v0x55f4b1ab8eb0_0 .net "S", 0 0, L_0x55f4b1abb090; alias, 1 drivers
S_0x55f4b1ab9680 .scope module, "ha0" "halfadder" 3 9, 5 1 0, S_0x55f4b1a81ef0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x55f4b1aba400 .functor XOR 1, L_0x55f4b1aba5c0, L_0x55f4b1aba6b0, C4<0>, C4<0>;
L_0x55f4b1aba500 .functor AND 1, L_0x55f4b1aba5c0, L_0x55f4b1aba6b0, C4<1>, C4<1>;
v0x55f4b1ab9900_0 .net "A", 0 0, L_0x55f4b1aba5c0; 1 drivers
v0x55f4b1ab99c0_0 .net "B", 0 0, L_0x55f4b1aba6b0; 1 drivers
v0x55f4b1ab9a80_0 .net "C", 0 0, L_0x55f4b1aba500; alias, 1 drivers
v0x55f4b1ab9ba0_0 .net "S", 0 0, L_0x55f4b1aba400; 1 drivers
.scope S_0x55f4b1a88210;
T_0 ;
%vpi_call 2 13 "$dumpfile", "bit3.vcd" {0 0 0};
%vpi_call 2 14 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 1, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 6, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 4, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 4, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 6, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 1, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 1, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 4, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 6, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%vpi_call 2 33 "$display", "Done" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 6;
"N/A";
"<interactive>";
"bit3Tb.v";
"bit3adder.v";
"fulladder.v";
"halfadder.v";
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55f4b1a88210 .scope module, "bit3Tb" "bit3Tb" 2 1;
.timescale 0 0;
v0x55f4b1aba170_0 .var "r1", 2 0;
v0x55f4b1aba230_0 .var "r2", 2 0;
v0x55f4b1aba300_0 .net "w1", 3 0, L_0x55f4b1abb700; 1 drivers
S_0x55f4b1a81ef0 .scope module, "uut" "bit3adder" 2 6, 3 1 0, S_0x55f4b1a88210;
.timescale 0 0;
.port_info 0 /INPUT 3 "A";
.port_info 1 /INPUT 3 "B";
.port_info 2 /OUTPUT 4 "C";
v0x55f4b1ab9cc0_0 .net "A", 2 0, v0x55f4b1aba170_0; 1 drivers
v0x55f4b1ab9dc0_0 .net "B", 2 0, v0x55f4b1aba230_0; 1 drivers
v0x55f4b1ab9ea0_0 .net "C", 3 0, L_0x55f4b1abb700; alias, 1 drivers
v0x55f4b1ab9f60_0 .net "c1", 0 0, L_0x55f4b1aba500; 1 drivers
v0x55f4b1aba000_0 .net "c2", 0 0, L_0x55f4b1ababd0; 1 drivers
L_0x55f4b1aba5c0 .part v0x55f4b1aba170_0, 0, 1;
L_0x55f4b1aba6b0 .part v0x55f4b1aba230_0, 0, 1;
L_0x55f4b1abad10 .part v0x55f4b1aba170_0, 1, 1;
L_0x55f4b1abae40 .part v0x55f4b1aba230_0, 1, 1;
L_0x55f4b1abb340 .part v0x55f4b1aba170_0, 2, 1;
L_0x55f4b1abb500 .part v0x55f4b1aba230_0, 2, 1;
L_0x55f4b1abb700 .concat8 [ 1 1 1 1], L_0x55f4b1aba400, L_0x55f4b1aba9b0, L_0x55f4b1abb090, L_0x55f4b1abb2b0;
S_0x55f4b1a81d10 .scope module, "fa0" "fulladder" 3 10, 4 1 0, S_0x55f4b1a81ef0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C0";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "C";
L_0x55f4b1ababd0 .functor OR 1, L_0x55f4b1abab40, L_0x55f4b1aba8d0, C4<0>, C4<0>;
v0x55f4b1ab7ae0_0 .net "A", 0 0, L_0x55f4b1abad10; 1 drivers
v0x55f4b1ab7ba0_0 .net "B", 0 0, L_0x55f4b1abae40; 1 drivers
v0x55f4b1ab7c70_0 .net "C", 0 0, L_0x55f4b1ababd0; alias, 1 drivers
v0x55f4b1ab7d40_0 .net "C0", 0 0, L_0x55f4b1aba500; alias, 1 drivers
v0x55f4b1ab7e10_0 .net "C1", 0 0, L_0x55f4b1aba8d0; 1 drivers
v0x55f4b1ab7f00_0 .net "C2", 0 0, L_0x55f4b1abab40; 1 drivers
v0x55f4b1ab7fd0_0 .net "S", 0 0, L_0x55f4b1aba9b0; 1 drivers
v0x55f4b1ab80a0_0 .net "S1", 0 0, L_0x55f4b1aba7a0; 1 drivers
S_0x55f4b1a98e60 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x55f4b1a81d10;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x55f4b1aba7a0 .functor XOR 1, L_0x55f4b1abad10, L_0x55f4b1abae40, C4<0>, C4<0>;
L_0x55f4b1aba8d0 .functor AND 1, L_0x55f4b1abad10, L_0x55f4b1abae40, C4<1>, C4<1>;
v0x55f4b1a89ba0_0 .net "A", 0 0, L_0x55f4b1abad10; alias, 1 drivers
v0x55f4b1a89950_0 .net "B", 0 0, L_0x55f4b1abae40; alias, 1 drivers
v0x55f4b1a885d0_0 .net "C", 0 0, L_0x55f4b1aba8d0; alias, 1 drivers
v0x55f4b1a87200_0 .net "S", 0 0, L_0x55f4b1aba7a0; alias, 1 drivers
S_0x55f4b1ab74f0 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x55f4b1a81d10;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x55f4b1aba9b0 .functor XOR 1, L_0x55f4b1aba7a0, L_0x55f4b1aba500, C4<0>, C4<0>;
L_0x55f4b1abab40 .functor AND 1, L_0x55f4b1aba7a0, L_0x55f4b1aba500, C4<1>, C4<1>;
v0x55f4b1ab7760_0 .net "A", 0 0, L_0x55f4b1aba7a0; alias, 1 drivers
v0x55f4b1ab7800_0 .net "B", 0 0, L_0x55f4b1aba500; alias, 1 drivers
v0x55f4b1ab78a0_0 .net "C", 0 0, L_0x55f4b1abab40; alias, 1 drivers
v0x55f4b1ab7970_0 .net "S", 0 0, L_0x55f4b1aba9b0; alias, 1 drivers
S_0x55f4b1ab8190 .scope module, "fa1" "fulladder" 3 11, 4 1 0, S_0x55f4b1a81ef0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C0";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "C";
L_0x55f4b1abb2b0 .functor OR 1, L_0x55f4b1abb220, L_0x55f4b1abb000, C4<0>, C4<0>;
v0x55f4b1ab8fe0_0 .net "A", 0 0, L_0x55f4b1abb340; 1 drivers
v0x55f4b1ab90a0_0 .net "B", 0 0, L_0x55f4b1abb500; 1 drivers
v0x55f4b1ab9170_0 .net "C", 0 0, L_0x55f4b1abb2b0; 1 drivers
v0x55f4b1ab9240_0 .net "C0", 0 0, L_0x55f4b1ababd0; alias, 1 drivers
v0x55f4b1ab9330_0 .net "C1", 0 0, L_0x55f4b1abb000; 1 drivers
v0x55f4b1ab9420_0 .net "C2", 0 0, L_0x55f4b1abb220; 1 drivers
v0x55f4b1ab94c0_0 .net "S", 0 0, L_0x55f4b1abb090; 1 drivers
v0x55f4b1ab9590_0 .net "S1", 0 0, L_0x55f4b1abaf70; 1 drivers
S_0x55f4b1ab8370 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x55f4b1ab8190;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x55f4b1abaf70 .functor XOR 1, L_0x55f4b1abb340, L_0x55f4b1abb500, C4<0>, C4<0>;
L_0x55f4b1abb000 .functor AND 1, L_0x55f4b1abb340, L_0x55f4b1abb500, C4<1>, C4<1>;
v0x55f4b1ab85f0_0 .net "A", 0 0, L_0x55f4b1abb340; alias, 1 drivers
v0x55f4b1ab86d0_0 .net "B", 0 0, L_0x55f4b1abb500; alias, 1 drivers
v0x55f4b1ab8790_0 .net "C", 0 0, L_0x55f4b1abb000; alias, 1 drivers
v0x55f4b1ab8860_0 .net "S", 0 0, L_0x55f4b1abaf70; alias, 1 drivers
S_0x55f4b1ab89d0 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x55f4b1ab8190;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x55f4b1abb090 .functor XOR 1, L_0x55f4b1abaf70, L_0x55f4b1ababd0, C4<0>, C4<0>;
L_0x55f4b1abb220 .functor AND 1, L_0x55f4b1abaf70, L_0x55f4b1ababd0, C4<1>, C4<1>;
v0x55f4b1ab8c40_0 .net "A", 0 0, L_0x55f4b1abaf70; alias, 1 drivers
v0x55f4b1ab8d10_0 .net "B", 0 0, L_0x55f4b1ababd0; alias, 1 drivers
v0x55f4b1ab8de0_0 .net "C", 0 0, L_0x55f4b1abb220; alias, 1 drivers
v0x55f4b1ab8eb0_0 .net "S", 0 0, L_0x55f4b1abb090; alias, 1 drivers
S_0x55f4b1ab9680 .scope module, "ha0" "halfadder" 3 9, 5 1 0, S_0x55f4b1a81ef0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x55f4b1aba400 .functor XOR 1, L_0x55f4b1aba5c0, L_0x55f4b1aba6b0, C4<0>, C4<0>;
L_0x55f4b1aba500 .functor AND 1, L_0x55f4b1aba5c0, L_0x55f4b1aba6b0, C4<1>, C4<1>;
v0x55f4b1ab9900_0 .net "A", 0 0, L_0x55f4b1aba5c0; 1 drivers
v0x55f4b1ab99c0_0 .net "B", 0 0, L_0x55f4b1aba6b0; 1 drivers
v0x55f4b1ab9a80_0 .net "C", 0 0, L_0x55f4b1aba500; alias, 1 drivers
v0x55f4b1ab9ba0_0 .net "S", 0 0, L_0x55f4b1aba400; 1 drivers
.scope S_0x55f4b1a88210;
T_0 ;
%vpi_call 2 13 "$dumpfile", "bit3.vcd" {0 0 0};
%vpi_call 2 14 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 1, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 6, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 4, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 4, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 6, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 1, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 1, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 4, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 6, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0;
%vpi_call 2 33 "$display", "Done" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 6;
"N/A";
"<interactive>";
"bit3Tb.v";
"bit3adder.v";
"fulladder.v";
"halfadder.v";

462
bit3-ledTest/bit3.vcd → gowin/OldBit3-ledTest/bit3.vcd
View File

@ -1,231 +1,231 @@
$date
Fri Jul 5 03:41:58 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module bit3Tb $end
$var wire 4 ! w1 [3:0] $end
$var reg 3 " r1 [2:0] $end
$var reg 3 # r2 [2:0] $end
$scope module uut $end
$var wire 3 $ A [2:0] $end
$var wire 3 % B [2:0] $end
$var wire 1 & c2 $end
$var wire 1 ' c1 $end
$var wire 4 ( C [3:0] $end
$scope module fa0 $end
$var wire 1 ) A $end
$var wire 1 * B $end
$var wire 1 & C $end
$var wire 1 + S1 $end
$var wire 1 , S $end
$var wire 1 - C2 $end
$var wire 1 . C1 $end
$var wire 1 ' C0 $end
$scope module ha1 $end
$var wire 1 ) A $end
$var wire 1 * B $end
$var wire 1 . C $end
$var wire 1 + S $end
$upscope $end
$scope module ha2 $end
$var wire 1 + A $end
$var wire 1 - C $end
$var wire 1 , S $end
$var wire 1 ' B $end
$upscope $end
$upscope $end
$scope module fa1 $end
$var wire 1 / A $end
$var wire 1 0 B $end
$var wire 1 1 C $end
$var wire 1 & C0 $end
$var wire 1 2 S1 $end
$var wire 1 3 S $end
$var wire 1 4 C2 $end
$var wire 1 5 C1 $end
$scope module ha1 $end
$var wire 1 / A $end
$var wire 1 0 B $end
$var wire 1 5 C $end
$var wire 1 2 S $end
$upscope $end
$scope module ha2 $end
$var wire 1 2 A $end
$var wire 1 & B $end
$var wire 1 4 C $end
$var wire 1 3 S $end
$upscope $end
$upscope $end
$scope module ha0 $end
$var wire 1 6 A $end
$var wire 1 7 B $end
$var wire 1 ' C $end
$var wire 1 8 S $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
18
17
06
05
04
13
12
01
10
0/
0.
0-
1,
1+
1*
0)
b111 (
0'
0&
b111 %
b0 $
b111 #
b0 "
b111 !
$end
#10
07
16
b110 #
b110 %
b1 "
b1 $
#20
17
0*
06
1)
b101 #
b101 %
b10 "
b10 $
#30
07
16
b100 #
b100 %
b11 "
b11 $
#40
17
1*
00
06
0)
1/
b11 #
b11 %
b100 "
b100 $
#50
07
16
b10 #
b10 %
b101 "
b101 $
#60
17
0*
06
1)
b1 #
b1 %
b110 "
b110 $
#70
07
16
b0 #
b0 %
b111 "
b111 $
#80
0,
03
b0 !
b0 (
08
0+
02
06
0)
0/
b0 "
b0 $
#90
b1 !
b1 (
18
16
b1 "
b1 $
#100
1,
b10 !
b10 (
08
1+
06
1)
b10 "
b10 $
#110
b11 !
b11 (
18
16
b11 "
b11 $
#120
0,
13
b100 !
b100 (
08
0+
12
06
0)
1/
b100 "
b100 $
#130
b101 !
b101 (
18
16
b101 "
b101 $
#140
1,
b110 !
b110 (
08
1+
06
1)
b110 "
b110 $
#150
b111 !
b111 (
18
16
b111 "
b111 $
#160
$date
Fri Jul 5 03:41:58 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module bit3Tb $end
$var wire 4 ! w1 [3:0] $end
$var reg 3 " r1 [2:0] $end
$var reg 3 # r2 [2:0] $end
$scope module uut $end
$var wire 3 $ A [2:0] $end
$var wire 3 % B [2:0] $end
$var wire 1 & c2 $end
$var wire 1 ' c1 $end
$var wire 4 ( C [3:0] $end
$scope module fa0 $end
$var wire 1 ) A $end
$var wire 1 * B $end
$var wire 1 & C $end
$var wire 1 + S1 $end
$var wire 1 , S $end
$var wire 1 - C2 $end
$var wire 1 . C1 $end
$var wire 1 ' C0 $end
$scope module ha1 $end
$var wire 1 ) A $end
$var wire 1 * B $end
$var wire 1 . C $end
$var wire 1 + S $end
$upscope $end
$scope module ha2 $end
$var wire 1 + A $end
$var wire 1 - C $end
$var wire 1 , S $end
$var wire 1 ' B $end
$upscope $end
$upscope $end
$scope module fa1 $end
$var wire 1 / A $end
$var wire 1 0 B $end
$var wire 1 1 C $end
$var wire 1 & C0 $end
$var wire 1 2 S1 $end
$var wire 1 3 S $end
$var wire 1 4 C2 $end
$var wire 1 5 C1 $end
$scope module ha1 $end
$var wire 1 / A $end
$var wire 1 0 B $end
$var wire 1 5 C $end
$var wire 1 2 S $end
$upscope $end
$scope module ha2 $end
$var wire 1 2 A $end
$var wire 1 & B $end
$var wire 1 4 C $end
$var wire 1 3 S $end
$upscope $end
$upscope $end
$scope module ha0 $end
$var wire 1 6 A $end
$var wire 1 7 B $end
$var wire 1 ' C $end
$var wire 1 8 S $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
18
17
06
05
04
13
12
01
10
0/
0.
0-
1,
1+
1*
0)
b111 (
0'
0&
b111 %
b0 $
b111 #
b0 "
b111 !
$end
#10
07
16
b110 #
b110 %
b1 "
b1 $
#20
17
0*
06
1)
b101 #
b101 %
b10 "
b10 $
#30
07
16
b100 #
b100 %
b11 "
b11 $
#40
17
1*
00
06
0)
1/
b11 #
b11 %
b100 "
b100 $
#50
07
16
b10 #
b10 %
b101 "
b101 $
#60
17
0*
06
1)
b1 #
b1 %
b110 "
b110 $
#70
07
16
b0 #
b0 %
b111 "
b111 $
#80
0,
03
b0 !
b0 (
08
0+
02
06
0)
0/
b0 "
b0 $
#90
b1 !
b1 (
18
16
b1 "
b1 $
#100
1,
b10 !
b10 (
08
1+
06
1)
b10 "
b10 $
#110
b11 !
b11 (
18
16
b11 "
b11 $
#120
0,
13
b100 !
b100 (
08
0+
12
06
0)
1/
b100 "
b100 $
#130
b101 !
b101 (
18
16
b101 "
b101 $
#140
1,
b110 !
b110 (
08
1+
06
1)
b110 "
b110 $
#150
b111 !
b111 (
18
16
b111 "
b111 $
#160

70
bit3-ledTest/bit3Tb.v → gowin/OldBit3-ledTest/bit3Tb.v
View File

@ -1,36 +1,36 @@
module bit3Tb();
reg [2:0] r1, r2;
wire [3:0] w1;
bit3adder uut(
.A(r1),
.B(r2),
.C(w1)
);
initial begin
$dumpfile("bit3.vcd");
$dumpvars;
r1 = 3'b000; r2 = 3'b111; #10;
r1 = 3'b001; r2 = 3'b110; #10;
r1 = 3'b010; r2 = 3'b101; #10;
r1 = 3'b011; r2 = 3'b100; #10;
r1 = 3'b100; r2 = 3'b011; #10;
r1 = 3'b101; r2 = 3'b010; #10;
r1 = 3'b110; r2 = 3'b001; #10;
r1 = 3'b111; r2 = 3'b000; #10;
r1 = 3'b000; r2 = 3'b000; #10;
r1 = 3'b001; r2 = 3'b000; #10;
r1 = 3'b010; r2 = 3'b000; #10;
r1 = 3'b011; r2 = 3'b000; #10;
r1 = 3'b100; r2 = 3'b000; #10;
r1 = 3'b101; r2 = 3'b000; #10;
r1 = 3'b110; r2 = 3'b000; #10;
r1 = 3'b111; r2 = 3'b000; #10;
$display("Done");
end
module bit3Tb();
reg [2:0] r1, r2;
wire [3:0] w1;
bit3adder uut(
.A(r1),
.B(r2),
.C(w1)
);
initial begin
$dumpfile("bit3.vcd");
$dumpvars;
r1 = 3'b000; r2 = 3'b111; #10;
r1 = 3'b001; r2 = 3'b110; #10;
r1 = 3'b010; r2 = 3'b101; #10;
r1 = 3'b011; r2 = 3'b100; #10;
r1 = 3'b100; r2 = 3'b011; #10;
r1 = 3'b101; r2 = 3'b010; #10;
r1 = 3'b110; r2 = 3'b001; #10;
r1 = 3'b111; r2 = 3'b000; #10;
r1 = 3'b000; r2 = 3'b000; #10;
r1 = 3'b001; r2 = 3'b000; #10;
r1 = 3'b010; r2 = 3'b000; #10;
r1 = 3'b011; r2 = 3'b000; #10;
r1 = 3'b100; r2 = 3'b000; #10;
r1 = 3'b101; r2 = 3'b000; #10;
r1 = 3'b110; r2 = 3'b000; #10;
r1 = 3'b111; r2 = 3'b000; #10;
$display("Done");
end
endmodule

24
bit3-ledTest/fulladder.v → gowin/OldBit3-ledTest/fulladder.v
View File

@ -1,13 +1,13 @@
module fulladder(
input A, B, C0,
output S, C
);
wire S1,C1,C2;
halfadder ha1(A, B, S1, C1);
halfadder ha2(S1, C0, S, C2);
or (C, C2, C1);
module fulladder(
input A, B, C0,
output S, C
);
wire S1,C1,C2;
halfadder ha1(A, B, S1, C1);
halfadder ha2(S1, C0, S, C2);
or (C, C2, C1);
endmodule

16
bit3-ledTest/halfadder.v → gowin/OldBit3-ledTest/halfadder.v
View File

@ -1,9 +1,9 @@
module halfadder(
input A,B,
output S,C
);
xor (S, A, B);
and (C, A, B);
module halfadder(
input A,B,
output S,C
);
xor (S, A, B);
and (C, A, B);
endmodule

378
bit3-ledTest/led1 → gowin/OldBit3-ledTest/led1
View File

@ -1,189 +1,189 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x5585ad829490 .scope module, "ledTest" "ledTest" 2 1;
.timescale 0 0;
.port_info 0 /INPUT 2 "v1";
.port_info 1 /INPUT 2 "v2";
.port_info 2 /OUTPUT 6 "L14";
v0x5585ad857530_0 .var "L14", 5 0;
L_0x7f76fd14c018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x5585ad857610_0 .net/2u *"_ivl_0", 0 0, L_0x7f76fd14c018; 1 drivers
L_0x7f76fd14c060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x5585ad8576f0_0 .net/2u *"_ivl_4", 0 0, L_0x7f76fd14c060; 1 drivers
v0x5585ad8577b0_0 .net "sum", 3 0, L_0x5585ad858d60; 1 drivers
o0x7f76fd195ac8 .functor BUFZ 2, C4<zz>; HiZ drive
v0x5585ad8578a0_0 .net "v1", 1 0, o0x7f76fd195ac8; 0 drivers
o0x7f76fd195af8 .functor BUFZ 2, C4<zz>; HiZ drive
v0x5585ad8579b0_0 .net "v2", 1 0, o0x7f76fd195af8; 0 drivers
E_0x5585ad83ba80 .event edge, v0x5585ad857260_0;
L_0x5585ad858e50 .concat [ 2 1 0 0], o0x7f76fd195ac8, L_0x7f76fd14c018;
L_0x5585ad858f80 .concat [ 2 1 0 0], o0x7f76fd195af8, L_0x7f76fd14c060;
S_0x5585ad822f60 .scope module, "adder" "bit3adder" 2 8, 3 1 0, S_0x5585ad829490;
.timescale 0 0;
.port_info 0 /INPUT 3 "A";
.port_info 1 /INPUT 3 "B";
.port_info 2 /OUTPUT 4 "C";
v0x5585ad857080_0 .net "A", 2 0, L_0x5585ad858e50; 1 drivers
v0x5585ad857180_0 .net "B", 2 0, L_0x5585ad858f80; 1 drivers
v0x5585ad857260_0 .net "C", 3 0, L_0x5585ad858d60; alias, 1 drivers
v0x5585ad857320_0 .net "c1", 0 0, L_0x5585ad857be0; 1 drivers
v0x5585ad8573c0_0 .net "c2", 0 0, L_0x5585ad858280; 1 drivers
L_0x5585ad857d30 .part L_0x5585ad858e50, 0, 1;
L_0x5585ad857dd0 .part L_0x5585ad858f80, 0, 1;
L_0x5585ad8583c0 .part L_0x5585ad858e50, 1, 1;
L_0x5585ad8584f0 .part L_0x5585ad858f80, 1, 1;
L_0x5585ad858ac0 .part L_0x5585ad858e50, 2, 1;
L_0x5585ad858bf0 .part L_0x5585ad858f80, 2, 1;
L_0x5585ad858d60 .concat8 [ 1 1 1 1], L_0x5585ad857b10, L_0x5585ad858060, L_0x5585ad858810, L_0x5585ad858a30;
S_0x5585ad823140 .scope module, "fa0" "fulladder" 3 10, 4 1 0, S_0x5585ad822f60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C0";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "C";
L_0x5585ad858280 .functor OR 1, L_0x5585ad8581f0, L_0x5585ad857f80, C4<0>, C4<0>;
v0x5585ad854ea0_0 .net "A", 0 0, L_0x5585ad8583c0; 1 drivers
v0x5585ad854f60_0 .net "B", 0 0, L_0x5585ad8584f0; 1 drivers
v0x5585ad855030_0 .net "C", 0 0, L_0x5585ad858280; alias, 1 drivers
v0x5585ad855100_0 .net "C0", 0 0, L_0x5585ad857be0; alias, 1 drivers
v0x5585ad8551d0_0 .net "C1", 0 0, L_0x5585ad857f80; 1 drivers
v0x5585ad8552c0_0 .net "C2", 0 0, L_0x5585ad8581f0; 1 drivers
v0x5585ad855390_0 .net "S", 0 0, L_0x5585ad858060; 1 drivers
v0x5585ad855460_0 .net "S1", 0 0, L_0x5585ad857e70; 1 drivers
S_0x5585ad8385a0 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x5585ad823140;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x5585ad857e70 .functor XOR 1, L_0x5585ad8583c0, L_0x5585ad8584f0, C4<0>, C4<0>;
L_0x5585ad857f80 .functor AND 1, L_0x5585ad8583c0, L_0x5585ad8584f0, C4<1>, C4<1>;
v0x5585ad839660_0 .net "A", 0 0, L_0x5585ad8583c0; alias, 1 drivers
v0x5585ad828480_0 .net "B", 0 0, L_0x5585ad8584f0; alias, 1 drivers
v0x5585ad8546d0_0 .net "C", 0 0, L_0x5585ad857f80; alias, 1 drivers
v0x5585ad854770_0 .net "S", 0 0, L_0x5585ad857e70; alias, 1 drivers
S_0x5585ad8548b0 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x5585ad823140;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x5585ad858060 .functor XOR 1, L_0x5585ad857e70, L_0x5585ad857be0, C4<0>, C4<0>;
L_0x5585ad8581f0 .functor AND 1, L_0x5585ad857e70, L_0x5585ad857be0, C4<1>, C4<1>;
v0x5585ad854b20_0 .net "A", 0 0, L_0x5585ad857e70; alias, 1 drivers
v0x5585ad854bc0_0 .net "B", 0 0, L_0x5585ad857be0; alias, 1 drivers
v0x5585ad854c60_0 .net "C", 0 0, L_0x5585ad8581f0; alias, 1 drivers
v0x5585ad854d30_0 .net "S", 0 0, L_0x5585ad858060; alias, 1 drivers
S_0x5585ad855550 .scope module, "fa1" "fulladder" 3 11, 4 1 0, S_0x5585ad822f60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C0";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "C";
L_0x5585ad858a30 .functor OR 1, L_0x5585ad8589a0, L_0x5585ad858730, C4<0>, C4<0>;
v0x5585ad8563a0_0 .net "A", 0 0, L_0x5585ad858ac0; 1 drivers
v0x5585ad856460_0 .net "B", 0 0, L_0x5585ad858bf0; 1 drivers
v0x5585ad856530_0 .net "C", 0 0, L_0x5585ad858a30; 1 drivers
v0x5585ad856600_0 .net "C0", 0 0, L_0x5585ad858280; alias, 1 drivers
v0x5585ad8566f0_0 .net "C1", 0 0, L_0x5585ad858730; 1 drivers
v0x5585ad8567e0_0 .net "C2", 0 0, L_0x5585ad8589a0; 1 drivers
v0x5585ad856880_0 .net "S", 0 0, L_0x5585ad858810; 1 drivers
v0x5585ad856950_0 .net "S1", 0 0, L_0x5585ad858650; 1 drivers
S_0x5585ad855730 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x5585ad855550;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x5585ad858650 .functor XOR 1, L_0x5585ad858ac0, L_0x5585ad858bf0, C4<0>, C4<0>;
L_0x5585ad858730 .functor AND 1, L_0x5585ad858ac0, L_0x5585ad858bf0, C4<1>, C4<1>;
v0x5585ad8559b0_0 .net "A", 0 0, L_0x5585ad858ac0; alias, 1 drivers
v0x5585ad855a90_0 .net "B", 0 0, L_0x5585ad858bf0; alias, 1 drivers
v0x5585ad855b50_0 .net "C", 0 0, L_0x5585ad858730; alias, 1 drivers
v0x5585ad855c20_0 .net "S", 0 0, L_0x5585ad858650; alias, 1 drivers
S_0x5585ad855d90 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x5585ad855550;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x5585ad858810 .functor XOR 1, L_0x5585ad858650, L_0x5585ad858280, C4<0>, C4<0>;
L_0x5585ad8589a0 .functor AND 1, L_0x5585ad858650, L_0x5585ad858280, C4<1>, C4<1>;
v0x5585ad856000_0 .net "A", 0 0, L_0x5585ad858650; alias, 1 drivers
v0x5585ad8560d0_0 .net "B", 0 0, L_0x5585ad858280; alias, 1 drivers
v0x5585ad8561a0_0 .net "C", 0 0, L_0x5585ad8589a0; alias, 1 drivers
v0x5585ad856270_0 .net "S", 0 0, L_0x5585ad858810; alias, 1 drivers
S_0x5585ad856a40 .scope module, "ha0" "halfadder" 3 9, 5 1 0, S_0x5585ad822f60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x5585ad857b10 .functor XOR 1, L_0x5585ad857d30, L_0x5585ad857dd0, C4<0>, C4<0>;
L_0x5585ad857be0 .functor AND 1, L_0x5585ad857d30, L_0x5585ad857dd0, C4<1>, C4<1>;
v0x5585ad856cc0_0 .net "A", 0 0, L_0x5585ad857d30; 1 drivers
v0x5585ad856d80_0 .net "B", 0 0, L_0x5585ad857dd0; 1 drivers
v0x5585ad856e40_0 .net "C", 0 0, L_0x5585ad857be0; alias, 1 drivers
v0x5585ad856f60_0 .net "S", 0 0, L_0x5585ad857b10; 1 drivers
.scope S_0x5585ad829490;
T_0 ;
%wait E_0x5585ad83ba80;
%pushi/vec4 0, 0, 6;
%store/vec4 v0x5585ad857530_0, 0, 6;
%load/vec4 v0x5585ad8577b0_0;
%cmpi/e 0, 0, 4;
%jmp/0xz T_0.0, 4;
%pushi/vec4 0, 0, 6;
%store/vec4 v0x5585ad857530_0, 0, 6;
%jmp T_0.1;
T_0.0 ;
%load/vec4 v0x5585ad8577b0_0;
%cmpi/e 1, 0, 4;
%jmp/0xz T_0.2, 4;
%pushi/vec4 1, 0, 6;
%store/vec4 v0x5585ad857530_0, 0, 6;
%jmp T_0.3;
T_0.2 ;
%load/vec4 v0x5585ad8577b0_0;
%cmpi/e 2, 0, 4;
%jmp/0xz T_0.4, 4;
%pushi/vec4 3, 0, 6;
%store/vec4 v0x5585ad857530_0, 0, 6;
%jmp T_0.5;
T_0.4 ;
%load/vec4 v0x5585ad8577b0_0;
%cmpi/e 3, 0, 4;
%jmp/0xz T_0.6, 4;
%pushi/vec4 7, 0, 6;
%store/vec4 v0x5585ad857530_0, 0, 6;
%jmp T_0.7;
T_0.6 ;
%load/vec4 v0x5585ad8577b0_0;
%cmpi/e 4, 0, 4;
%jmp/0xz T_0.8, 4;
%pushi/vec4 15, 0, 6;
%store/vec4 v0x5585ad857530_0, 0, 6;
T_0.8 ;
T_0.7 ;
T_0.5 ;
T_0.3 ;
T_0.1 ;
%jmp T_0;
.thread T_0, $push;
# The file index is used to find the file name in the following table.
:file_names 6;
"N/A";
"<interactive>";
"ledTest.v";
"bit3adder.v";
"fulladder.v";
"halfadder.v";
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x5585ad829490 .scope module, "ledTest" "ledTest" 2 1;
.timescale 0 0;
.port_info 0 /INPUT 2 "v1";
.port_info 1 /INPUT 2 "v2";
.port_info 2 /OUTPUT 6 "L14";
v0x5585ad857530_0 .var "L14", 5 0;
L_0x7f76fd14c018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x5585ad857610_0 .net/2u *"_ivl_0", 0 0, L_0x7f76fd14c018; 1 drivers
L_0x7f76fd14c060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x5585ad8576f0_0 .net/2u *"_ivl_4", 0 0, L_0x7f76fd14c060; 1 drivers
v0x5585ad8577b0_0 .net "sum", 3 0, L_0x5585ad858d60; 1 drivers
o0x7f76fd195ac8 .functor BUFZ 2, C4<zz>; HiZ drive
v0x5585ad8578a0_0 .net "v1", 1 0, o0x7f76fd195ac8; 0 drivers
o0x7f76fd195af8 .functor BUFZ 2, C4<zz>; HiZ drive
v0x5585ad8579b0_0 .net "v2", 1 0, o0x7f76fd195af8; 0 drivers
E_0x5585ad83ba80 .event edge, v0x5585ad857260_0;
L_0x5585ad858e50 .concat [ 2 1 0 0], o0x7f76fd195ac8, L_0x7f76fd14c018;
L_0x5585ad858f80 .concat [ 2 1 0 0], o0x7f76fd195af8, L_0x7f76fd14c060;
S_0x5585ad822f60 .scope module, "adder" "bit3adder" 2 8, 3 1 0, S_0x5585ad829490;
.timescale 0 0;
.port_info 0 /INPUT 3 "A";
.port_info 1 /INPUT 3 "B";
.port_info 2 /OUTPUT 4 "C";
v0x5585ad857080_0 .net "A", 2 0, L_0x5585ad858e50; 1 drivers
v0x5585ad857180_0 .net "B", 2 0, L_0x5585ad858f80; 1 drivers
v0x5585ad857260_0 .net "C", 3 0, L_0x5585ad858d60; alias, 1 drivers
v0x5585ad857320_0 .net "c1", 0 0, L_0x5585ad857be0; 1 drivers
v0x5585ad8573c0_0 .net "c2", 0 0, L_0x5585ad858280; 1 drivers
L_0x5585ad857d30 .part L_0x5585ad858e50, 0, 1;
L_0x5585ad857dd0 .part L_0x5585ad858f80, 0, 1;
L_0x5585ad8583c0 .part L_0x5585ad858e50, 1, 1;
L_0x5585ad8584f0 .part L_0x5585ad858f80, 1, 1;
L_0x5585ad858ac0 .part L_0x5585ad858e50, 2, 1;
L_0x5585ad858bf0 .part L_0x5585ad858f80, 2, 1;
L_0x5585ad858d60 .concat8 [ 1 1 1 1], L_0x5585ad857b10, L_0x5585ad858060, L_0x5585ad858810, L_0x5585ad858a30;
S_0x5585ad823140 .scope module, "fa0" "fulladder" 3 10, 4 1 0, S_0x5585ad822f60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C0";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "C";
L_0x5585ad858280 .functor OR 1, L_0x5585ad8581f0, L_0x5585ad857f80, C4<0>, C4<0>;
v0x5585ad854ea0_0 .net "A", 0 0, L_0x5585ad8583c0; 1 drivers
v0x5585ad854f60_0 .net "B", 0 0, L_0x5585ad8584f0; 1 drivers
v0x5585ad855030_0 .net "C", 0 0, L_0x5585ad858280; alias, 1 drivers
v0x5585ad855100_0 .net "C0", 0 0, L_0x5585ad857be0; alias, 1 drivers
v0x5585ad8551d0_0 .net "C1", 0 0, L_0x5585ad857f80; 1 drivers
v0x5585ad8552c0_0 .net "C2", 0 0, L_0x5585ad8581f0; 1 drivers
v0x5585ad855390_0 .net "S", 0 0, L_0x5585ad858060; 1 drivers
v0x5585ad855460_0 .net "S1", 0 0, L_0x5585ad857e70; 1 drivers
S_0x5585ad8385a0 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x5585ad823140;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x5585ad857e70 .functor XOR 1, L_0x5585ad8583c0, L_0x5585ad8584f0, C4<0>, C4<0>;
L_0x5585ad857f80 .functor AND 1, L_0x5585ad8583c0, L_0x5585ad8584f0, C4<1>, C4<1>;
v0x5585ad839660_0 .net "A", 0 0, L_0x5585ad8583c0; alias, 1 drivers
v0x5585ad828480_0 .net "B", 0 0, L_0x5585ad8584f0; alias, 1 drivers
v0x5585ad8546d0_0 .net "C", 0 0, L_0x5585ad857f80; alias, 1 drivers
v0x5585ad854770_0 .net "S", 0 0, L_0x5585ad857e70; alias, 1 drivers
S_0x5585ad8548b0 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x5585ad823140;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x5585ad858060 .functor XOR 1, L_0x5585ad857e70, L_0x5585ad857be0, C4<0>, C4<0>;
L_0x5585ad8581f0 .functor AND 1, L_0x5585ad857e70, L_0x5585ad857be0, C4<1>, C4<1>;
v0x5585ad854b20_0 .net "A", 0 0, L_0x5585ad857e70; alias, 1 drivers
v0x5585ad854bc0_0 .net "B", 0 0, L_0x5585ad857be0; alias, 1 drivers
v0x5585ad854c60_0 .net "C", 0 0, L_0x5585ad8581f0; alias, 1 drivers
v0x5585ad854d30_0 .net "S", 0 0, L_0x5585ad858060; alias, 1 drivers
S_0x5585ad855550 .scope module, "fa1" "fulladder" 3 11, 4 1 0, S_0x5585ad822f60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C0";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "C";
L_0x5585ad858a30 .functor OR 1, L_0x5585ad8589a0, L_0x5585ad858730, C4<0>, C4<0>;
v0x5585ad8563a0_0 .net "A", 0 0, L_0x5585ad858ac0; 1 drivers
v0x5585ad856460_0 .net "B", 0 0, L_0x5585ad858bf0; 1 drivers
v0x5585ad856530_0 .net "C", 0 0, L_0x5585ad858a30; 1 drivers
v0x5585ad856600_0 .net "C0", 0 0, L_0x5585ad858280; alias, 1 drivers
v0x5585ad8566f0_0 .net "C1", 0 0, L_0x5585ad858730; 1 drivers
v0x5585ad8567e0_0 .net "C2", 0 0, L_0x5585ad8589a0; 1 drivers
v0x5585ad856880_0 .net "S", 0 0, L_0x5585ad858810; 1 drivers
v0x5585ad856950_0 .net "S1", 0 0, L_0x5585ad858650; 1 drivers
S_0x5585ad855730 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x5585ad855550;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x5585ad858650 .functor XOR 1, L_0x5585ad858ac0, L_0x5585ad858bf0, C4<0>, C4<0>;
L_0x5585ad858730 .functor AND 1, L_0x5585ad858ac0, L_0x5585ad858bf0, C4<1>, C4<1>;
v0x5585ad8559b0_0 .net "A", 0 0, L_0x5585ad858ac0; alias, 1 drivers
v0x5585ad855a90_0 .net "B", 0 0, L_0x5585ad858bf0; alias, 1 drivers
v0x5585ad855b50_0 .net "C", 0 0, L_0x5585ad858730; alias, 1 drivers
v0x5585ad855c20_0 .net "S", 0 0, L_0x5585ad858650; alias, 1 drivers
S_0x5585ad855d90 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x5585ad855550;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x5585ad858810 .functor XOR 1, L_0x5585ad858650, L_0x5585ad858280, C4<0>, C4<0>;
L_0x5585ad8589a0 .functor AND 1, L_0x5585ad858650, L_0x5585ad858280, C4<1>, C4<1>;
v0x5585ad856000_0 .net "A", 0 0, L_0x5585ad858650; alias, 1 drivers
v0x5585ad8560d0_0 .net "B", 0 0, L_0x5585ad858280; alias, 1 drivers
v0x5585ad8561a0_0 .net "C", 0 0, L_0x5585ad8589a0; alias, 1 drivers
v0x5585ad856270_0 .net "S", 0 0, L_0x5585ad858810; alias, 1 drivers
S_0x5585ad856a40 .scope module, "ha0" "halfadder" 3 9, 5 1 0, S_0x5585ad822f60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x5585ad857b10 .functor XOR 1, L_0x5585ad857d30, L_0x5585ad857dd0, C4<0>, C4<0>;
L_0x5585ad857be0 .functor AND 1, L_0x5585ad857d30, L_0x5585ad857dd0, C4<1>, C4<1>;
v0x5585ad856cc0_0 .net "A", 0 0, L_0x5585ad857d30; 1 drivers
v0x5585ad856d80_0 .net "B", 0 0, L_0x5585ad857dd0; 1 drivers
v0x5585ad856e40_0 .net "C", 0 0, L_0x5585ad857be0; alias, 1 drivers
v0x5585ad856f60_0 .net "S", 0 0, L_0x5585ad857b10; 1 drivers
.scope S_0x5585ad829490;
T_0 ;
%wait E_0x5585ad83ba80;
%pushi/vec4 0, 0, 6;
%store/vec4 v0x5585ad857530_0, 0, 6;
%load/vec4 v0x5585ad8577b0_0;
%cmpi/e 0, 0, 4;
%jmp/0xz T_0.0, 4;
%pushi/vec4 0, 0, 6;
%store/vec4 v0x5585ad857530_0, 0, 6;
%jmp T_0.1;
T_0.0 ;
%load/vec4 v0x5585ad8577b0_0;
%cmpi/e 1, 0, 4;
%jmp/0xz T_0.2, 4;
%pushi/vec4 1, 0, 6;
%store/vec4 v0x5585ad857530_0, 0, 6;
%jmp T_0.3;
T_0.2 ;
%load/vec4 v0x5585ad8577b0_0;
%cmpi/e 2, 0, 4;
%jmp/0xz T_0.4, 4;
%pushi/vec4 3, 0, 6;
%store/vec4 v0x5585ad857530_0, 0, 6;
%jmp T_0.5;
T_0.4 ;
%load/vec4 v0x5585ad8577b0_0;
%cmpi/e 3, 0, 4;
%jmp/0xz T_0.6, 4;
%pushi/vec4 7, 0, 6;
%store/vec4 v0x5585ad857530_0, 0, 6;
%jmp T_0.7;
T_0.6 ;
%load/vec4 v0x5585ad8577b0_0;
%cmpi/e 4, 0, 4;
%jmp/0xz T_0.8, 4;
%pushi/vec4 15, 0, 6;
%store/vec4 v0x5585ad857530_0, 0, 6;
T_0.8 ;
T_0.7 ;
T_0.5 ;
T_0.3 ;
T_0.1 ;
%jmp T_0;
.thread T_0, $push;
# The file index is used to find the file name in the following table.
:file_names 6;
"N/A";
"<interactive>";
"ledTest.v";
"bit3adder.v";
"fulladder.v";
"halfadder.v";

64
bit3-ledTest/ledTest.v → gowin/OldBit3-ledTest/ledTest.v
View File

@ -1,33 +1,33 @@
module ledTest (
input[1:0] v1, v2,
output [5:0] L14
);
wire[3:0] sum;
bit3adder adder(
.A({1'b0, v1}),
.B({1'b0, v2}),
.C(sum)
);
always @(*) begin
L14 = 6'b000_000;
if(sum == 4'd0) begin
L14 = 6'b000_000;
end
else if(sum == 4'd1)
L14 = 6'b000_001;
else if(sum == 4'd2)
L14 = 6'b000_011;
else if(sum == 4'd3)
L14 = 6'b000_111;
else if(sum == 4'd4)
L14 = 6'b001_111;
end
module ledTest (
input[1:0] v1, v2,
output [5:0] L14
);
wire[3:0] sum;
bit3adder adder(
.A({1'b0, v1}),
.B({1'b0, v2}),
.C(sum)
);
always @(*) begin
L14 = 6'b000_000;
if(sum == 4'd0) begin
L14 = 6'b000_000;
end
else if(sum == 4'd1)
L14 = 6'b000_001;
else if(sum == 4'd2)
L14 = 6'b000_011;
else if(sum == 4'd3)
L14 = 6'b000_111;
else if(sum == 4'd4)
L14 = 6'b001_111;
end
endmodule

6
bit3-ledTest/ledTest2.v → gowin/OldBit3-ledTest/ledTest2.v
View File

@ -1,4 +1,4 @@
module ledTest2 (
input
)
module ledTest2 (
input
)
// Buton verisi eklenecek TO-DO

344
bit3-ledTest/sub1 → gowin/OldBit3-ledTest/sub1
View File

@ -1,172 +1,172 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55c07506ba60 .scope module, "fulladder" "fulladder" 2 1;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C0";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "C";
L_0x55c0750836c0 .functor OR 1, L_0x55c0750835e0, L_0x55c075083400, C4<0>, C4<0>;
o0x7ffa3a6e3018 .functor BUFZ 1, C4<z>; HiZ drive
v0x55c0750823d0_0 .net "A", 0 0, o0x7ffa3a6e3018; 0 drivers
o0x7ffa3a6e3048 .functor BUFZ 1, C4<z>; HiZ drive
v0x55c075082490_0 .net "B", 0 0, o0x7ffa3a6e3048; 0 drivers
v0x55c075082560_0 .net "C", 0 0, L_0x55c0750836c0; 1 drivers
o0x7ffa3a6e3198 .functor BUFZ 1, C4<z>; HiZ drive
v0x55c075082630_0 .net "C0", 0 0, o0x7ffa3a6e3198; 0 drivers
v0x55c075082700_0 .net "C1", 0 0, L_0x55c075083400; 1 drivers
v0x55c0750827f0_0 .net "C2", 0 0, L_0x55c0750835e0; 1 drivers
v0x55c0750828c0_0 .net "S", 0 0, L_0x55c0750834e0; 1 drivers
v0x55c075082990_0 .net "S1", 0 0, L_0x55c0750832f0; 1 drivers
S_0x55c07506dab0 .scope module, "ha1" "halfadder" 2 8, 3 1 0, S_0x55c07506ba60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x55c0750832f0 .functor XOR 1, o0x7ffa3a6e3018, o0x7ffa3a6e3048, C4<0>, C4<0>;
L_0x55c075083400 .functor AND 1, o0x7ffa3a6e3018, o0x7ffa3a6e3048, C4<1>, C4<1>;
v0x55c07506dd30_0 .net "A", 0 0, o0x7ffa3a6e3018; alias, 0 drivers
v0x55c075081ab0_0 .net "B", 0 0, o0x7ffa3a6e3048; alias, 0 drivers
v0x55c075081b70_0 .net "C", 0 0, L_0x55c075083400; alias, 1 drivers
v0x55c075081c40_0 .net "S", 0 0, L_0x55c0750832f0; alias, 1 drivers
S_0x55c075081db0 .scope module, "ha2" "halfadder" 2 9, 3 1 0, S_0x55c07506ba60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x55c0750834e0 .functor XOR 1, L_0x55c0750832f0, o0x7ffa3a6e3198, C4<0>, C4<0>;
L_0x55c0750835e0 .functor AND 1, L_0x55c0750832f0, o0x7ffa3a6e3198, C4<1>, C4<1>;
v0x55c075082020_0 .net "A", 0 0, L_0x55c0750832f0; alias, 1 drivers
v0x55c0750820f0_0 .net "B", 0 0, o0x7ffa3a6e3198; alias, 0 drivers
v0x55c075082190_0 .net "C", 0 0, L_0x55c0750835e0; alias, 1 drivers
v0x55c075082260_0 .net "S", 0 0, L_0x55c0750834e0; alias, 1 drivers
S_0x55c07506bbf0 .scope module, "test3bitTest" "test3bitTest" 4 1;
.timescale 0 0;
v0x55c075083030_0 .var "r1", 2 0;
v0x55c075083120_0 .var "r2", 2 0;
v0x55c0750831f0_0 .net "w1", 3 0, v0x55c075082ef0_0; 1 drivers
S_0x55c075082a80 .scope module, "uut" "Adder3Bit_behavioral" 4 6, 5 1 0, S_0x55c07506bbf0;
.timescale 0 0;
.port_info 0 /INPUT 3 "A";
.port_info 1 /INPUT 3 "B";
.port_info 2 /OUTPUT 4 "C";
v0x55c075082d10_0 .net "A", 2 0, v0x55c075083030_0; 1 drivers
v0x55c075082e10_0 .net "B", 2 0, v0x55c075083120_0; 1 drivers
v0x55c075082ef0_0 .var "C", 3 0;
E_0x55c075064d90 .event edge, v0x55c075082e10_0, v0x55c075082d10_0;
.scope S_0x55c075082a80;
T_0 ;
%wait E_0x55c075064d90;
%load/vec4 v0x55c075082d10_0;
%pad/u 4;
%load/vec4 v0x55c075082e10_0;
%pad/u 4;
%sub;
%store/vec4 v0x55c075082ef0_0, 0, 4;
%jmp T_0;
.thread T_0, $push;
.scope S_0x55c07506bbf0;
T_1 ;
%vpi_call 4 13 "$dumpfile", "bit3.vcd" {0 0 0};
%vpi_call 4 14 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 1, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 6, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 4, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 4, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 6, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 1, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 1, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 4, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 6, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%vpi_call 4 33 "$display", "Done" {0 0 0};
%end;
.thread T_1;
# The file index is used to find the file name in the following table.
:file_names 6;
"N/A";
"<interactive>";
"fulladder.v";
"halfadder.v";
"test3bitTest.v";
"adder3bitBehavioral.v";
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55c07506ba60 .scope module, "fulladder" "fulladder" 2 1;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C0";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "C";
L_0x55c0750836c0 .functor OR 1, L_0x55c0750835e0, L_0x55c075083400, C4<0>, C4<0>;
o0x7ffa3a6e3018 .functor BUFZ 1, C4<z>; HiZ drive
v0x55c0750823d0_0 .net "A", 0 0, o0x7ffa3a6e3018; 0 drivers
o0x7ffa3a6e3048 .functor BUFZ 1, C4<z>; HiZ drive
v0x55c075082490_0 .net "B", 0 0, o0x7ffa3a6e3048; 0 drivers
v0x55c075082560_0 .net "C", 0 0, L_0x55c0750836c0; 1 drivers
o0x7ffa3a6e3198 .functor BUFZ 1, C4<z>; HiZ drive
v0x55c075082630_0 .net "C0", 0 0, o0x7ffa3a6e3198; 0 drivers
v0x55c075082700_0 .net "C1", 0 0, L_0x55c075083400; 1 drivers
v0x55c0750827f0_0 .net "C2", 0 0, L_0x55c0750835e0; 1 drivers
v0x55c0750828c0_0 .net "S", 0 0, L_0x55c0750834e0; 1 drivers
v0x55c075082990_0 .net "S1", 0 0, L_0x55c0750832f0; 1 drivers
S_0x55c07506dab0 .scope module, "ha1" "halfadder" 2 8, 3 1 0, S_0x55c07506ba60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x55c0750832f0 .functor XOR 1, o0x7ffa3a6e3018, o0x7ffa3a6e3048, C4<0>, C4<0>;
L_0x55c075083400 .functor AND 1, o0x7ffa3a6e3018, o0x7ffa3a6e3048, C4<1>, C4<1>;
v0x55c07506dd30_0 .net "A", 0 0, o0x7ffa3a6e3018; alias, 0 drivers
v0x55c075081ab0_0 .net "B", 0 0, o0x7ffa3a6e3048; alias, 0 drivers
v0x55c075081b70_0 .net "C", 0 0, L_0x55c075083400; alias, 1 drivers
v0x55c075081c40_0 .net "S", 0 0, L_0x55c0750832f0; alias, 1 drivers
S_0x55c075081db0 .scope module, "ha2" "halfadder" 2 9, 3 1 0, S_0x55c07506ba60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x55c0750834e0 .functor XOR 1, L_0x55c0750832f0, o0x7ffa3a6e3198, C4<0>, C4<0>;
L_0x55c0750835e0 .functor AND 1, L_0x55c0750832f0, o0x7ffa3a6e3198, C4<1>, C4<1>;
v0x55c075082020_0 .net "A", 0 0, L_0x55c0750832f0; alias, 1 drivers
v0x55c0750820f0_0 .net "B", 0 0, o0x7ffa3a6e3198; alias, 0 drivers
v0x55c075082190_0 .net "C", 0 0, L_0x55c0750835e0; alias, 1 drivers
v0x55c075082260_0 .net "S", 0 0, L_0x55c0750834e0; alias, 1 drivers
S_0x55c07506bbf0 .scope module, "test3bitTest" "test3bitTest" 4 1;
.timescale 0 0;
v0x55c075083030_0 .var "r1", 2 0;
v0x55c075083120_0 .var "r2", 2 0;
v0x55c0750831f0_0 .net "w1", 3 0, v0x55c075082ef0_0; 1 drivers
S_0x55c075082a80 .scope module, "uut" "Adder3Bit_behavioral" 4 6, 5 1 0, S_0x55c07506bbf0;
.timescale 0 0;
.port_info 0 /INPUT 3 "A";
.port_info 1 /INPUT 3 "B";
.port_info 2 /OUTPUT 4 "C";
v0x55c075082d10_0 .net "A", 2 0, v0x55c075083030_0; 1 drivers
v0x55c075082e10_0 .net "B", 2 0, v0x55c075083120_0; 1 drivers
v0x55c075082ef0_0 .var "C", 3 0;
E_0x55c075064d90 .event edge, v0x55c075082e10_0, v0x55c075082d10_0;
.scope S_0x55c075082a80;
T_0 ;
%wait E_0x55c075064d90;
%load/vec4 v0x55c075082d10_0;
%pad/u 4;
%load/vec4 v0x55c075082e10_0;
%pad/u 4;
%sub;
%store/vec4 v0x55c075082ef0_0, 0, 4;
%jmp T_0;
.thread T_0, $push;
.scope S_0x55c07506bbf0;
T_1 ;
%vpi_call 4 13 "$dumpfile", "bit3.vcd" {0 0 0};
%vpi_call 4 14 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 1, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 6, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 4, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 4, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 6, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 1, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 1, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 4, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 6, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0;
%vpi_call 4 33 "$display", "Done" {0 0 0};
%end;
.thread T_1;
# The file index is used to find the file name in the following table.
:file_names 6;
"N/A";
"<interactive>";
"fulladder.v";
"halfadder.v";
"test3bitTest.v";
"adder3bitBehavioral.v";

47
iverilog/nand2tetris/nands/andGate
View File

@ -7,46 +7,47 @@
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55a27af99200 .scope module, "andGateTB" "andGateTB" 2 1;
S_0x563ba96be200 .scope module, "andGateTB" "andGateTB" 2 1;
.timescale 0 0;
v0x55a27afaa010_0 .var "A", 0 0;
v0x55a27afaa0e0_0 .var "B", 0 0;
v0x55a27afaa1b0_0 .net "Y", 0 0, L_0x55a27afaa3f0; 1 drivers
S_0x55a27af99390 .scope module, "uut" "andGate" 2 5, 3 1 0, S_0x55a27af99200;
v0x563ba96cf140_0 .var "A_i", 0 0;
v0x563ba96cf210_0 .var "B_i", 0 0;
v0x563ba96cf2e0_0 .net "Y_o", 0 0, L_0x563ba96cf520; 1 drivers
S_0x563ba96be390 .scope module, "uut" "andGate" 2 5, 3 1 0, S_0x563ba96be200;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Y";
L_0x55a27afaa2b0 .functor NAND 1, v0x55a27afaa010_0, v0x55a27afaa0e0_0, C4<1>, C4<1>;
L_0x55a27afaa3f0 .functor NAND 1, L_0x55a27afaa2b0, L_0x55a27afaa2b0, C4<1>, C4<1>;
v0x55a27af61c00_0 .net "A", 0 0, v0x55a27afaa010_0; 1 drivers
v0x55a27afa9d70_0 .net "B", 0 0, v0x55a27afaa0e0_0; 1 drivers
v0x55a27afa9e30_0 .net "Y", 0 0, L_0x55a27afaa3f0; alias, 1 drivers
v0x55a27afa9ed0_0 .net "tempOut", 0 0, L_0x55a27afaa2b0; 1 drivers
.scope S_0x55a27af99200;
.port_info 0 /INPUT 1 "A_i";
.port_info 1 /INPUT 1 "B_i";
.port_info 2 /OUTPUT 1 "Y_o";
L_0x563ba96cf3e0 .functor NAND 1, v0x563ba96cf140_0, v0x563ba96cf210_0, C4<1>, C4<1>;
L_0x563ba96cf520 .functor NAND 1, L_0x563ba96cf3e0, L_0x563ba96cf3e0, C4<1>, C4<1>;
v0x563ba9686c00_0 .net "A_i", 0 0, v0x563ba96cf140_0; 1 drivers
v0x563ba96ceea0_0 .net "B_i", 0 0, v0x563ba96cf210_0; 1 drivers
v0x563ba96cef60_0 .net "Y_o", 0 0, L_0x563ba96cf520; alias, 1 drivers
v0x563ba96cf000_0 .net "nand_out", 0 0, L_0x563ba96cf3e0; 1 drivers
.scope S_0x563ba96be200;
T_0 ;
%vpi_call 2 12 "$dumpfile", "andGate.vcd" {0 0 0};
%vpi_call 2 13 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a27afaa010_0, 0, 1;
%store/vec4 v0x563ba96cf140_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a27afaa0e0_0, 0, 1;
%store/vec4 v0x563ba96cf210_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a27afaa010_0, 0, 1;
%store/vec4 v0x563ba96cf140_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a27afaa0e0_0, 0, 1;
%store/vec4 v0x563ba96cf210_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a27afaa010_0, 0, 1;
%store/vec4 v0x563ba96cf140_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a27afaa0e0_0, 0, 1;
%store/vec4 v0x563ba96cf210_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a27afaa010_0, 0, 1;
%store/vec4 v0x563ba96cf140_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a27afaa0e0_0, 0, 1;
%store/vec4 v0x563ba96cf210_0, 0, 1;
%delay 10, 0;
%vpi_call 2 26 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.

13
iverilog/nand2tetris/nands/andGate.v.orig
View File

@ -1,13 +0,0 @@
module andGate (
input wire A_i,
input wire B_i,
output wire Y_o
);
wire nand_out;
nand nand1 ( nand_out, A_i, B_i );
nand nand2 ( Y_o, nand_out, nand_out );
endmodule

16
iverilog/nand2tetris/nands/andGate.vcd
View File

@ -1,5 +1,5 @@
$date
Sun Dec 1 02:41:57 2024
Mon Dec 9 22:41:40 2024
$end
$version
Icarus Verilog
@ -8,14 +8,14 @@ $timescale
1s
$end
$scope module andGateTB $end
$var wire 1 ! Y $end
$var reg 1 " A $end
$var reg 1 # B $end
$var wire 1 ! Y_o $end
$var reg 1 " A_i $end
$var reg 1 # B_i $end
$scope module uut $end
$var wire 1 " A $end
$var wire 1 # B $end
$var wire 1 ! Y $end
$var wire 1 $ tempOut $end
$var wire 1 " A_i $end
$var wire 1 # B_i $end
$var wire 1 ! Y_o $end
$var wire 1 $ nand_out $end
$upscope $end
$upscope $end
$enddefinitions $end

26
iverilog/nand2tetris/nands/andGateTB.v
View File

@ -1,27 +1,27 @@
module andGateTB ();
reg A, B;
wire Y;
reg A_i, B_i;
wire Y_o;
andGate uut (
.A(A),
.B(B),
.Y(Y)
.A_i(A_i),
.B_i(B_i),
.Y_o(Y_o)
);
initial begin
$dumpfile("andGate.vcd");
$dumpvars;
A = 1'b0;
B = 1'b0;
A_i = 1'b0;
B_i = 1'b0;
#10;
A = 1'b0;
B = 1'b1;
A_i = 1'b0;
B_i = 1'b1;
#10;
A = 1'b1;
B = 1'b0;
A_i = 1'b1;
B_i = 1'b0;
#10;
A = 1'b1;
B = 1'b1;
A_i = 1'b1;
B_i = 1'b1;
#10;
$finish;
end

24
iverilog/nand2tetris/nands/notGate
View File

@ -7,26 +7,26 @@
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x5628fffa0b60 .scope module, "notGateTB" "notGateTB" 2 1;
S_0x56057d7feb60 .scope module, "notGateTB" "notGateTB" 2 1;
.timescale 0 0;
v0x5628fffafdd0_0 .var "A", 0 0;
v0x5628fffafe70_0 .net "B", 0 0, L_0x5628fffaff40; 1 drivers
S_0x5628fffa0cf0 .scope module, "uut" "notGate" 2 6, 3 1 0, S_0x5628fffa0b60;
v0x56057d80ddd0_0 .var "A_i", 0 0;
v0x56057d80de70_0 .net "B_o", 0 0, L_0x56057d80df40; 1 drivers
S_0x56057d7fecf0 .scope module, "uut" "notGate" 2 6, 3 1 0, S_0x56057d7feb60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /OUTPUT 1 "B";
L_0x5628fffaff40 .functor NAND 1, v0x5628fffafdd0_0, v0x5628fffafdd0_0, C4<1>, C4<1>;
v0x5628fff697f0_0 .net "A", 0 0, v0x5628fffafdd0_0; 1 drivers
v0x5628fff69c00_0 .net "B", 0 0, L_0x5628fffaff40; alias, 1 drivers
.scope S_0x5628fffa0b60;
.port_info 0 /INPUT 1 "A_i";
.port_info 1 /OUTPUT 1 "B_o";
L_0x56057d80df40 .functor NAND 1, v0x56057d80ddd0_0, v0x56057d80ddd0_0, C4<1>, C4<1>;
v0x56057d7c77f0_0 .net "A_i", 0 0, v0x56057d80ddd0_0; 1 drivers
v0x56057d7c7c00_0 .net "B_o", 0 0, L_0x56057d80df40; alias, 1 drivers
.scope S_0x56057d7feb60;
T_0 ;
%vpi_call 2 12 "$dumpfile", "notGate.vcd" {0 0 0};
%vpi_call 2 13 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5628fffafdd0_0, 0, 1;
%store/vec4 v0x56057d80ddd0_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5628fffafdd0_0, 0, 1;
%store/vec4 v0x56057d80ddd0_0, 0, 1;
%delay 10, 0;
%vpi_call 2 18 "$finish" {0 0 0};
%end;

6
iverilog/nand2tetris/nands/notGate.v
View File

@ -1,7 +1,7 @@
module notGate (
input A,
output B
input A_i,
output B_o
);
nand nand1 (B, A, A);
nand nand1 (B_o, A_i, A_i);
endmodule

10
iverilog/nand2tetris/nands/notGate.vcd
View File

@ -1,5 +1,5 @@
$date
Sun Dec 1 02:50:52 2024
Mon Dec 9 22:38:49 2024
$end
$version
Icarus Verilog
@ -8,11 +8,11 @@ $timescale
1s
$end
$scope module notGateTB $end
$var wire 1 ! B $end
$var reg 1 " A $end
$var wire 1 ! B_o $end
$var reg 1 " A_i $end
$scope module uut $end
$var wire 1 " A $end
$var wire 1 ! B $end
$var wire 1 " A_i $end
$var wire 1 ! B_o $end
$upscope $end
$upscope $end
$enddefinitions $end

32
iverilog/nand2tetris/nands/notGateTB.v
View File

@ -1,20 +1,20 @@
module notGateTB ();
module notGateTB;
reg A;
wire B;
reg A_i;
wire B_o;
notGate uut (
.A(A),
.B(B)
);
notGate uut (
.A_i(A_i),
.B_o(B_o)
);
initial begin
$dumpfile("notGate.vcd");
$dumpvars;
A = 1'b0;
#10;
A = 1'b1;
#10;
$finish;
end
initial begin
$dumpfile("notGate.vcd");
$dumpvars;
A_i = 1'b0;
#10;
A_i = 1'b1;
#10;
$finish;
end
endmodule

60
iverilog/nand2tetris/nands/orGate Normal file
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@ -0,0 +1,60 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55778f5946b0 .scope module, "orGateTB" "orGateTB" 2 1;
.timescale 0 0;
v0x55778f5a58d0_0 .var "A_i", 0 0;
v0x55778f5a5970_0 .var "B_i", 0 0;
v0x55778f5a5a40_0 .net "F_o", 0 0, L_0x55778f5a5cf0; 1 drivers
S_0x55778f594840 .scope module, "uut" "orGate" 2 5, 3 1 0, S_0x55778f5946b0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A_i";
.port_info 1 /INPUT 1 "B_i";
.port_info 2 /OUTPUT 1 "F_o";
L_0x55778f5a5b40 .functor NAND 1, v0x55778f5a58d0_0, v0x55778f5a58d0_0, C4<1>, C4<1>;
L_0x55778f5a5c30 .functor NAND 1, v0x55778f5a5970_0, v0x55778f5a5970_0, C4<1>, C4<1>;
L_0x55778f5a5cf0 .functor NAND 1, L_0x55778f5a5b40, L_0x55778f5a5c30, C4<1>, C4<1>;
v0x55778f581720_0 .net "A_i", 0 0, v0x55778f5a58d0_0; 1 drivers
v0x55778f5a5520_0 .net "B_i", 0 0, v0x55778f5a5970_0; 1 drivers
v0x55778f5a55e0_0 .net "F_o", 0 0, L_0x55778f5a5cf0; alias, 1 drivers
v0x55778f5a5680_0 .net "nand1_out", 0 0, L_0x55778f5a5b40; 1 drivers
v0x55778f5a5740_0 .net "nand2_out", 0 0, L_0x55778f5a5c30; 1 drivers
.scope S_0x55778f5946b0;
T_0 ;
%vpi_call 2 12 "$dumpfile", "orGate.vcd" {0 0 0};
%vpi_call 2 13 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55778f5a58d0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55778f5a5970_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55778f5a58d0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55778f5a5970_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55778f5a58d0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55778f5a5970_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55778f5a58d0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55778f5a5970_0, 0, 1;
%delay 10, 0;
%vpi_call 2 18 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"orGateTB.v";
"orGate.v";

43
iverilog/nand2tetris/nands/orGate.vcd Normal file
View File

@ -0,0 +1,43 @@
$date
Mon Dec 9 22:45:31 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module orGateTB $end
$var wire 1 ! F_o $end
$var reg 1 " A_i $end
$var reg 1 # B_i $end
$scope module uut $end
$var wire 1 " A_i $end
$var wire 1 # B_i $end
$var wire 1 ! F_o $end
$var wire 1 $ nand1_out $end
$var wire 1 % nand2_out $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1%
1$
0#
0"
0!
$end
#10
1!
0%
1#
#20
1%
0$
0#
1"
#30
0%
1#
#40

21
iverilog/nand2tetris/nands/orGateTB.v
View File

@ -0,0 +1,21 @@
module orGateTB();
reg A_i, B_i;
wire F_o;
orGate uut(
.A_i(A_i),
.B_i(B_i),
.F_o(F_o)
);
initial begin
$dumpfile("orGate.vcd");
$dumpvars;
A_i = 1'b0; B_i = 1'b0; #10;
A_i = 1'b0; B_i = 1'b1; #10;
A_i = 1'b1; B_i = 1'b0; #10;
A_i = 1'b1; B_i = 1'b1; #10;
$finish;
end
endmodule

62
iverilog/nand2tetris/nands/xorGate Normal file
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@ -0,0 +1,62 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55594b700b30 .scope module, "xorGateTB" "xorGateTB" 2 1;
.timescale 0 0;
v0x55594b712090_0 .var "A_i", 0 0;
v0x55594b712130_0 .var "B_i", 0 0;
v0x55594b712200_0 .net "F_o", 0 0, L_0x55594b712570; 1 drivers
S_0x55594b700cc0 .scope module, "uut" "xorGate" 2 5, 3 1 0, S_0x55594b700b30;
.timescale 0 0;
.port_info 0 /INPUT 1 "A_i";
.port_info 1 /INPUT 1 "B_i";
.port_info 2 /OUTPUT 1 "F_o";
L_0x55594b712300 .functor NAND 1, v0x55594b712090_0, v0x55594b712130_0, C4<1>, C4<1>;
L_0x55594b712440 .functor NAND 1, v0x55594b712090_0, L_0x55594b712300, C4<1>, C4<1>;
L_0x55594b712500 .functor NAND 1, v0x55594b712130_0, L_0x55594b712300, C4<1>, C4<1>;
L_0x55594b712570 .functor NAND 1, L_0x55594b712500, L_0x55594b712440, C4<1>, C4<1>;
v0x55594b6eda80_0 .net "A_i", 0 0, v0x55594b712090_0; 1 drivers
v0x55594b711c20_0 .net "B_i", 0 0, v0x55594b712130_0; 1 drivers
v0x55594b711ce0_0 .net "F_o", 0 0, L_0x55594b712570; alias, 1 drivers
v0x55594b711d80_0 .net "nand1_out", 0 0, L_0x55594b712300; 1 drivers
v0x55594b711e40_0 .net "nand2_out", 0 0, L_0x55594b712440; 1 drivers
v0x55594b711f50_0 .net "nand3_out", 0 0, L_0x55594b712500; 1 drivers
.scope S_0x55594b700b30;
T_0 ;
%vpi_call 2 12 "$dumpfile", "xorGate.vcd" {0 0 0};
%vpi_call 2 13 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55594b712090_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55594b712130_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55594b712090_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55594b712130_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55594b712090_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55594b712130_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55594b712090_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55594b712130_0, 0, 1;
%delay 10, 0;
%vpi_call 2 18 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"xorGateTB.v";
"xorGate.v";

14
iverilog/nand2tetris/nands/xorGate.v Normal file
View File

@ -0,0 +1,14 @@
module xorGate (
input A_i,
input B_i,
output F_o
);
wire nand1_out, nand2_out, nand3_out;
nand nand1(nand1_out, A_i, B_i);
nand nand2(nand2_out, A_i, nand1_out);
nand nand3(nand3_out, B_i, nand1_out);
nand nand4(F_o, nand3_out, nand2_out);
endmodule

48
iverilog/nand2tetris/nands/xorGate.vcd Normal file
View File

@ -0,0 +1,48 @@
$date
Mon Dec 9 22:56:38 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module xorGateTB $end
$var wire 1 ! F_o $end
$var reg 1 " A_i $end
$var reg 1 # B_i $end
$scope module uut $end
$var wire 1 " A_i $end
$var wire 1 # B_i $end
$var wire 1 ! F_o $end
$var wire 1 $ nand1_out $end
$var wire 1 % nand2_out $end
$var wire 1 & nand3_out $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1&
1%
1$
0#
0"
0!
$end
#10
1!
0&
1#
#20
1&
0%
0#
1"
#30
0!
1%
0$
1&
1#
#40

21
iverilog/nand2tetris/nands/xorGateTB.v Normal file
View File

@ -0,0 +1,21 @@
module xorGateTB();
reg A_i, B_i;
wire F_o;
xorGate uut(
.A_i(A_i),
.B_i(B_i),
.F_o(F_o)
);
initial begin
$dumpfile("xorGate.vcd");
$dumpvars;
A_i = 1'b0; B_i = 1'b0; #10;
A_i = 1'b0; B_i = 1'b1; #10;
A_i = 1'b1; B_i = 1'b0; #10;
A_i = 1'b1; B_i = 1'b1; #10;
$finish;
end
endmodule

26
iverilog/tobb/lab2/Fulladder.v
View File

@ -1,26 +0,0 @@
module Fulladder (
input A,
input B,
input Cin,
output S,
output Cout
);
wire AxB, AnB1, AnB2;
halfadder h1 (
.A(A),
.B(B),
.Sum(AxB),
.Carry(AnB2)
);
halfadder h2 (
.A(AxB),
.B(Cin),
.Sum(S),
.Carry(AnB1)
);
or o1 (.Y(Cout), .A(AnB1), .B(AnB2));
endmodule

168
iverilog/tobb/lab2/fdmp.vcd
View File

@ -1,84 +1,84 @@
$date
Tue Oct 8 14:05:40 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module fulladdertb $end
$var wire 1 ! w2 $end
$var wire 1 " w1 $end
$var reg 1 # r1 $end
$var reg 1 $ r2 $end
$var reg 1 % r3 $end
$scope module uut $end
$var wire 1 # A $end
$var wire 1 $ B $end
$var wire 1 % Cin $end
$var wire 1 ! Cout $end
$var wire 1 " S $end
$var wire 1 & AxB $end
$var wire 1 ' AnB2 $end
$var wire 1 ( AnB1 $end
$scope module h1 $end
$var wire 1 # A $end
$var wire 1 $ B $end
$var wire 1 ' C $end
$var wire 1 & S $end
$upscope $end
$scope module h2 $end
$var wire 1 & A $end
$var wire 1 % B $end
$var wire 1 ( C $end
$var wire 1 " S $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0(
0'
0&
0%
0$
0#
0"
0!
$end
#10
1"
1%
#20
1&
0%
1$
#30
1!
0"
1(
1%
#40
0!
1"
0(
0%
0$
1#
#50
1!
0"
1(
1%
#60
0(
0&
1'
0%
1$
#70
1"
1%
#80
$date
Sun Dec 8 20:51:56 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module fulladdertb $end
$var wire 1 ! w2 $end
$var wire 1 " w1 $end
$var reg 1 # r1 $end
$var reg 1 $ r2 $end
$var reg 1 % r3 $end
$scope module uut $end
$var wire 1 # A $end
$var wire 1 $ B $end
$var wire 1 % Cin $end
$var wire 1 ! Cout $end
$var wire 1 " S $end
$var wire 1 & AxB $end
$var wire 1 ' AnB2 $end
$var wire 1 ( AnB1 $end
$scope module h1 $end
$var wire 1 # A $end
$var wire 1 $ B $end
$var wire 1 ' C $end
$var wire 1 & S $end
$upscope $end
$scope module h2 $end
$var wire 1 & A $end
$var wire 1 % B $end
$var wire 1 ( C $end
$var wire 1 " S $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0(
0'
0&
0%
0$
0#
0"
0!
$end
#10
1"
1%
#20
1&
0%
1$
#30
1!
0"
1(
1%
#40
0!
1"
0(
0%
0$
1#
#50
1!
0"
1(
1%
#60
0(
0&
1'
0%
1$
#70
1"
1%
#80

254
iverilog/tobb/lab2/fulladder
View File

@ -1,127 +1,127 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x557fe3a27ae0 .scope module, "fulladdertb" "fulladdertb" 2 1;
.timescale 0 0;
v0x557fe3a3b940_0 .var "r1", 0 0;
v0x557fe3a3ba30_0 .var "r2", 0 0;
v0x557fe3a3bb40_0 .var "r3", 0 0;
v0x557fe3a3bc30_0 .net "w1", 0 0, L_0x557fe3a3bf40; 1 drivers
v0x557fe3a3bd20_0 .net "w2", 0 0, L_0x557fe3a3c1a0; 1 drivers
S_0x557fe3a27c70 .scope module, "uut" "fullAdder" 2 6, 3 1 0, S_0x557fe3a27ae0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Cin";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "Cout";
L_0x557fe3a3c1a0 .functor OR 1, L_0x557fe3a3c080, L_0x557fe3a3be80, C4<0>, C4<0>;
v0x557fe3a3b290_0 .net "A", 0 0, v0x557fe3a3b940_0; 1 drivers
v0x557fe3a3b350_0 .net "AnB1", 0 0, L_0x557fe3a3c080; 1 drivers
v0x557fe3a3b420_0 .net "AnB2", 0 0, L_0x557fe3a3be80; 1 drivers
v0x557fe3a3b520_0 .net "AxB", 0 0, L_0x557fe3a3be10; 1 drivers
v0x557fe3a3b610_0 .net "B", 0 0, v0x557fe3a3ba30_0; 1 drivers
v0x557fe3a3b700_0 .net "Cin", 0 0, v0x557fe3a3bb40_0; 1 drivers
v0x557fe3a3b7a0_0 .net "Cout", 0 0, L_0x557fe3a3c1a0; alias, 1 drivers
v0x557fe3a3b840_0 .net "S", 0 0, L_0x557fe3a3bf40; alias, 1 drivers
S_0x557fe3a22df0 .scope module, "h1" "halfadder" 3 9, 4 1 0, S_0x557fe3a27c70;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x557fe3a3be10 .functor XOR 1, v0x557fe3a3b940_0, v0x557fe3a3ba30_0, C4<0>, C4<0>;
L_0x557fe3a3be80 .functor AND 1, v0x557fe3a3b940_0, v0x557fe3a3ba30_0, C4<1>, C4<1>;
v0x557fe3a23070_0 .net "A", 0 0, v0x557fe3a3b940_0; alias, 1 drivers
v0x557fe3a3a970_0 .net "B", 0 0, v0x557fe3a3ba30_0; alias, 1 drivers
v0x557fe3a3aa30_0 .net "C", 0 0, L_0x557fe3a3be80; alias, 1 drivers
v0x557fe3a3ab00_0 .net "S", 0 0, L_0x557fe3a3be10; alias, 1 drivers
S_0x557fe3a3ac70 .scope module, "h2" "halfadder" 3 10, 4 1 0, S_0x557fe3a27c70;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x557fe3a3bf40 .functor XOR 1, L_0x557fe3a3be10, v0x557fe3a3bb40_0, C4<0>, C4<0>;
L_0x557fe3a3c080 .functor AND 1, L_0x557fe3a3be10, v0x557fe3a3bb40_0, C4<1>, C4<1>;
v0x557fe3a3aee0_0 .net "A", 0 0, L_0x557fe3a3be10; alias, 1 drivers
v0x557fe3a3afb0_0 .net "B", 0 0, v0x557fe3a3bb40_0; alias, 1 drivers
v0x557fe3a3b050_0 .net "C", 0 0, L_0x557fe3a3c080; alias, 1 drivers
v0x557fe3a3b120_0 .net "S", 0 0, L_0x557fe3a3bf40; alias, 1 drivers
.scope S_0x557fe3a27ae0;
T_0 ;
%vpi_call 2 15 "$dumpfile", "fdmp.vcd" {0 0 0};
%vpi_call 2 16 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0;
%vpi_call 2 25 "$display", v0x557fe3a3bc30_0 {0 0 0};
%vpi_call 2 26 "$display", v0x557fe3a3bd20_0 {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 5;
"N/A";
"<interactive>";
"fulladdertb.v";
"fulladder.v";
"halfadder.v";
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x56122b07fae0 .scope module, "fulladdertb" "fulladdertb" 2 1;
.timescale 0 0;
v0x56122b093940_0 .var "r1", 0 0;
v0x56122b093a30_0 .var "r2", 0 0;
v0x56122b093b40_0 .var "r3", 0 0;
v0x56122b093c30_0 .net "w1", 0 0, L_0x56122b093f40; 1 drivers
v0x56122b093d20_0 .net "w2", 0 0, L_0x56122b0941a0; 1 drivers
S_0x56122b07fc70 .scope module, "uut" "fulladder" 2 6, 3 1 0, S_0x56122b07fae0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Cin";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "Cout";
L_0x56122b0941a0 .functor OR 1, L_0x56122b094080, L_0x56122b093e80, C4<0>, C4<0>;
v0x56122b093290_0 .net "A", 0 0, v0x56122b093940_0; 1 drivers
v0x56122b093350_0 .net "AnB1", 0 0, L_0x56122b094080; 1 drivers
v0x56122b093420_0 .net "AnB2", 0 0, L_0x56122b093e80; 1 drivers
v0x56122b093520_0 .net "AxB", 0 0, L_0x56122b093e10; 1 drivers
v0x56122b093610_0 .net "B", 0 0, v0x56122b093a30_0; 1 drivers
v0x56122b093700_0 .net "Cin", 0 0, v0x56122b093b40_0; 1 drivers
v0x56122b0937a0_0 .net "Cout", 0 0, L_0x56122b0941a0; alias, 1 drivers
v0x56122b093840_0 .net "S", 0 0, L_0x56122b093f40; alias, 1 drivers
S_0x56122b07adf0 .scope module, "h1" "halfadder" 3 11, 4 1 0, S_0x56122b07fc70;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x56122b093e10 .functor XOR 1, v0x56122b093940_0, v0x56122b093a30_0, C4<0>, C4<0>;
L_0x56122b093e80 .functor AND 1, v0x56122b093940_0, v0x56122b093a30_0, C4<1>, C4<1>;
v0x56122b07b070_0 .net "A", 0 0, v0x56122b093940_0; alias, 1 drivers
v0x56122b092970_0 .net "B", 0 0, v0x56122b093a30_0; alias, 1 drivers
v0x56122b092a30_0 .net "C", 0 0, L_0x56122b093e80; alias, 1 drivers
v0x56122b092b00_0 .net "S", 0 0, L_0x56122b093e10; alias, 1 drivers
S_0x56122b092c70 .scope module, "h2" "halfadder" 3 13, 4 1 0, S_0x56122b07fc70;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x56122b093f40 .functor XOR 1, L_0x56122b093e10, v0x56122b093b40_0, C4<0>, C4<0>;
L_0x56122b094080 .functor AND 1, L_0x56122b093e10, v0x56122b093b40_0, C4<1>, C4<1>;
v0x56122b092ee0_0 .net "A", 0 0, L_0x56122b093e10; alias, 1 drivers
v0x56122b092fb0_0 .net "B", 0 0, v0x56122b093b40_0; alias, 1 drivers
v0x56122b093050_0 .net "C", 0 0, L_0x56122b094080; alias, 1 drivers
v0x56122b093120_0 .net "S", 0 0, L_0x56122b093f40; alias, 1 drivers
.scope S_0x56122b07fae0;
T_0 ;
%vpi_call 2 15 "$dumpfile", "fdmp.vcd" {0 0 0};
%vpi_call 2 16 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%vpi_call 2 25 "$display", v0x56122b093c30_0 {0 0 0};
%vpi_call 2 26 "$display", v0x56122b093d20_0 {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 5;
"N/A";
"<interactive>";
"fulladdertb.v";
"fulladder.v";
"halfadder.v";

16
iverilog/tobb/lab2/fulladder.v Normal file
View File

@ -0,0 +1,16 @@
module fulladder (
input A,
input B,
input Cin,
output S,
output Cout
);
wire AxB, AnB1, AnB2;
halfadder h1 (A,B,AxB,AnB2);
halfadder h2 (AxB,Cin,S,AnB1);
or o1 (Cout,AnB1,AnB2);
endmodule

2
iverilog/tobb/lab2/fulladdertb.v
View File

@ -3,7 +3,7 @@ module fulladdertb ();
reg r1, r2, r3;
wire w1, w2;
FullAdder uut(
fulladder uut(
.A(r1),
.B(r2),
.Cin(r3),