17 lines
285 B
Verilog
17 lines
285 B
Verilog
module dmuxGate(
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input A_i, S_i,
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output Y0_o, Y1_o
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);
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wire notS, nand2_out, nand4_out;
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nand nand1(notS, S_i, S_i);
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nand nand2(nand2_out, notS, A_i);
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nand nand3(Y0_o, nand2_out, nand2_out);
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nand nand4(nand4_out, S_i, A_i);
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nand nand5(Y1_o, nand4_out, nand4_out);
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endmodule
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