24 lines
363 B
Verilog
24 lines
363 B
Verilog
module dmuxGateTB();
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reg A_i, S_i;
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wire Y0_o, Y1_o;
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dmuxGate uut(
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.A_i(A_i),
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.S_i(S_i),
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.Y0_o(Y0_o),
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.Y1_o(Y1_o)
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);
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initial begin
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$dumpfile("dmuxGate.vcd");
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$dumpvars;
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A_i = 1'b0; S_i = 1'b0; #10;
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A_i = 1'b1; S_i = 1'b0; #10;
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A_i = 1'b0; S_i = 1'b1; #10;
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A_i = 1'b1; S_i = 1'b1; #10;
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$finish;
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end
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endmodule
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