27 lines
826 B
Verilog
27 lines
826 B
Verilog
module andSixTGateTB();
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reg [15:0] A_i;
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reg [15:0] B_i;
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wire [15:0] Y_o;
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andSixTGate uut(
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.A_i(A_i),
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.B_i(B_i),
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.Y_o(Y_o)
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);
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initial begin
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$dumpfile("andSixTGate.vcd");
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$dumpvars;
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A_i = 16'b0000_0000_0000_0000; B_i = 16'b0000_0000_0000_0000; #10;
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A_i = 16'b0000_0000_0000_0000; B_i = 16'b0000_0000_0000_0001; #10;
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A_i = 16'b0000_0000_0000_0001; B_i = 16'b0000_0000_0000_0001; #10;
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A_i = 16'b0000_0000_0100_0000; B_i = 16'b0000_0000_0000_0000; #10;
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A_i = 16'b0000_0000_0100_0000; B_i = 16'b0000_0000_0100_0000; #10;
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A_i = 16'b0000_0000_0000_0000; B_i = 16'b0000_0010_0000_0000; #10;
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A_i = 16'b0000_0010_0000_0000; B_i = 16'b0000_0010_0000_0000; #10;
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A_i = 16'b1111_1111_1111_1111; B_i = 16'b1111_1111_1111_1111; #10;
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$finish;
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end
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endmodule
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