28 lines
317 B
Plaintext
28 lines
317 B
Plaintext
$date
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Mon Dec 9 22:38:49 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module notGateTB $end
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$var wire 1 ! B_o $end
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$var reg 1 " A_i $end
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$scope module uut $end
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$var wire 1 " A_i $end
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$var wire 1 ! B_o $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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0"
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1!
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$end
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#10
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0!
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1"
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#20
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