310 lines
3.3 KiB
Plaintext
310 lines
3.3 KiB
Plaintext
$date
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Tue Dec 10 00:39:27 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module andSixTGateTB $end
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$var wire 16 ! Y_o [15:0] $end
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$var reg 16 " A_i [15:0] $end
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$var reg 16 # B_i [15:0] $end
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$scope module uut $end
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$var wire 16 $ A_i [15:0] $end
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$var wire 16 % B_i [15:0] $end
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$var wire 16 & Y_o [15:0] $end
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$scope module a0 $end
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$var wire 1 ' A_i $end
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$var wire 1 ( B_i $end
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$var wire 1 ) Y_o $end
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$var wire 1 * nand_out $end
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$upscope $end
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$scope module a1 $end
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$var wire 1 + A_i $end
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$var wire 1 , B_i $end
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$var wire 1 - Y_o $end
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$var wire 1 . nand_out $end
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$upscope $end
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$scope module a10 $end
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$var wire 1 / A_i $end
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$var wire 1 0 B_i $end
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$var wire 1 1 Y_o $end
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$var wire 1 2 nand_out $end
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$upscope $end
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$scope module a11 $end
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$var wire 1 3 A_i $end
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$var wire 1 4 B_i $end
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$var wire 1 5 Y_o $end
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$var wire 1 6 nand_out $end
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$upscope $end
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$scope module a12 $end
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$var wire 1 7 A_i $end
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$var wire 1 8 B_i $end
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$var wire 1 9 Y_o $end
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$var wire 1 : nand_out $end
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$upscope $end
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$scope module a13 $end
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$var wire 1 ; A_i $end
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$var wire 1 < B_i $end
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$var wire 1 = Y_o $end
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$var wire 1 > nand_out $end
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$upscope $end
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$scope module a14 $end
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$var wire 1 ? A_i $end
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$var wire 1 @ B_i $end
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$var wire 1 A Y_o $end
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$var wire 1 B nand_out $end
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$upscope $end
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$scope module a15 $end
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$var wire 1 C A_i $end
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$var wire 1 D B_i $end
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$var wire 1 E Y_o $end
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$var wire 1 F nand_out $end
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$upscope $end
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$scope module a2 $end
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$var wire 1 G A_i $end
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$var wire 1 H B_i $end
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$var wire 1 I Y_o $end
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$var wire 1 J nand_out $end
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$upscope $end
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$scope module a3 $end
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$var wire 1 K A_i $end
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$var wire 1 L B_i $end
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$var wire 1 M Y_o $end
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$var wire 1 N nand_out $end
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$upscope $end
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$scope module a4 $end
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$var wire 1 O A_i $end
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$var wire 1 P B_i $end
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$var wire 1 Q Y_o $end
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$var wire 1 R nand_out $end
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$upscope $end
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$scope module a5 $end
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$var wire 1 S A_i $end
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$var wire 1 T B_i $end
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$var wire 1 U Y_o $end
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$var wire 1 V nand_out $end
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$upscope $end
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$scope module a6 $end
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$var wire 1 W A_i $end
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$var wire 1 X B_i $end
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$var wire 1 Y Y_o $end
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$var wire 1 Z nand_out $end
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$upscope $end
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$scope module a7 $end
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$var wire 1 [ A_i $end
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$var wire 1 \ B_i $end
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$var wire 1 ] Y_o $end
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$var wire 1 ^ nand_out $end
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$upscope $end
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$scope module a8 $end
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$var wire 1 _ A_i $end
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$var wire 1 ` B_i $end
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$var wire 1 a Y_o $end
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$var wire 1 b nand_out $end
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$upscope $end
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$scope module a9 $end
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$var wire 1 c A_i $end
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$var wire 1 d B_i $end
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$var wire 1 e Y_o $end
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$var wire 1 f nand_out $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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1f
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0e
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0d
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0c
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1b
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0a
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0`
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0_
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1^
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0]
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0\
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0[
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1Z
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0Y
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0X
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0W
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1V
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0U
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0T
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0S
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1R
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0Q
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0P
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0O
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1N
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0M
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0L
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0K
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1J
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0I
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0H
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0G
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1F
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0E
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0D
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0C
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1B
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0A
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0@
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0?
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1>
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0=
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0<
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0;
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1:
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09
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08
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07
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16
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05
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04
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03
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12
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01
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00
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0/
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1.
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0-
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0,
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0+
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1*
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0)
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0(
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0'
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b0 &
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b0 %
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b0 $
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b0 #
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b0 "
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b0 !
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$end
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#10
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1(
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b1 #
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b1 %
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#20
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b1 !
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b1 &
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1)
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0*
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1'
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b1 "
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b1 $
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#30
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b0 !
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b0 &
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0)
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1*
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0(
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0'
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1W
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b0 #
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b0 %
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b1000000 "
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b1000000 $
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#40
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b1000000 !
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b1000000 &
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1Y
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0Z
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1X
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b1000000 #
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b1000000 %
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#50
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b0 !
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b0 &
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0Y
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1Z
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0X
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1d
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0W
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b1000000000 #
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b1000000000 %
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b0 "
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b0 $
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#60
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b1000000000 !
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b1000000000 &
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1e
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0f
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1c
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b1000000000 "
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b1000000000 $
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#70
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1)
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1-
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1I
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1M
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1Q
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1U
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1Y
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1]
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1a
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11
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15
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19
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1=
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1A
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b1111111111111111 !
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b1111111111111111 &
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1E
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0*
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0.
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0J
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0N
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0R
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0V
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0Z
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0^
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0b
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02
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06
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0:
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0>
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0B
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0F
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1(
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1,
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1H
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1L
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1P
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1T
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1X
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1\
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1`
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10
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14
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18
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1<
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1@
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1D
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1'
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1+
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1G
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1K
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1O
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1S
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1W
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1[
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1_
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1/
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13
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17
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1;
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1?
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1C
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b1111111111111111 #
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b1111111111111111 %
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b1111111111111111 "
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b1111111111111111 $
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#80
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