22 lines
333 B
Verilog
22 lines
333 B
Verilog
module xorGateTB();
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reg A_i, B_i;
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wire F_o;
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xorGate uut(
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.A_i(A_i),
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.B_i(B_i),
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.F_o(F_o)
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);
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initial begin
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$dumpfile("xorGate.vcd");
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$dumpvars;
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A_i = 1'b0; B_i = 1'b0; #10;
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A_i = 1'b0; B_i = 1'b1; #10;
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A_i = 1'b1; B_i = 1'b0; #10;
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A_i = 1'b1; B_i = 1'b1; #10;
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$finish;
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end
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endmodule
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