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19 Commits
4ca5ab1995 ... main

Author SHA1 Message Date
k0rrluna
ee84dbe799 lab7 2025-02-03 22:46:58 +03:00
k0rrluna
1d5ff13ca1 labs 2025-02-01 06:35:32 +03:00
k0rrluna
57c2935e1c lab7 2025-01-30 07:23:51 +03:00
k0rrluna
85dbb22740 lab6 2025-01-30 06:50:00 +03:00
k0rrluna
1b0958962c lab5 2025-01-26 06:05:52 +03:00
k0rrluna
7605bbf473 lab5 2025-01-25 08:00:40 +03:00
k0rrluna
c5e6bb95a0 lab4 2025-01-25 03:15:10 +03:00
k0rrluna
0f359fa8a4 f# fix 2025-01-23 07:58:44 +03:00
k0rrluna
8003e7f253 fpga 2025-01-23 05:25:40 +03:00
k0rrluna
e91a8471ac final fpga 2025-01-21 05:12:57 +03:00
k0rrluna
6b83c0f2e7 merge 2025-01-21 05:12:02 +03:00
k0rrluna
8e613a767e tangFpga 2025-01-20 18:23:08 +03:00
k0rrluna
15916a2c53 bttnTB 2025-01-20 15:16:37 +03:00
k0rrluna
a007343feb fpga added 2025-01-19 14:01:08 +03:00
k0rrluna
4b2009e207 selector&bcd 2025-01-15 22:21:50 +03:00
k0rrluna
3d71f7e69f fpga 2025-01-12 07:23:34 +03:00
k0rrluna
39d8168cc0 some random things 2025-01-08 01:05:46 +03:00
k0rrluna
ceede4abc3 Merge branch 'main' of ssh://ssh.ras-pi.tr/kaltinsoy/verilog 2025-01-03 05:09:40 +03:00
k0rrluna
44a86fb2c0 selector 2025-01-03 05:09:20 +03:00
80 changed files with 12467 additions and 2 deletions
Expand all files Collapse all files

25
gowin/bttn/bttn.gprj Normal file
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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
<FileList>
<File path="src/ALU.v" type="file.verilog" enable="1"/>
<File path="src/BinaryToBCD.v" type="file.verilog" enable="1"/>
<File path="src/addition.v" type="file.verilog" enable="1"/>
<File path="src/arithmeticUnit.v" type="file.verilog" enable="1"/>
<File path="src/dabble.v" type="file.verilog" enable="1"/>
<File path="src/fulladder.v" type="file.verilog" enable="1"/>
<File path="src/fullsubtraction.v" type="file.verilog" enable="1"/>
<File path="src/halfadder.v" type="file.verilog" enable="1"/>
<File path="src/halfsubtraction.v" type="file.verilog" enable="1"/>
<File path="src/logicUnit.v" type="file.verilog" enable="1"/>
<File path="src/multiplier.v" type="file.verilog" enable="1"/>
<File path="src/opCode.v" type="file.verilog" enable="1"/>
<File path="src/selector.v" type="file.verilog" enable="1"/>
<File path="src/subtraction.v" type="file.verilog" enable="1"/>
<File path="src/top.v" type="file.verilog" enable="1"/>
<File path="src/top.cst" type="file.cst" enable="1"/>
</FileList>
</Project>

27
gowin/bttn/bttn.gprj.user Normal file
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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE ProjectUserData>
<UserConfig>
<Version>1.0</Version>
<FlowState>
<Process ID="Synthesis" State="2"/>
<Process ID="Pnr" State="2"/>
<Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/>
<Process ID="Gvio" State="2"/>
<Process ID="Place" State="2"/>
</FlowState>
<ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/bttn.vg"/>
<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/bttn.fs"/>
<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/bttn.pin.html"/>
<ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/bttn.db"/>
<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/bttn.power.html"/>
<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/bttn.rpt.html"/>
<ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/bttn.timing_paths"/>
<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/bttn.tr.html"/>
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/bttn_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/bttn_syn_rsc.xml"/>
</ResultFileList>
<Ui>000000ff00000001fd00000002000000000000018e0000025dfc0200000001fc000000370000025d0000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000078000000145fc0100000001fc0000000000000780000000a100fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100ffffff000005ee0000025d00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000000000280043006f00720065002e0054006f006f006c006200610072002e00500072006f00630065007300730100000245ffffffff0000000000000000</Ui>
<FpUi></FpUi>
</UserConfig>

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gowin/bttn/src/ALU.v Normal file
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module ALU (
input [3:0] A, B,
input CarryIN,
input [2:0] opCodeA,
output [11:0] bcd,
output CarryOUT, overflow
);
// Supports: ADD[0], SUB[1], MULT[2], AND[4], OR[5], XOR[6]
wire [7:0] opCode8;
wire [3:0] add_Y, sub_Y;
wire [3:0] resultA, resultO, resultX, lUOutput1;
wire [3:0] aUtemp1, aUtemp2, lUOutput2;
wire [3:0] wireY, wireLA;
wire [7:0] opwireM, wireM, Y;
opCode opCd (.A(opCodeA), .opCode(opCode8));
arithmeticUnit aU(.opCode(opCode8[1:0]), .A(A), .B(B), .CarryIN(CarryIN), .add_Y(add_Y), .sub_Y(sub_Y), .CarryOUT(CarryOUT), .overflow(overflow));
logicUnit lU (.opCode(opCode8[6:4]), .A(A), .B(B), .resultA(resultA), .resultO(resultO), .resultX(resultX));
multiplier mU (.A(A), .B(B), .Y(opwireM));
or o01 (lUOutput1[0], resultA[0], resultO[0]);
or o02 (lUOutput1[1], resultA[1], resultO[1]);
or o03 (lUOutput1[2], resultA[2], resultO[2]);
or o04 (lUOutput1[3], resultA[3], resultO[3]);
or o11 (lUOutput2[0], lUOutput1[0], resultX[0]);
or o12 (lUOutput2[1], lUOutput1[1], resultX[1]);
or o13 (lUOutput2[2], lUOutput1[2], resultX[2]);
or o14 (lUOutput2[3], lUOutput1[3], resultX[3]);
and a01 (aUtemp1[0], opCode8[0], add_Y[0]);
and a02 (aUtemp1[1], opCode8[0], add_Y[1]);
and a03 (aUtemp1[2], opCode8[0], add_Y[2]);
and a04 (aUtemp1[3], opCode8[0], add_Y[3]);
and a11 (aUtemp2[0], opCode8[1], sub_Y[0]);
and a12 (aUtemp2[1], opCode8[1], sub_Y[1]);
and a13 (aUtemp2[2], opCode8[1], sub_Y[2]);
and a14 (aUtemp2[3], opCode8[1], sub_Y[3]);
and a21 (wireM[0], opCode8[2], opwireM[0]);
and a22 (wireM[1], opCode8[2], opwireM[1]);
and a23 (wireM[2], opCode8[2], opwireM[2]);
and a24 (wireM[3], opCode8[2], opwireM[3]);
and a25 (wireM[4], opCode8[2], opwireM[4]);
and a26 (wireM[5], opCode8[2], opwireM[5]);
and a27 (wireM[6], opCode8[2], opwireM[6]);
and a28 (wireM[7], opCode8[2], opwireM[7]);
or o21 (wireY[0], aUtemp1[0], aUtemp2[0]);
or o22 (wireY[1], aUtemp1[1], aUtemp2[1]);
or o23 (wireY[2], aUtemp1[2], aUtemp2[2]);
or o24 (wireY[3], aUtemp1[3], aUtemp2[3]);
or o1 (wireLA[0], lUOutput2[0], wireY[0]);
or o2 (wireLA[1], lUOutput2[1], wireY[1]);
or o3 (wireLA[2], lUOutput2[2], wireY[2]);
or o4 (wireLA[3], lUOutput2[3], wireY[3]);
or o31 (Y[0], wireLA[0], wireM[0]);
or o32 (Y[1], wireLA[1], wireM[1]);
or o33 (Y[2], wireLA[2], wireM[2]);
or o34 (Y[3], wireLA[3], wireM[3]);
or o35 (Y[4], 1'b0, wireM[4]);
or o36 (Y[5], 1'b0, wireM[5]);
or o37 (Y[6], 1'b0, wireM[6]);
or o38 (Y[7], 1'b0, wireM[7]);
BinaryToBCD btod1(.binary(Y), .bcd(bcd)); // WIRE Y BINARY!!!!
endmodule

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module BinaryToBCD (
input [7:0] binary,
output [11:0] bcd
);
wire empty1, empty2;
wire [3:0] dab1, dab2, dab3, dab4, dab5;
and a111 (empty1, 1'b0, 1'b0);
and a000 (empty2, 1'b0, 1'b0);
and a222 (bcd[11], 1'b0, 1'b0);
and a223 (bcd[10], 1'b0, 1'b0);
dabble d1t (.A((empty1)),
.B(binary[7]),
.C(binary[6]),
.D(binary[5]),
.X(dab1[0]),
.Y(dab1[1]),
.Z(dab1[2]),
.E(dab1[3]));
dabble d2u (.A((dab1[1])),
.B(dab1[2]),
.C(dab1[3]),
.D(binary[4]),
.X(dab2[0]),
.Y(dab2[1]),
.Z(dab2[2]),
.E(dab2[3]));
dabble d3v (.A((dab2[1])),
.B(dab2[2]),
.C(dab2[3]),
.D(binary[3]),
.X(dab3[0]),
.Y(dab3[1]),
.Z(dab3[2]),
.E(dab3[3]));
dabble d4w (.A((empty2)),
.B(dab1[0]),
.C(dab2[0]),
.D(dab3[0]),
.X(bcd[9]),
.Y(dab4[1]),
.Z(dab4[2]),
.E(dab4[3]));
dabble d5x (.A((dab3[1])),
.B(dab3[2]),
.C(dab3[3]),
.D(binary[2]),
.X(dab5[0]),
.Y(dab5[1]),
.Z(dab5[2]),
.E(dab5[3]));
dabble d6y (.A((dab4[1])),
.B(dab4[2]),
.C(dab4[3]),
.D(dab5[0]),
.X(bcd[8]),
.Y(bcd[7]),
.Z(bcd[6]),
.E(bcd[5]));
dabble d7z (.A((dab5[1])),
.B(dab5[2]),
.C(dab5[3]),
.D(binary[1]),
.X(bcd[4]),
.Y(bcd[3]),
.Z(bcd[2]),
.E(bcd[1]));
or o1 (bcd[0], binary[0], 1'b0);
endmodule

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gowin/bttn/src/addition.v Normal file
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module addition (
input [3:0] A, B,
input CarryIN,
output [3:0] Y,
output CarryOUT,
output overflow
);
wire [2:0] Carry4;
fulladder f0(.A(A[0]), .B(B[0]), .Carry(CarryIN), .Sum(Y[0]), .CarryO(Carry4[0]));
fulladder f1(.A(A[1]), .B(B[1]), .Carry(Carry4[0]), .Sum(Y[1]), .CarryO(Carry4[1]));
fulladder f2(.A(A[2]), .B(B[2]), .Carry(Carry4[1]), .Sum(Y[2]), .CarryO(Carry4[2]));
fulladder f3(.A(A[3]), .B(B[3]), .Carry(Carry4[2]), .Sum(Y[3]), .CarryO(CarryOUT));
//overflowDetect od1 (.opCode(2'b01), .A(A), .B(B), .Y(Y), .CarryOUT(CarryOUT), .overflowDetect(overflow)); (KULLANILMAYACAK!!!!)
xor ov1 (overflow, Carry4[2], CarryOUT);
endmodule

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gowin/bttn/src/arithmeticUnit.v Normal file
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module arithmeticUnit (
input [1:0] opCode,
input [3:0] A, B,
input CarryIN,
output [3:0] add_Y, sub_Y,
output CarryOUT,
output overflow
);
wire [3:0] addY, subY;
wire CarryOUTADD, CarryOUTSUB, tempCAdd, tempCSub, tempoverflow;
addition a1(.A(A), .B(B), .CarryIN(CarryIN), .Y(addY), .CarryOUT(CarryOUTADD), .overflow(tempoverflow));
subtraction s1(.A(A), .B(B), .BorrowIN(CarryIN), .Y(subY), .BorrowOUT(CarryOUTSUB));
and add1 (add_Y[0], opCode[0], addY[0]);
and add2 (add_Y[1], opCode[0], addY[1]);
and add3 (add_Y[2], opCode[0], addY[2]);
and add4 (add_Y[3], opCode[0], addY[3]);
and sub1 (sub_Y[0], opCode[1], subY[0]);
and sub2 (sub_Y[1], opCode[1], subY[1]);
and sub3 (sub_Y[2], opCode[1], subY[2]);
and sub4 (sub_Y[3], opCode[1], subY[3]);
// or or1 (CarryOUT, CarryOUTADD, CarryOUTSUB); (OLD!!!)
and and10 (tempCSub, CarryOUTSUB, opCode[1]);
and and11 (tempCAdd, CarryOUTADD, opCode[0]);
or or4 (CarryOUT, tempCAdd, tempCSub);
and add12 (overflow, opCode[0], tempoverflow);
endmodule

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gowin/bttn/src/dabble.v Normal file
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module dabble (
input A, B, C, D,
output X, Y, Z, E
);
wire xor1, nor1, xor2, nor2, nor3, or1;
xor xo1 (xor1, A, D);
nor no1 (nor1, A, B);
xor xo2 (xor2, A, C);
nor no2 (nor2, xor1, xor2);
nor no3 (nor3, nor2, nor1);
buf bu1 (X, nor3);
or o1 (or1, xor1, nor1);
nor no4 (Y, or1, C);
and an1 (Z, or1, xor2);
xor xo3 (E, nor3, D);
endmodule

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gowin/bttn/src/fulladder.v Normal file
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module fulladder (
input A, B, Carry,
output Sum, CarryO
);
wire xor1, and1, and2;
halfadder h1(.A(A), .B(B), .Sum(xor1), .Carry(and1));
halfadder h2 (.A(xor1), .B(Carry), .Sum(Sum), .Carry(and2));
or o1 (CarryO, and1, and2);
endmodule

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gowin/bttn/src/fullsubtraction.v Normal file
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module fullsubtraction (
input A, B, BorrowIN,
output Difference, BorrowOut
);
wire tempD, tempB1, tempB2;
halfsubtraction hf1(.A(A), .B(B), .Difference(tempD), .Borrow(tempB1));
halfsubtraction hf2(.A(tempD), .B(BorrowIN), .Difference(Difference), .Borrow(tempB2));
or o1 (BorrowOut, tempB1, tempB2);
endmodule

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gowin/bttn/src/halfadder.v Normal file
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module halfadder (
input A, B,
output Sum, Carry
);
and a1 (Carry, A, B);
xor xo1 (Sum, A, B);
endmodule

12
gowin/bttn/src/halfsubtraction.v Normal file
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module halfsubtraction (
input A, B,
output Difference, Borrow
);
wire notA;
xor xo1 (Difference, A, B);
not a1 (notA, A);
and an1 (Borrow, notA, B);
endmodule

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gowin/bttn/src/logicUnit.v Normal file
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module logicUnit (
input [2:0] opCode,
input [3:0] A, B,
output [3:0] resultA, resultO, resultX
);
wire [3:0] and1, or1, xor1;
and a01 (and1[0], A[0], B[0]);
and a02 (and1[1], A[1], B[1]);
and a03 (and1[2], A[2], B[2]);
and a04 (and1[3], A[3], B[3]);
or o01 (or1[0], A[0], B[0]);
or o02 (or1[1], A[1], B[1]);
or o03 (or1[2], A[2], B[2]);
or o04 (or1[3], A[3], B[3]);
xor xor01 (xor1[0], A[0], B[0]);
xor xor02 (xor1[1], A[1], B[1]);
xor xor03 (xor1[2], A[2], B[2]);
xor xor04 (xor1[3], A[3], B[3]);
and a_o1 (resultA[0], opCode[0], and1[0]);
and a_o2 (resultA[1], opCode[0], and1[1]);
and a_o3 (resultA[2], opCode[0], and1[2]);
and a_o4 (resultA[3], opCode[0], and1[3]);
and o_o1 (resultO[0], opCode[1], or1[0]);
and o_o2 (resultO[1], opCode[1], or1[1]);
and o_o3 (resultO[2], opCode[1], or1[2]);
and o_o4 (resultO[3], opCode[1], or1[3]);
and x_o1 (resultX[0], opCode[2], xor1[0]);
and x_o2 (resultX[1], opCode[2], xor1[1]);
and x_o3 (resultX[2], opCode[2], xor1[2]);
and x_o4 (resultX[3], opCode[2], xor1[3]);
endmodule

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gowin/bttn/src/multiplier.v Normal file
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module multiplier (
input [3:0] A, B,
output [7:0] Y
);
wire [3:0] b0, a0, a1, a2;
wire [4:0] S0, S1, S2;
wire carry0, carry1, carry2;
wire overflow0, overflow1, overflow2;
// Partial product generation
and (Y[0], A[0], B[0]); // LSB of the result
// Generate partial products for B[0] and B[1]
and ab00 (b0[0], A[1], B[0]);
and ab01 (b0[1], A[2], B[0]);
and ab02 (b0[2], A[3], B[0]);
not ab03 (b0[3], 1'b1); // Initialize b0[3] to 0
and aa00 (a0[0], A[0], B[1]);
and aa01 (a0[1], A[1], B[1]);
and aa02 (a0[2], A[2], B[1]);
and aa03 (a0[3], A[3], B[1]);
// First addition
addition add0 (
.A(a0),
.B(b0),
.CarryIN(1'b0),
.Y(S0[3:0]),
.CarryOUT(S0[4]),
.overflow(overflow0)
);
// Generate partial products for B[2]
and aa10 (a1[0], A[0], B[2]);
and aa11 (a1[1], A[1], B[2]);
and aa12 (a1[2], A[2], B[2]);
and aa13 (a1[3], A[3], B[2]);
// Second addition
addition add1 (
.A(a1),
.B(S0[4:1]),
.CarryIN(1'b0),
.Y(S1[3:0]),
.CarryOUT(S1[4]),
.overflow(overflow1)
);
// Generate partial products for B[3]
and aa20 (a2[0], A[0], B[3]);
and aa21 (a2[1], A[1], B[3]);
and aa22 (a2[2], A[2], B[3]);
and aa23 (a2[3], A[3], B[3]);
// Third addition
addition add2 (
.A(a2),
.B(S1[4:1]),
.CarryIN(1'b0),
.Y(S2[3:0]),
.CarryOUT(S2[4]),
.overflow(overflow2)
);
// Combine results into the final output Y
or o01 (Y[1], S0[0], 1'b0);
or o02 (Y[2], S1[0], 1'b0);
or o03 (Y[3], S2[0], 1'b0);
or o04 (Y[4], S2[1], 1'b0);
or o05 (Y[5], S2[2], 1'b0);
or o06 (Y[6], S2[3], 1'b0);
or o07 (Y[7], S2[4], 1'b0);
endmodule

25
gowin/bttn/src/opCode.v Normal file
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module opCode (
input [2:0] A,
output [7:0] opCode
);
wire and1, and2, and3, and4, notA, notB, notC;
not n1(notA, A[2]);
not n2(notB, A[1]);
not n3(notC, A[0]);
and a01(and1, A[2], A[1]);
and a02(and2, notA, A[1]);
and a03(and3, A[2], notB);
and a04(and4, notA, notB);
and a1(opCode[0], and4, notC);
and a2(opCode[1], and4, A[0]);
and a3(opCode[2], and2, notC);
and a4(opCode[3], and2, A[0]);
and a5(opCode[4], and3, notC);
and a6(opCode[5], and3, A[0]);
and a7(opCode[6], and1, notC);
and a8(opCode[7], and1, A[0]);
endmodule

20
gowin/bttn/src/selector.v Normal file
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module selector (
input [3:0] A,
input [3:0] B,
input [2:0] opCodeA,
input [1:0] select,
input [11:0] ALUY,
output reg [11:0] Y
);
always @(*) begin
case (select)
2'b00: Y = {8'b00000000, A}; // Zero-extend A to 8 bits
2'b01: Y = {8'b00000000, B}; // Zero-extend B to 8 bits
2'b10: Y = {9'b000000000, opCodeA}; // Zero-extend opCodeA to 8 bits
2'b11: Y = ALUY; // Directly assign ALUY
default: Y = ALUY; // Default case for safety
endcase
end
endmodule

16
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module subtraction (
input [3:0] A, B,
input BorrowIN,
output [3:0] Y,
output BorrowOUT //Overflow signal'ini yani negatif gonderecek
);
wire [3:0] tempB;
// Full Subtraction logic for each bit (borrow-in for each subsequent bit)
fullsubtraction f0 (.A(A[0]), .B(B[0]), .BorrowIN(BorrowIN), .Difference(Y[0]), .BorrowOut(tempB[0]));
fullsubtraction f1 (.A(A[1]), .B(B[1]), .BorrowIN(tempB[0]), .Difference(Y[1]), .BorrowOut(tempB[1]));
fullsubtraction f2 (.A(A[2]), .B(B[2]), .BorrowIN(tempB[1]), .Difference(Y[2]), .BorrowOut(tempB[2]));
fullsubtraction f3 (.A(A[3]), .B(B[3]), .BorrowIN(tempB[2]), .Difference(Y[3]), .BorrowOut(BorrowOUT));
endmodule

65
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//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Physical Constraints file
//Tool Version: V1.9.9.03 Education (64-bit)
//Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18
//Device Version: C
//Created Time: Mon 01 20 17:48:00 2025
IO_LOC "Y[11]" B12;
IO_PORT "Y[11]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[10]" B13;
IO_PORT "Y[10]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[9]" B14;
IO_PORT "Y[9]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[8]" D14;
IO_PORT "Y[8]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[7]" J14;
IO_PORT "Y[7]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[6]" M14;
IO_PORT "Y[6]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[5]" T12;
IO_PORT "Y[5]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[4]" T11;
IO_PORT "Y[4]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[3]" P9;
IO_PORT "Y[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[2]" P8;
IO_PORT "Y[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[1]" T7;
IO_PORT "Y[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[0]" P6;
IO_PORT "Y[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[1]" L14;
IO_PORT "leds[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[0]" L16;
IO_PORT "leds[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Cin" E9;
IO_PORT "Cin" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "select[1]" A14;
IO_PORT "select[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "select[0]" A15;
IO_PORT "select[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[2]" E8;
IO_PORT "opCodeA[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[1]" T4;
IO_PORT "opCodeA[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[0]" T5;
IO_PORT "opCodeA[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "B[3]" N8;
IO_PORT "B[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[2]" N7;
IO_PORT "B[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[1]" D11;
IO_PORT "B[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[0]" B11;
IO_PORT "B[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[3]" L9;
IO_PORT "A[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[2]" E15;
IO_PORT "A[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[1]" N6;
IO_PORT "A[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[0]" A11;
IO_PORT "A[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;

19
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module top (
input [3:0] A, B,
input [2:0] opCodeA,
input [1:0] select,
input Cin,
output [1:0] leds,
output [11:0] Y
);
wire wire1, wire2;
wire [11:0] selectY;
ALU a1(.A(A), .B(B), .opCodeA(opCodeA), .CarryIN(Cin), .bcd(selectY), .CarryOUT(wire2), .overflow(wire1)); //ALU module
selector s1(.A(A), .B(B), .opCodeA(opCodeA), .select(select), .ALUY(selectY), .Y(Y)); // selector for 7 segment
assign leds[0] = ~wire1; //overflow led
assign leds[1] = ~wire2; //CarryOut/BorrowOut led
endmodule

23
gowin/bttn/src/topTB.v Normal file
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module topTB();
reg [3:0] A,B;
reg [2:0] opCodeA;
reg [1:0] select;
wire [11:0] Y;
top uut (
.A(A),
.B(B),
.opCodeA(opCodeA),
.select(select),
.Y(Y)
);
initial begin
$dumpfile("top.vcd");
$dumpvars;
A = 4'b0001; B = 4'b0110; opCodeA = 3'b000; select = 2'b01; #5;
$finish;
end
endmodule

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module bttn (
input [3:0] bttns,
output [3:0] pmod
);
assign bttns = pmod;
endmodule

291
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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55ec90657360 .scope module, "bib3TB" "bib3TB" 2 1;
.timescale 0 0;
v0x55ec9066dea0_0 .var "A", 8 0;
v0x55ec9066df60_0 .net "Y", 3 0, v0x55ec9066dd60_0; 1 drivers
S_0x55ec906574f0 .scope module, "uut" "bib3" 2 6, 3 1 0, S_0x55ec90657360;
.timescale 0 0;
.port_info 0 /INPUT 9 "buyruk";
.port_info 1 /OUTPUT 4 "sonuc";
v0x55ec90618c00_0 .var/i "a", 31 0;
v0x55ec9066d8d0_0 .var/i "b", 31 0;
v0x55ec9066d9b0_0 .net "buyruk", 8 0, v0x55ec9066dea0_0; 1 drivers
v0x55ec9066da70_0 .var/i "c", 31 0;
v0x55ec9066db50_0 .var/i "count", 31 0;
v0x55ec9066dc80_0 .var/i "i", 31 0;
v0x55ec9066dd60_0 .var "sonuc", 3 0;
E_0x55ec9064fc40 .event edge, v0x55ec9066d9b0_0;
.scope S_0x55ec906574f0;
T_0 ;
%wait E_0x55ec9064fc40;
%load/vec4 v0x55ec9066d9b0_0;
%parti/s 3, 6, 4;
%dup/vec4;
%pushi/vec4 0, 0, 3;
%cmp/u;
%jmp/1 T_0.1, 6;
%dup/vec4;
%pushi/vec4 1, 0, 3;
%cmp/u;
%jmp/1 T_0.2, 6;
%dup/vec4;
%pushi/vec4 2, 0, 3;
%cmp/u;
%jmp/1 T_0.3, 6;
%dup/vec4;
%pushi/vec4 3, 0, 3;
%cmp/u;
%jmp/1 T_0.4, 6;
%dup/vec4;
%pushi/vec4 4, 0, 3;
%cmp/u;
%jmp/1 T_0.5, 6;
%dup/vec4;
%pushi/vec4 5, 0, 3;
%cmp/u;
%jmp/1 T_0.6, 6;
%dup/vec4;
%pushi/vec4 6, 0, 3;
%cmp/u;
%jmp/1 T_0.7, 6;
%dup/vec4;
%pushi/vec4 7, 0, 3;
%cmp/u;
%jmp/1 T_0.8, 6;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
%jmp T_0.9;
T_0.1 ;
%load/vec4 v0x55ec9066d9b0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55ec9066d9b0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%add;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
%jmp T_0.9;
T_0.2 ;
%load/vec4 v0x55ec9066d9b0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55ec9066d9b0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%sub;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
%jmp T_0.9;
T_0.3 ;
%load/vec4 v0x55ec9066d9b0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55ec9066d9b0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%and;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
%jmp T_0.9;
T_0.4 ;
%load/vec4 v0x55ec9066d9b0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55ec9066d9b0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%or;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
%jmp T_0.9;
T_0.5 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55ec9066dc80_0, 0, 32;
T_0.10 ;
%load/vec4 v0x55ec9066dc80_0;
%cmpi/s 4, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.11, 5;
%load/vec4 v0x55ec9066d9b0_0;
%load/vec4 v0x55ec9066dc80_0;
%part/s 1;
%load/vec4 v0x55ec9066d9b0_0;
%load/vec4 v0x55ec9066dc80_0;
%addi 1, 0, 32;
%part/s 1;
%cmp/e;
%jmp/0xz T_0.12, 4;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
%jmp T_0.13;
T_0.12 ;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
T_0.13 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55ec9066dc80_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55ec9066dc80_0, 0, 32;
%jmp T_0.10;
T_0.11 ;
%jmp T_0.9;
T_0.6 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55ec90618c00_0, 0, 32;
T_0.14 ;
%load/vec4 v0x55ec90618c00_0;
%cmpi/s 5, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.15, 5;
%load/vec4 v0x55ec9066d9b0_0;
%load/vec4 v0x55ec90618c00_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.16, 4;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
%jmp T_0.17;
T_0.16 ;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
T_0.17 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55ec90618c00_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55ec90618c00_0, 0, 32;
%jmp T_0.14;
T_0.15 ;
%jmp T_0.9;
T_0.7 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55ec9066db50_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55ec9066d8d0_0, 0, 32;
T_0.18 ;
%load/vec4 v0x55ec9066d8d0_0;
%cmpi/s 5, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.19, 5;
%load/vec4 v0x55ec9066d9b0_0;
%load/vec4 v0x55ec9066d8d0_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.20, 4;
%load/vec4 v0x55ec9066db50_0;
%addi 1, 0, 32;
%store/vec4 v0x55ec9066db50_0, 0, 32;
T_0.20 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55ec9066d8d0_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55ec9066d8d0_0, 0, 32;
%jmp T_0.18;
T_0.19 ;
%load/vec4 v0x55ec9066db50_0;
%pushi/vec4 2, 0, 32;
%mod/s;
%cmpi/e 0, 0, 32;
%jmp/0xz T_0.22, 4;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
%jmp T_0.23;
T_0.22 ;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
T_0.23 ;
%jmp T_0.9;
T_0.8 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55ec9066db50_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55ec9066da70_0, 0, 32;
T_0.24 ;
%load/vec4 v0x55ec9066da70_0;
%cmpi/s 5, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.25, 5;
%load/vec4 v0x55ec9066d9b0_0;
%load/vec4 v0x55ec9066da70_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.26, 4;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55ec9066db50_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55ec9066db50_0, 0, 32;
T_0.26 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55ec9066da70_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55ec9066da70_0, 0, 32;
%jmp T_0.24;
T_0.25 ;
%load/vec4 v0x55ec9066db50_0;
%pushi/vec4 2, 0, 32;
%mod/s;
%cmpi/e 0, 0, 32;
%jmp/0xz T_0.28, 4;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
%jmp T_0.29;
T_0.28 ;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
T_0.29 ;
%jmp T_0.9;
T_0.9 ;
%pop/vec4 1;
%jmp T_0;
.thread T_0, $push;
.scope S_0x55ec90657360;
T_1 ;
%vpi_call 2 12 "$dumpfile", "bib3.vcd" {0 0 0};
%vpi_call 2 13 "$dumpvars" {0 0 0};
%pushi/vec4 9, 0, 9;
%store/vec4 v0x55ec9066dea0_0, 0, 9;
%delay 5, 0;
%pushi/vec4 97, 0, 9;
%store/vec4 v0x55ec9066dea0_0, 0, 9;
%delay 5, 0;
%pushi/vec4 165, 0, 9;
%store/vec4 v0x55ec9066dea0_0, 0, 9;
%delay 5, 0;
%pushi/vec4 227, 0, 9;
%store/vec4 v0x55ec9066dea0_0, 0, 9;
%delay 5, 0;
%pushi/vec4 319, 0, 9;
%store/vec4 v0x55ec9066dea0_0, 0, 9;
%delay 5, 0;
%pushi/vec4 289, 0, 9;
%store/vec4 v0x55ec9066dea0_0, 0, 9;
%delay 5, 0;
%pushi/vec4 353, 0, 9;
%store/vec4 v0x55ec9066dea0_0, 0, 9;
%delay 5, 0;
%pushi/vec4 417, 0, 9;
%store/vec4 v0x55ec9066dea0_0, 0, 9;
%delay 5, 0;
%pushi/vec4 481, 0, 9;
%store/vec4 v0x55ec9066dea0_0, 0, 9;
%delay 5, 0;
%end;
.thread T_1;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"bib3TB.v";
"bib3.v";

49
iverilog/tobb/lab4/bib3.v Normal file
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module bib3 (
input [8:0] buyruk,
output reg [3:0] sonuc
);
integer i, a, b, c, count;
always@(buyruk) begin
case (buyruk[8:6])
default: sonuc = 4'b0000;
3'b000: sonuc = buyruk[5:3] + buyruk[2:0];
3'b001: sonuc = buyruk[5:3] - buyruk[2:0];
3'b010: sonuc = buyruk[5:3] & buyruk[2:0];
3'b011: sonuc = buyruk[5:3] | buyruk[2:0];
3'b100: begin
for (i = 0; i <= 4; i++)
if (buyruk[i] == buyruk[i+1])
sonuc = 4'b1111;
else
sonuc = 4'b0000;
end
3'b101: for (a = 0; a <= 5; a++) begin
if (buyruk[a] == 1)
sonuc = 4'b1111;
else
sonuc = 4'b0000;
end
3'b110: begin
count = 0;
for (b = 0; b <= 5; b++) begin
if (buyruk[b] == 1)
count = count + 1;
end
if (count % 2 == 0)
sonuc = 4'b1111;
else
sonuc = 4'b0000;
end
3'b111: begin
count = 0;
for (c = 0; c <= 5; c++)
if (buyruk[c] == 1)
count++;
if (count % 2 == 0)
sonuc = 4'b0000;
else
sonuc = 4'b1111;
end
endcase
end
endmodule

81
iverilog/tobb/lab4/bib3.vcd Normal file
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@ -0,0 +1,81 @@
$date
Sat Jan 25 01:26:43 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module bib3TB $end
$var wire 4 ! Y [3:0] $end
$var reg 9 " A [8:0] $end
$scope module uut $end
$var wire 9 # buyruk [8:0] $end
$var reg 4 $ sonuc [3:0] $end
$var integer 32 % a [31:0] $end
$var integer 32 & b [31:0] $end
$var integer 32 ' c [31:0] $end
$var integer 32 ( count [31:0] $end
$var integer 32 ) i [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
bx )
bx (
bx '
bx &
bx %
b10 $
b1001 #
b1001 "
b10 !
$end
#5
b11 !
b11 $
b1100001 "
b1100001 #
#10
b100 !
b100 $
b10100101 "
b10100101 #
#15
b111 !
b111 $
b11100011 "
b11100011 #
#20
b1111 !
b1111 $
b101 )
b100111111 "
b100111111 #
#25
b0 !
b0 $
b101 )
b100100001 "
b100100001 #
#30
b1111 !
b1111 $
b110 %
b101100001 "
b101100001 #
#35
b110 &
b10 (
b110100001 "
b110100001 #
#40
b0 !
b0 $
b110 '
b10 (
b111100001 "
b111100001 #
#45

25
iverilog/tobb/lab4/bib3TB.v Normal file
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@ -0,0 +1,25 @@
module bib3TB();
reg [8:0] A;
wire [3:0] Y;
bib3 uut (
.buyruk(A),
.sonuc(Y)
);
initial begin
$dumpfile("bib3.vcd");
$dumpvars;
A = 9'b000_001_001; #5;
A = 9'b001_100_001; #5;
A = 9'b010_100_101; #5;
A = 9'b011_100_011; #5;
A = 9'b100_111_111; #5;
A = 9'b100_100_001; #5;
A = 9'b101_100_001; #5;
A = 9'b110_100_001; #5;
A = 9'b111_100_001; #5;
end
endmodule

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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55a0b73b0f40 .scope module, "sube3soru2TB" "sube3soru2TB" 2 1;
.timescale 0 0;
v0x55a0b73c4170_0 .var "A", 9 0;
v0x55a0b73c4250_0 .var "B", 5 0;
v0x55a0b73c4320_0 .net "D", 4 0, v0x55a0b73c3b30_0; 1 drivers
v0x55a0b73c4420_0 .net "l1", 4 0, v0x55a0b73c3d00_0; 1 drivers
v0x55a0b73c44f0_0 .net "l2", 4 0, v0x55a0b73c3e30_0; 1 drivers
S_0x55a0b73b10d0 .scope module, "uut" "sube3soru2" 2 7, 3 1 0, S_0x55a0b73b0f40;
.timescale 0 0;
.port_info 0 /INPUT 10 "A";
.port_info 1 /INPUT 6 "B";
.port_info 2 /OUTPUT 5 "D";
.port_info 3 /OUTPUT 5 "l1";
.port_info 4 /OUTPUT 5 "l2";
v0x55a0b7376c00_0 .net "A", 9 0, v0x55a0b73c4170_0; 1 drivers
v0x55a0b73c3a50_0 .net "B", 5 0, v0x55a0b73c4250_0; 1 drivers
v0x55a0b73c3b30_0 .var "D", 4 0;
v0x55a0b73c3c20_0 .var/i "hunderedR", 31 0;
v0x55a0b73c3d00_0 .var "l1", 4 0;
v0x55a0b73c3e30_0 .var "l2", 4 0;
v0x55a0b73c3f10_0 .var/i "tempD", 31 0;
v0x55a0b73c3ff0_0 .var/i "tempO", 31 0;
E_0x55a0b73ae360 .event edge, v0x55a0b73c3a50_0, v0x55a0b7376c00_0;
.scope S_0x55a0b73b10d0;
T_0 ;
%wait E_0x55a0b73ae360;
%load/vec4 v0x55a0b7376c00_0;
%parti/s 8, 2, 3;
%pad/u 32;
%muli 100, 0, 32;
%store/vec4 v0x55a0b73c3c20_0, 0, 32;
%load/vec4 v0x55a0b7376c00_0;
%parti/s 2, 0, 2;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_0.0, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_0.1, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_0.2, 6;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55a0b73c3f10_0, 0, 32;
%jmp T_0.4;
T_0.0 ;
%pushi/vec4 25, 0, 32;
%store/vec4 v0x55a0b73c3f10_0, 0, 32;
%jmp T_0.4;
T_0.1 ;
%pushi/vec4 50, 0, 32;
%store/vec4 v0x55a0b73c3f10_0, 0, 32;
%jmp T_0.4;
T_0.2 ;
%pushi/vec4 75, 0, 32;
%store/vec4 v0x55a0b73c3f10_0, 0, 32;
%jmp T_0.4;
T_0.4 ;
%pop/vec4 1;
%load/vec4 v0x55a0b73c3c20_0;
%load/vec4 v0x55a0b73c3f10_0;
%add;
%store/vec4 v0x55a0b73c3ff0_0, 0, 32;
%load/vec4 v0x55a0b73c3ff0_0;
%load/vec4 v0x55a0b73c3a50_0;
%pad/u 32;
%div;
%store/vec4 v0x55a0b73c3ff0_0, 0, 32;
%load/vec4 v0x55a0b73c3ff0_0;
%pushi/vec4 100, 0, 32;
%div/s;
%pad/s 5;
%store/vec4 v0x55a0b73c3b30_0, 0, 5;
%load/vec4 v0x55a0b73c3ff0_0;
%pushi/vec4 100, 0, 32;
%mod/s;
%pushi/vec4 10, 0, 32;
%div/s;
%pad/s 5;
%store/vec4 v0x55a0b73c3d00_0, 0, 5;
%load/vec4 v0x55a0b73c3ff0_0;
%pushi/vec4 10, 0, 32;
%mod/s;
%pad/s 5;
%store/vec4 v0x55a0b73c3e30_0, 0, 5;
%jmp T_0;
.thread T_0, $push;
.scope S_0x55a0b73b0f40;
T_1 ;
%vpi_call 2 16 "$dumpfile", "sube3soru2.vcd" {0 0 0};
%vpi_call 2 17 "$dumpvars" {0 0 0};
%pushi/vec4 25, 0, 10;
%store/vec4 v0x55a0b73c4170_0, 0, 10;
%pushi/vec4 3, 0, 6;
%store/vec4 v0x55a0b73c4250_0, 0, 6;
%delay 5, 0;
%vpi_call 2 19 "$finish" {0 0 0};
%end;
.thread T_1;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"sube3soru2TB.v";
"sube3soru2.v";

24
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module sube3soru2 (
input [9:0] A,
input [5:0] B,
output reg [4:0] D,l1,l2
);
integer tempD, tempO, hunderedR;
always@(A or B) begin
hunderedR = A[9:2] * 100;
case(A[1:0])
2'b01: tempD = 25;
2'b10: tempD = 50;
2'b11: tempD = 75;
default: tempD = 00;
endcase
tempO = hunderedR + tempD;
tempO = tempO / B;
D = tempO / 100;
l1 = (tempO%100)/10;
l2 = tempO%10;
end
endmodule

44
iverilog/tobb/lab4/sube3soru2.vcd Normal file
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@ -0,0 +1,44 @@
$date
Sat Jan 25 03:14:14 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module sube3soru2TB $end
$var wire 5 ! l2 [4:0] $end
$var wire 5 " l1 [4:0] $end
$var wire 5 # D [4:0] $end
$var reg 10 $ A [9:0] $end
$var reg 6 % B [5:0] $end
$scope module uut $end
$var wire 10 & A [9:0] $end
$var wire 6 ' B [5:0] $end
$var reg 5 ( D [4:0] $end
$var reg 5 ) l1 [4:0] $end
$var reg 5 * l2 [4:0] $end
$var integer 32 + hunderedR [31:0] $end
$var integer 32 , tempD [31:0] $end
$var integer 32 - tempO [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b11010000 -
b11001 ,
b1001011000 +
b1000 *
b0 )
b10 (
b11 '
b11001 &
b11 %
b11001 $
b10 #
b0 "
b1000 !
$end
#5

22
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module sube3soru2TB();
reg [9:0] A;
reg [5:0] B;
wire [4:0] D,l1,l2;
sube3soru2 uut (
.A(A),
.B(B),
.D(D),
.l1(l1),
.l2(l2)
);
initial begin
$dumpfile("sube3soru2.vcd");
$dumpvars;
A = 10'b0000011001; B = 6'b000011; #5;
$finish;
end
endmodule

193
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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55b4b9d0fd50 .scope module, "ayarliSayacTB" "ayarliSayacTB" 2 1;
.timescale 0 0;
v0x55b4b9d66830_0 .var "clk", 0 0;
v0x55b4b9d668f0_0 .var "en", 0 0;
v0x55b4b9d669c0_0 .var "rst", 0 0;
v0x55b4b9d66ac0_0 .net "sayac", 5 0, v0x55b4b9d664f0_0; 1 drivers
v0x55b4b9d66b90_0 .var "sayma_miktari", 2 0;
v0x55b4b9d66c80_0 .var "sayma_yonu", 0 0;
S_0x55b4b9d0fee0 .scope module, "uut" "sayac" 2 8, 3 1 0, S_0x55b4b9d0fd50;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst";
.port_info 2 /INPUT 1 "en";
.port_info 3 /INPUT 3 "sayma_miktari";
.port_info 4 /INPUT 1 "sayma_yonu";
.port_info 5 /OUTPUT 6 "sayac";
v0x55b4b9d4e5b0_0 .net "clk", 0 0, v0x55b4b9d66830_0; 1 drivers
v0x55b4b9d66180_0 .var "clk_divider", 1 0;
v0x55b4b9d66260_0 .net "en", 0 0, v0x55b4b9d668f0_0; 1 drivers
v0x55b4b9d66300_0 .var "miktar", 2 0;
v0x55b4b9d663e0_0 .net "rst", 0 0, v0x55b4b9d669c0_0; 1 drivers
v0x55b4b9d664f0_0 .var "sayac", 5 0;
v0x55b4b9d665d0_0 .net "sayma_miktari", 2 0, v0x55b4b9d66b90_0; 1 drivers
v0x55b4b9d666b0_0 .net "sayma_yonu", 0 0, v0x55b4b9d66c80_0; 1 drivers
E_0x55b4b9d4f1d0/0 .event negedge, v0x55b4b9d4e5b0_0;
E_0x55b4b9d4f1d0/1 .event posedge, v0x55b4b9d663e0_0;
E_0x55b4b9d4f1d0 .event/or E_0x55b4b9d4f1d0/0, E_0x55b4b9d4f1d0/1;
.scope S_0x55b4b9d0fee0;
T_0 ;
%pushi/vec4 0, 0, 6;
%store/vec4 v0x55b4b9d664f0_0, 0, 6;
%pushi/vec4 0, 0, 2;
%store/vec4 v0x55b4b9d66180_0, 0, 2;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55b4b9d66300_0, 0, 3;
%end;
.thread T_0;
.scope S_0x55b4b9d0fee0;
T_1 ;
%wait E_0x55b4b9d4f1d0;
%load/vec4 v0x55b4b9d663e0_0;
%flag_set/vec4 8;
%jmp/0xz T_1.0, 8;
%pushi/vec4 0, 0, 6;
%assign/vec4 v0x55b4b9d664f0_0, 0;
%pushi/vec4 0, 0, 2;
%assign/vec4 v0x55b4b9d66180_0, 0;
%pushi/vec4 0, 0, 3;
%assign/vec4 v0x55b4b9d66300_0, 0;
%jmp T_1.1;
T_1.0 ;
%load/vec4 v0x55b4b9d66180_0;
%addi 1, 0, 2;
%assign/vec4 v0x55b4b9d66180_0, 0;
%load/vec4 v0x55b4b9d66180_0;
%cmpi/e 3, 0, 2;
%jmp/0xz T_1.2, 4;
%pushi/vec4 0, 0, 2;
%assign/vec4 v0x55b4b9d66180_0, 0;
%load/vec4 v0x55b4b9d66260_0;
%flag_set/vec4 8;
%jmp/0xz T_1.4, 8;
%load/vec4 v0x55b4b9d665d0_0;
%assign/vec4 v0x55b4b9d66300_0, 0;
T_1.4 ;
%load/vec4 v0x55b4b9d666b0_0;
%flag_set/vec4 8;
%jmp/0xz T_1.6, 8;
%load/vec4 v0x55b4b9d664f0_0;
%load/vec4 v0x55b4b9d66300_0;
%pad/u 6;
%add;
%cmpi/u 63, 0, 6;
%flag_inv 5; GE is !LT
%jmp/0xz T_1.8, 5;
%pushi/vec4 63, 0, 6;
%assign/vec4 v0x55b4b9d664f0_0, 0;
%jmp T_1.9;
T_1.8 ;
%load/vec4 v0x55b4b9d664f0_0;
%load/vec4 v0x55b4b9d66300_0;
%pad/u 6;
%add;
%assign/vec4 v0x55b4b9d664f0_0, 0;
T_1.9 ;
%jmp T_1.7;
T_1.6 ;
%load/vec4 v0x55b4b9d664f0_0;
%load/vec4 v0x55b4b9d66300_0;
%pad/u 6;
%cmp/u;
%flag_or 5, 4;
%jmp/0xz T_1.10, 5;
%pushi/vec4 0, 0, 6;
%assign/vec4 v0x55b4b9d664f0_0, 0;
%jmp T_1.11;
T_1.10 ;
%load/vec4 v0x55b4b9d664f0_0;
%load/vec4 v0x55b4b9d66300_0;
%pad/u 6;
%sub;
%assign/vec4 v0x55b4b9d664f0_0, 0;
T_1.11 ;
T_1.7 ;
T_1.2 ;
T_1.1 ;
%jmp T_1;
.thread T_1;
.scope S_0x55b4b9d0fd50;
T_2 ;
%load/vec4 v0x55b4b9d66830_0;
%inv;
%store/vec4 v0x55b4b9d66830_0, 0, 1;
%delay 1, 0;
%jmp T_2;
.thread T_2;
.scope S_0x55b4b9d0fd50;
T_3 ;
%vpi_call 2 22 "$dumpfile", "ayarliSayac.vcd" {0 0 0};
%vpi_call 2 23 "$dumpvars" {0 0 0};
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66830_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55b4b9d669c0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d668f0_0, 0, 1;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b4b9d66b90_0, 0, 3;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66c80_0, 0, 1;
%delay 32, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66830_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55b4b9d669c0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d668f0_0, 0, 1;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b4b9d66b90_0, 0, 3;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66c80_0, 0, 1;
%delay 8, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66830_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55b4b9d669c0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d668f0_0, 0, 1;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b4b9d66b90_0, 0, 3;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66c80_0, 0, 1;
%delay 64, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66830_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55b4b9d669c0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d668f0_0, 0, 1;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b4b9d66b90_0, 0, 3;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66c80_0, 0, 1;
%delay 16, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66830_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d669c0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d668f0_0, 0, 1;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x55b4b9d66b90_0, 0, 3;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66c80_0, 0, 1;
%delay 8, 0;
%vpi_call 2 29 "$finish" {0 0 0};
%end;
.thread T_3;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"ayarliSayacTB.v";
"sayac.v";

43
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@ -0,0 +1,43 @@
module ayarliSayac (
input clk, rst, en,
input [2:0] sayma_miktari,
input sayma_yonu,
output reg [5:0] sayac
);
reg [2:0] miktar;
reg [1:0] clk_divider;
initial begin
sayac = 6'b0000_00;
miktar = 3'b001;
clk_divider = 2'b00;
end
always @(negedge clk or posedge rst) begin
if (rst) begin
sayac <= 6'b0000_00;
clk_divider <= 2'b00;
end else begin
clk_divider <= clk_divider + 1;
end
if (clk_divider == 2'b11) begin
if (en) begin
miktar = sayma_miktari;
if (sayma_yonu == 1) begin
if (sayac + miktar >= 6'b1111_11) begin
sayac <= 6'b1111_11;
end else begin
sayac <= miktar + sayac;
end
end else begin
if (sayac - miktar <= 6'b0000_00) begin
sayac <= 6'b0000_00;
end else begin
sayac <= sayac - miktar;
end
end
end
end
end
endmodule

393
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@ -0,0 +1,393 @@
$date
Sun Jan 26 04:55:11 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module ayarliSayacTB $end
$var wire 6 ! sayac [5:0] $end
$var reg 1 " clk $end
$var reg 1 # en $end
$var reg 1 $ rst $end
$var reg 3 % sayma_miktari [2:0] $end
$var reg 1 & sayma_yonu $end
$scope module uut $end
$var wire 1 " clk $end
$var wire 1 # en $end
$var wire 1 $ rst $end
$var wire 3 ' sayma_miktari [2:0] $end
$var wire 1 & sayma_yonu $end
$var reg 2 ( clk_divider [1:0] $end
$var reg 3 ) miktar [2:0] $end
$var reg 6 * sayac [5:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 *
b0 )
b0 (
b111 '
1&
b111 %
0$
1#
1"
b0 !
$end
#1
b1 (
0"
#2
1"
#3
b10 (
0"
#4
1"
#5
b11 (
0"
#6
1"
#7
b111 )
b0 (
0"
#8
1"
#9
b1 (
0"
#10
1"
#11
b10 (
0"
#12
1"
#13
b11 (
0"
#14
1"
#15
b111 !
b111 *
b0 (
0"
#16
1"
#17
b1 (
0"
#18
1"
#19
b10 (
0"
#20
1"
#21
b11 (
0"
#22
1"
#23
b1110 !
b1110 *
b0 (
0"
#24
1"
#25
b1 (
0"
#26
1"
#27
b10 (
0"
#28
1"
#29
b11 (
0"
#30
1"
#31
b10101 !
b10101 *
b0 (
0"
#32
b1 (
0"
#33
1"
#34
b10 (
0"
#35
1"
#36
b11 (
0"
#37
1"
#38
b11100 !
b11100 *
b0 (
0"
#39
1"
#40
b1 (
0"
#41
1"
#42
b10 (
0"
#43
1"
#44
b11 (
0"
#45
1"
#46
b100011 !
b100011 *
b0 (
0"
#47
1"
#48
b1 (
0"
#49
1"
#50
b10 (
0"
#51
1"
#52
b11 (
0"
#53
1"
#54
b101010 !
b101010 *
b0 (
0"
#55
1"
#56
b1 (
0"
#57
1"
#58
b10 (
0"
#59
1"
#60
b11 (
0"
#61
1"
#62
b110001 !
b110001 *
b0 (
0"
#63
1"
#64
b1 (
0"
#65
1"
#66
b10 (
0"
#67
1"
#68
b11 (
0"
#69
1"
#70
b111000 !
b#70
00 *
b0 (
0"
#71
1"
#72
b1 (
0"
#73
1"
#74
b10 (
0"
#75
1"
#76
b11 (
0"
#77
1"
#78
b111111 !
b111111 *
b0 (
0"
#79
1"
#80
b1 (
0"
#81
1"
#82
b10 (
0"
#83
1"
#84
b11 (
0"
#85
1"
#86
b110 !
b110 *
b0 (
0"
#87
1"
#88
b1 (
0"
#89
1"
#90
b10 (
0"
#91
1"
#92
b11 (
0"
#93
1"
#94
b1101 !
b1101 *
b0 (
0"
#95
1"
#96
b1 (
0"
#97
1"
#98
b10 (
0"
#99
1"
#100
b11 (
0"
#101
1"
#102
b10100 !
b10100 *
b0 (
0"
#103
1"
#104
b1 (
0"
#105
1"
#106
b10 (
0"
#107
1"
#108
b11 (
0"
#109
1"
#110
b11011 !
b11011 *
b0 (
0"
#111
1"
#112
b1 (
0"
#113
1"
#114
b10 (
0"
#115
1"
#116
b11 (
0"
#117
1"
#118
b100010 !
b100010 *
b0 (
0"
#119
1"
#120
b0 )
b0 !
b0 *
0"
b10 %
b10 '
1$
#121
1"
#122
0"
#123
1"
#124
0"
#125
1"
#126
0"
#127
1"
#128
0"

32
iverilog/tobb/lab5/ayarliSayacTB.v Normal file
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@ -0,0 +1,32 @@
module ayarliSayacTB();
reg clk, rst, en;
reg [2:0] sayma_miktari;
reg sayma_yonu;
wire [5:0] sayac;
sayac uut (
.clk(clk),
.rst(rst),
.en(en),
.sayma_miktari(sayma_miktari),
.sayma_yonu(sayma_yonu),
.sayac(sayac)
);
always begin
clk = ~clk; #1;
end
initial begin
$dumpfile("ayarliSayac.vcd");
$dumpvars;
clk = 1; rst = 0; en = 1; sayma_miktari = 3'b111; sayma_yonu = 1'b1; #32;
clk = 1; rst = 0; en = 1; sayma_miktari = 3'b111; sayma_yonu = 1'b1; #8;
clk = 1; rst = 0; en = 1; sayma_miktari = 3'b111; sayma_yonu = 1'b1; #64;
clk = 1; rst = 0; en = 1; sayma_miktari = 3'b111; sayma_yonu = 1'b1; #16;
clk = 1; rst = 1; en = 1; sayma_miktari = 3'b010; sayma_yonu = 1'b1; #8;
$finish;
end
endmodule

101
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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55c07fb12c40 .scope module, "knightRiderTB" "knightRiderTB" 2 1;
.timescale 0 0;
v0x55c07fb24010_0 .var "clk", 0 0;
v0x55c07fb240e0_0 .net "leds", 7 0, v0x55c07fb23ef0_0; 1 drivers
S_0x55c07fb12dd0 .scope module, "uut" "knightRider" 2 6, 3 1 0, S_0x55c07fb12c40;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /OUTPUT 8 "leds";
v0x55c07fad87f0_0 .net "clk", 0 0, v0x55c07fb24010_0; 1 drivers
v0x55c07fad8c00_0 .var "direction", 0 0;
v0x55c07fb23ef0_0 .var "leds", 7 0;
E_0x55c07fad7810 .event posedge, v0x55c07fad87f0_0;
.scope S_0x55c07fb12dd0;
T_0 ;
%pushi/vec4 7, 0, 8;
%store/vec4 v0x55c07fb23ef0_0, 0, 8;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55c07fad8c00_0, 0, 1;
%end;
.thread T_0;
.scope S_0x55c07fb12dd0;
T_1 ;
%wait E_0x55c07fad7810;
%load/vec4 v0x55c07fad8c00_0;
%pad/u 32;
%cmpi/e 0, 0, 32;
%jmp/0xz T_1.0, 4;
%load/vec4 v0x55c07fb23ef0_0;
%cmpi/e 224, 0, 8;
%jmp/0xz T_1.2, 4;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55c07fad8c00_0, 0;
%load/vec4 v0x55c07fb23ef0_0;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%shiftr 4;
%assign/vec4 v0x55c07fb23ef0_0, 0;
%jmp T_1.3;
T_1.2 ;
%load/vec4 v0x55c07fb23ef0_0;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%shiftl 4;
%assign/vec4 v0x55c07fb23ef0_0, 0;
T_1.3 ;
%jmp T_1.1;
T_1.0 ;
%load/vec4 v0x55c07fb23ef0_0;
%cmpi/e 7, 0, 8;
%jmp/0xz T_1.4, 4;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x55c07fad8c00_0, 0;
%load/vec4 v0x55c07fb23ef0_0;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%shiftl 4;
%assign/vec4 v0x55c07fb23ef0_0, 0;
%jmp T_1.5;
T_1.4 ;
%load/vec4 v0x55c07fb23ef0_0;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%shiftr 4;
%assign/vec4 v0x55c07fb23ef0_0, 0;
T_1.5 ;
T_1.1 ;
%jmp T_1;
.thread T_1;
.scope S_0x55c07fb12c40;
T_2 ;
%load/vec4 v0x55c07fb24010_0;
%inv;
%store/vec4 v0x55c07fb24010_0, 0, 1;
%delay 2, 0;
%jmp T_2;
.thread T_2;
.scope S_0x55c07fb12c40;
T_3 ;
%vpi_call 2 16 "$dumpfile", "knightRider.vcd" {0 0 0};
%vpi_call 2 17 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55c07fb24010_0, 0, 1;
%delay 50, 0;
%vpi_call 2 19 "$finish" {0 0 0};
%end;
.thread T_3;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"knightRiderTB.v";
"knightRider.v";

31
iverilog/tobb/lab5/knightRider.v Normal file
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module knightRider (
input clk,
output reg [7:0] leds
);
reg direction;
initial begin
leds = 8'b0000_0111;
direction = 1'b0; // 0 left to right
end
always@(posedge clk) begin
if (direction == 0) begin
if (leds == 8'b1110_0000) begin
direction <= 1;
leds <= leds >> 1;
end else begin
leds <= leds << 1;
end
end else begin
if (leds == 8'b0000_0111) begin
direction <= 0;
leds <= leds << 1;
end else begin
leds <= leds >> 1;
end
end
end
endmodule

104
iverilog/tobb/lab5/knightRider.vcd Normal file
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@ -0,0 +1,104 @@
$date
Sat Jan 25 05:37:22 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module knightRiderTB $end
$var wire 8 ! leds [7:0] $end
$var reg 1 " clk $end
$scope module uut $end
$var wire 1 " clk $end
$var reg 1 # direction $end
$var reg 8 $ leds [7:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b111 $
0#
0"
b111 !
$end
#2
b1110 !
b1110 $
1"
#4
0"
#6
b11100 !
b11100 $
1"
#8
0"
#10
b111000 !
b111000 $
1"
#12
0"
#14
b1110000 !
b1110000 $
1"
#16
0"
#18
b11100000 !
b11100000 $
1"
#20
0"
#22
b1110000 !
b1110000 $
1#
1"
#24
0"
#26
b111000 !
b111000 $
1"
#28
0"
#30
b11100 !
b11100 $
1"
#32
0"
#34
b1110 !
b1110 $
1"
#36
0"
#38
b111 !
b111 $
1"
#40
0"
#42
b1110 !
b1110 $
0#
1"
#44
0"
#46
b11100 !
b11100 $
1"
#48
0"
#50
b111000 !
b111000 $
1"

22
iverilog/tobb/lab5/knightRiderTB.v Normal file
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@ -0,0 +1,22 @@
module knightRiderTB();
reg clk;
wire [7:0] leds;
knightRider uut (
.clk(clk),
.leds(leds)
);
always begin
clk = ~clk; #2;
end
initial begin
$dumpfile("knightRider.vcd");
$dumpvars;
clk = 0; #50;
$finish;
end
endmodule

48
iverilog/tobb/lab5/sayac.v Normal file
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module sayac (
input clk, rst, en,
input [2:0] sayma_miktari,
input sayma_yonu,
output reg [5:0] sayac
);
reg [1:0] clk_divider;
reg [2:0] miktar;
initial begin
sayac = 6'b0000_00;
miktar = 3'b001;
clk_divider = 2'b00;
end
always@(*) begin
miktar = sayma_miktari;
end
always@(negedge clk or posedge rst) begin
if (rst) begin
sayac <= 6'b0000_00;
clk_divider <= 2'b00;
end else begin
clk_divider <= clk_divider + 1;
end
if (clk_divider == 2'b11) begin
clk_divider <= 2'b00;
if (en) begin
if (sayma_miktari) begin
if (sayac + miktar >= 6'b1111_11) begin
sayac <= 6'b1111_11;
end else begin
sayac <= sayac + miktar;
end
end else begin
if (miktar >= sayac) begin
sayac <= 6'b0000_00;
end else begin
sayac <= sayac - miktar;
end
end
end
end
end
endmodule

177
iverilog/tobb/lab5/tetris Normal file
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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x56335d23e170 .scope module, "tetrisTB" "tetrisTB" 2 1;
.timescale 0 0;
v0x56335d253500_0 .net "bitti_mi", 0 0, v0x56335d200370_0; 1 drivers
v0x56335d2535c0_0 .net "cevrim", 3 0, v0x56335d200c00_0; 1 drivers
v0x56335d253690_0 .var "clk", 0 0;
v0x56335d253790_0 .var "p", 2 0;
v0x56335d253860_0 .net "yukseklik", 3 0, v0x56335d253090_0; 1 drivers
S_0x56335d23e300 .scope module, "uut" "tetris" 2 9, 3 1 0, S_0x56335d23e170;
.timescale 0 0;
.port_info 0 /INPUT 3 "parca";
.port_info 1 /INPUT 1 "clk";
.port_info 2 /OUTPUT 4 "yukseklik";
.port_info 3 /OUTPUT 1 "bitti_mi";
.port_info 4 /OUTPUT 4 "cevrim";
v0x56335d200370_0 .var "bitti_mi", 0 0;
v0x56335d200c00_0 .var "cevrim", 3 0;
v0x56335d252ee0_0 .net "clk", 0 0, v0x56335d253690_0; 1 drivers
v0x56335d252fb0_0 .net "parca", 2 0, v0x56335d253790_0; 1 drivers
v0x56335d253090_0 .var "yukseklik", 3 0;
v0x56335d2531c0_0 .var "yukseklik1", 3 0;
v0x56335d2532a0_0 .var "yukseklik2", 3 0;
v0x56335d253380_0 .var "yukseklik3", 3 0;
E_0x56335d238670 .event posedge, v0x56335d252ee0_0;
.scope S_0x56335d23e300;
T_0 ;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x56335d200c00_0, 0, 4;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56335d200370_0, 0, 1;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x56335d253090_0, 0, 4;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x56335d2531c0_0, 0, 4;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x56335d2532a0_0, 0, 4;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x56335d253380_0, 0, 4;
%end;
.thread T_0;
.scope S_0x56335d23e300;
T_1 ;
%wait E_0x56335d238670;
%load/vec4 v0x56335d200370_0;
%nor/r;
%flag_set/vec4 8;
%jmp/0xz T_1.0, 8;
%load/vec4 v0x56335d252fb0_0;
%parti/s 1, 0, 2;
%flag_set/vec4 8;
%jmp/0xz T_1.2, 8;
%load/vec4 v0x56335d2531c0_0;
%addi 1, 0, 4;
%assign/vec4 v0x56335d2531c0_0, 0;
T_1.2 ;
%load/vec4 v0x56335d252fb0_0;
%parti/s 1, 1, 2;
%flag_set/vec4 8;
%jmp/0xz T_1.4, 8;
%load/vec4 v0x56335d2532a0_0;
%addi 1, 0, 4;
%assign/vec4 v0x56335d2532a0_0, 0;
T_1.4 ;
%load/vec4 v0x56335d252fb0_0;
%parti/s 1, 2, 3;
%flag_set/vec4 8;
%jmp/0xz T_1.6, 8;
%load/vec4 v0x56335d253380_0;
%addi 1, 0, 4;
%assign/vec4 v0x56335d253380_0, 0;
T_1.6 ;
%load/vec4 v0x56335d200c00_0;
%addi 1, 0, 4;
%assign/vec4 v0x56335d200c00_0, 0;
%load/vec4 v0x56335d200c00_0;
%cmpi/e 15, 0, 4;
%jmp/0xz T_1.8, 4;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x56335d200370_0, 0;
T_1.8 ;
T_1.0 ;
%jmp T_1;
.thread T_1;
.scope S_0x56335d23e300;
T_2 ;
%wait E_0x56335d238670;
%load/vec4 v0x56335d200370_0;
%flag_set/vec4 8;
%jmp/0xz T_2.0, 8;
%load/vec4 v0x56335d2532a0_0;
%load/vec4 v0x56335d2531c0_0;
%cmp/u;
%flag_get/vec4 4;
%flag_get/vec4 5;
%or;
%load/vec4 v0x56335d253380_0;
%load/vec4 v0x56335d2531c0_0;
%cmp/u;
%flag_get/vec4 4;
%flag_get/vec4 5;
%or;
%and;
%flag_set/vec4 8;
%jmp/0xz T_2.2, 8;
%load/vec4 v0x56335d2531c0_0;
%assign/vec4 v0x56335d253090_0, 0;
%jmp T_2.3;
T_2.2 ;
%load/vec4 v0x56335d2531c0_0;
%load/vec4 v0x56335d2532a0_0;
%cmp/u;
%flag_get/vec4 4;
%flag_get/vec4 5;
%or;
%load/vec4 v0x56335d253380_0;
%load/vec4 v0x56335d2532a0_0;
%cmp/u;
%flag_get/vec4 4;
%flag_get/vec4 5;
%or;
%and;
%flag_set/vec4 8;
%jmp/0xz T_2.4, 8;
%load/vec4 v0x56335d2532a0_0;
%assign/vec4 v0x56335d253090_0, 0;
%jmp T_2.5;
T_2.4 ;
%load/vec4 v0x56335d253380_0;
%assign/vec4 v0x56335d253090_0, 0;
T_2.5 ;
T_2.3 ;
T_2.0 ;
%jmp T_2;
.thread T_2;
.scope S_0x56335d23e170;
T_3 ;
%load/vec4 v0x56335d253690_0;
%inv;
%store/vec4 v0x56335d253690_0, 0, 1;
%delay 1, 0;
%jmp T_3;
.thread T_3;
.scope S_0x56335d23e170;
T_4 ;
%vpi_call 2 22 "$dumpfile", "tetris.vcd" {0 0 0};
%vpi_call 2 23 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56335d253690_0, 0, 1;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x56335d253790_0, 0, 3;
%delay 2, 0;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x56335d253790_0, 0, 3;
%delay 2, 0;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x56335d253790_0, 0, 3;
%delay 2, 0;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x56335d253790_0, 0, 3;
%delay 30, 0;
%vpi_call 2 28 "$finish" {0 0 0};
%end;
.thread T_4;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"tetrisTB.v";
"tetris.v";

49
iverilog/tobb/lab5/tetris.v Normal file
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@ -0,0 +1,49 @@
module tetris (
input [2:0] parca,
input clk,
output reg [3:0] yukseklik,
output reg bitti_mi,
output reg [3:0] cevrim
);
reg [3:0] yukseklik1, yukseklik2, yukseklik3;
initial begin
cevrim = 4'd0;
bitti_mi = 1'b0;
yukseklik = 4'b0;
yukseklik1 = 4'd0;
yukseklik2 = 4'd0;
yukseklik3 = 4'd0;
end
always@(posedge clk) begin
if (!bitti_mi) begin
if (parca[0]) begin
yukseklik1 <= yukseklik1 + 1;
end if (parca[1]) begin
yukseklik2 <= yukseklik2 + 1;
end if (parca[2]) begin
yukseklik3 <= yukseklik3 + 1;
end
cevrim <= cevrim + 1;
if (cevrim == 4'd15) begin
bitti_mi <= 1'b1;
end
end
end
always@(posedge clk) begin //comperator
if (bitti_mi) begin
if (yukseklik1 >= yukseklik2 && yukseklik1 >= yukseklik3) begin
yukseklik <= yukseklik1;
end else if (yukseklik2 >= yukseklik1 && yukseklik2 >= yukseklik3) begin
yukseklik <= yukseklik2;
end else begin
yukseklik <= yukseklik3;
end
end
end
endmodule

158
iverilog/tobb/lab5/tetris.vcd Normal file
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@ -0,0 +1,158 @@
$date
Sun Jan 26 06:03:11 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module tetrisTB $end
$var wire 4 ! yukseklik [3:0] $end
$var wire 4 " cevrim [3:0] $end
$var wire 1 # bitti_mi $end
$var reg 1 $ clk $end
$var reg 3 % p [2:0] $end
$scope module uut $end
$var wire 1 $ clk $end
$var wire 3 & parca [2:0] $end
$var reg 1 # bitti_mi $end
$var reg 4 ' cevrim [3:0] $end
$var reg 4 ( yukseklik [3:0] $end
$var reg 4 ) yukseklik1 [3:0] $end
$var reg 4 * yukseklik2 [3:0] $end
$var reg 4 + yukseklik3 [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 +
b0 *
b0 )
b0 (
b0 '
b10 &
b10 %
0$
0#
b0 "
b0 !
$end
#1
b1 "
b1 '
b1 *
1$
#2
0$
b11 %
b11 &
#3
b10 "
b10 '
b10 *
b1 )
1$
#4
0$
b10 %
b10 &
#5
b11 "
b11 '
b11 *
1$
#6
0$
b0 %
b0 &
#7
b100 "
b100 '
1$
#8
0$
#9
b101 "
b101 '
1$
#10
0$
#11
b110 "
b110 '
1$
#12
0$
#13
b111 "
b111 '
1$
#14
0$
#15
b1000 "
b1000 '
1$
#16
0$
#17
b1001 "
b1001 '
1$
#18
0$
#19
b1010 "
b1010 '
1$
#20
0$
#21
b1011 "
b1011 '
1$
#22
0$
#23
b1100 "
b1100 '
1$
#24
0$
#25
b1101 "
b1101 '
1$
#26
0$
#27
b1110 "
b1110 '
1$
#28
0$
#29
b1111 "
b1111 '
1$
#30
0$
#31
1#
b0 "
b0 '
1$
#32
0$
#33
b11 !
b11 (
1$
#34
0$
#35
1$
#36
0$

31
iverilog/tobb/lab5/tetrisTB.v Normal file
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@ -0,0 +1,31 @@
module tetrisTB();
reg [2:0] p;
reg clk;
wire [3:0] yukseklik;
wire bitti_mi;
wire [3:0] cevrim;
tetris uut (
.parca(p),
.clk(clk),
.yukseklik(yukseklik),
.bitti_mi(bitti_mi),
.cevrim(cevrim)
);
always begin
clk = ~clk; #1;
end
initial begin
$dumpfile("tetris.vcd");
$dumpvars;
clk = 0; p = 3'b010; #2;
p = 3'b011; #2;
p = 3'b010; #2;
p = 3'b000; #30;
$finish;
end
endmodule

286
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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55e76f51ca80 .scope module, "bibpTB" "bibpTB" 2 1;
.timescale 0 0;
P_0x55e76f51cc10 .param/l "N" 0 2 2, +C4<00000000000000000000000000000011>;
v0x55e76f534860_0 .var "A", 8 0;
v0x55e76f534920_0 .net "sonuc", 3 0, v0x55e76f534720_0; 1 drivers
S_0x55e76f51ccb0 .scope module, "uut" "bibp" 2 6, 3 1 0, S_0x55e76f51ca80;
.timescale 0 0;
.port_info 0 /INPUT 9 "buyruk";
.port_info 1 /OUTPUT 4 "sonuc";
P_0x55e76f51d420 .param/l "N" 0 3 1, +C4<00000000000000000000000000000011>;
v0x55e76f4d8cf0_0 .var/i "a", 31 0;
v0x55e76f534290_0 .var/i "b", 31 0;
v0x55e76f534370_0 .net "buyruk", 8 0, v0x55e76f534860_0; 1 drivers
v0x55e76f534430_0 .var/i "c", 31 0;
v0x55e76f534510_0 .var/i "count", 31 0;
v0x55e76f534640_0 .var/i "i", 31 0;
v0x55e76f534720_0 .var "sonuc", 3 0;
E_0x55e76f511f90 .event edge, v0x55e76f534370_0;
.scope S_0x55e76f51ccb0;
T_0 ;
%wait E_0x55e76f511f90;
%load/vec4 v0x55e76f534370_0;
%parti/s 3, 6, 4;
%dup/vec4;
%pushi/vec4 0, 0, 3;
%cmp/u;
%jmp/1 T_0.1, 6;
%dup/vec4;
%pushi/vec4 1, 0, 3;
%cmp/u;
%jmp/1 T_0.2, 6;
%dup/vec4;
%pushi/vec4 2, 0, 3;
%cmp/u;
%jmp/1 T_0.3, 6;
%dup/vec4;
%pushi/vec4 3, 0, 3;
%cmp/u;
%jmp/1 T_0.4, 6;
%dup/vec4;
%pushi/vec4 4, 0, 3;
%cmp/u;
%jmp/1 T_0.5, 6;
%dup/vec4;
%pushi/vec4 5, 0, 3;
%cmp/u;
%jmp/1 T_0.6, 6;
%dup/vec4;
%pushi/vec4 6, 0, 3;
%cmp/u;
%jmp/1 T_0.7, 6;
%dup/vec4;
%pushi/vec4 7, 0, 3;
%cmp/u;
%jmp/1 T_0.8, 6;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55e76f534720_0, 0, 4;
%jmp T_0.9;
T_0.1 ;
%load/vec4 v0x55e76f534370_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55e76f534370_0;
%parti/s 3, 0, 2;
%pad/u 4;
%add;
%store/vec4 v0x55e76f534720_0, 0, 4;
%jmp T_0.9;
T_0.2 ;
%load/vec4 v0x55e76f534370_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55e76f534370_0;
%parti/s 3, 0, 2;
%pad/u 4;
%sub;
%store/vec4 v0x55e76f534720_0, 0, 4;
%jmp T_0.9;
T_0.3 ;
%load/vec4 v0x55e76f534370_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55e76f534370_0;
%parti/s 3, 0, 2;
%pad/u 4;
%and;
%store/vec4 v0x55e76f534720_0, 0, 4;
%jmp T_0.9;
T_0.4 ;
%load/vec4 v0x55e76f534370_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55e76f534370_0;
%parti/s 3, 0, 2;
%pad/u 4;
%or;
%store/vec4 v0x55e76f534720_0, 0, 4;
%jmp T_0.9;
T_0.5 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55e76f534640_0, 0, 32;
T_0.10 ;
%load/vec4 v0x55e76f534640_0;
%cmpi/s 4, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.11, 5;
%load/vec4 v0x55e76f534370_0;
%load/vec4 v0x55e76f534640_0;
%part/s 1;
%load/vec4 v0x55e76f534370_0;
%load/vec4 v0x55e76f534640_0;
%addi 1, 0, 32;
%part/s 1;
%cmp/e;
%jmp/0xz T_0.12, 4;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x55e76f534720_0, 0, 4;
%jmp T_0.13;
T_0.12 ;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55e76f534720_0, 0, 4;
T_0.13 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55e76f534640_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55e76f534640_0, 0, 32;
%jmp T_0.10;
T_0.11 ;
%jmp T_0.9;
T_0.6 ;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55e76f534720_0, 0, 4;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55e76f4d8cf0_0, 0, 32;
T_0.14 ;
%load/vec4 v0x55e76f4d8cf0_0;
%cmpi/s 6, 0, 32;
%jmp/0xz T_0.15, 5;
%load/vec4 v0x55e76f534370_0;
%load/vec4 v0x55e76f4d8cf0_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.16, 4;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x55e76f534720_0, 0, 4;
T_0.16 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55e76f4d8cf0_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55e76f4d8cf0_0, 0, 32;
%jmp T_0.14;
T_0.15 ;
%jmp T_0.9;
T_0.7 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55e76f534510_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55e76f534290_0, 0, 32;
T_0.18 ;
%load/vec4 v0x55e76f534290_0;
%cmpi/s 6, 0, 32;
%jmp/0xz T_0.19, 5;
%load/vec4 v0x55e76f534370_0;
%load/vec4 v0x55e76f534290_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.20, 4;
%load/vec4 v0x55e76f534510_0;
%addi 1, 0, 32;
%store/vec4 v0x55e76f534510_0, 0, 32;
T_0.20 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55e76f534290_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55e76f534290_0, 0, 32;
%jmp T_0.18;
T_0.19 ;
%load/vec4 v0x55e76f534510_0;
%pushi/vec4 2, 0, 32;
%mod/s;
%cmpi/e 0, 0, 32;
%jmp/0xz T_0.22, 4;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x55e76f534720_0, 0, 4;
%jmp T_0.23;
T_0.22 ;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55e76f534720_0, 0, 4;
T_0.23 ;
%jmp T_0.9;
T_0.8 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55e76f534510_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55e76f534430_0, 0, 32;
T_0.24 ;
%load/vec4 v0x55e76f534430_0;
%cmpi/s 6, 0, 32;
%jmp/0xz T_0.25, 5;
%load/vec4 v0x55e76f534370_0;
%load/vec4 v0x55e76f534430_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.26, 4;
%load/vec4 v0x55e76f534510_0;
%addi 1, 0, 32;
%store/vec4 v0x55e76f534510_0, 0, 32;
T_0.26 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55e76f534430_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55e76f534430_0, 0, 32;
%jmp T_0.24;
T_0.25 ;
%load/vec4 v0x55e76f534510_0;
%pushi/vec4 2, 0, 32;
%mod/s;
%cmpi/e 0, 0, 32;
%jmp/0xz T_0.28, 4;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55e76f534720_0, 0, 4;
%jmp T_0.29;
T_0.28 ;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x55e76f534720_0, 0, 4;
T_0.29 ;
%jmp T_0.9;
T_0.9 ;
%pop/vec4 1;
%jmp T_0;
.thread T_0, $push;
.scope S_0x55e76f51ca80;
T_1 ;
%vpi_call 2 12 "$dumpfile", "bibp.vcd" {0 0 0};
%vpi_call 2 13 "$dumpvars" {0 0 0};
%pushi/vec4 9, 0, 9;
%store/vec4 v0x55e76f534860_0, 0, 9;
%delay 5, 0;
%pushi/vec4 97, 0, 9;
%store/vec4 v0x55e76f534860_0, 0, 9;
%delay 5, 0;
%pushi/vec4 165, 0, 9;
%store/vec4 v0x55e76f534860_0, 0, 9;
%delay 5, 0;
%pushi/vec4 227, 0, 9;
%store/vec4 v0x55e76f534860_0, 0, 9;
%delay 5, 0;
%pushi/vec4 319, 0, 9;
%store/vec4 v0x55e76f534860_0, 0, 9;
%delay 5, 0;
%pushi/vec4 289, 0, 9;
%store/vec4 v0x55e76f534860_0, 0, 9;
%delay 5, 0;
%pushi/vec4 353, 0, 9;
%store/vec4 v0x55e76f534860_0, 0, 9;
%delay 5, 0;
%pushi/vec4 417, 0, 9;
%store/vec4 v0x55e76f534860_0, 0, 9;
%delay 5, 0;
%pushi/vec4 481, 0, 9;
%store/vec4 v0x55e76f534860_0, 0, 9;
%delay 5, 0;
%end;
.thread T_1;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"bibpTB.v";
"bibp.v";

56
iverilog/tobb/lab6/bibp.v Normal file
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@ -0,0 +1,56 @@
module bibp #(parameter N = 3) (
input [(N*2)+2:0] buyruk,
output reg [N:0] sonuc
);
integer i, a, b, c, count;
always @(buyruk) begin
case (buyruk[(N*2)+2:N*2])
default: sonuc = {(N+1){1'b0}};
3'b000: sonuc = buyruk[(N*2)-1:(N*2)-3] + buyruk[(N*2)-4:0];
3'b001: sonuc = buyruk[(N*2)-1:(N*2)-3] - buyruk[(N*2)-4:0];
3'b010: sonuc = buyruk[(N*2)-1:(N*2)-3] & buyruk[(N*2)-4:0];
3'b011: sonuc = buyruk[(N*2)-1:(N*2)-3] | buyruk[(N*2)-4:0];
3'b100: begin
for (i = 0; i <= (N*2)-2; i++)
if (buyruk[i] == buyruk[i+1])
sonuc = {(N+1){1'b1}};
else
sonuc = {(N+1){1'b0}};
end
3'b101: begin
sonuc = {(N+1){1'b0}};
for (a = 0; a < (N*2); a++) begin
if (buyruk[a] == 1)
sonuc = {(N+1){1'b1}};
end
end
3'b110: begin
count = 0;
for (b = 0; b < (N*2); b++) begin
if (buyruk[b] == 1)
count = count + 1;
end
if (count % 2 == 0)
sonuc = {(N+1){1'b1}};
else
sonuc = {(N+1){1'b0}};
end
3'b111: begin
count = 0;
for (c = 0; c < (N*2); c++) begin
if (buyruk[c] == 1)
count = count + 1;
end
if (count % 2 == 0)
sonuc = {(N+1){1'b0}};
else
sonuc = {(N+1){1'b1}};
end
endcase
end
endmodule

81
iverilog/tobb/lab6/bibp.vcd Normal file
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@ -0,0 +1,81 @@
$date
Thu Jan 30 06:13:44 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module bibpTB $end
$var wire 4 ! sonuc [3:0] $end
$var reg 9 " A [8:0] $end
$scope module uut $end
$var wire 9 # buyruk [8:0] $end
$var reg 4 $ sonuc [3:0] $end
$var integer 32 % a [31:0] $end
$var integer 32 & b [31:0] $end
$var integer 32 ' c [31:0] $end
$var integer 32 ( count [31:0] $end
$var integer 32 ) i [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
bx )
bx (
bx '
bx &
bx %
b10 $
b1001 #
b1001 "
b10 !
$end
#5
b11 !
b11 $
b1100001 "
b1100001 #
#10
b100 !
b100 $
b10100101 "
b10100101 #
#15
b111 !
b111 $
b11100011 "
b11100011 #
#20
b1111 !
b1111 $
b101 )
b100111111 "
b100111111 #
#25
b0 !
b0 $
b101 )
b100100001 "
b100100001 #
#30
b1111 !
b1111 $
b110 %
b101100001 "
b101100001 #
#35
b110 &
b10 (
b110100001 "
b110100001 #
#40
b0 !
b0 $
b110 '
b10 (
b111100001 "
b111100001 #
#45

25
iverilog/tobb/lab6/bibpTB.v Normal file
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@ -0,0 +1,25 @@
module bibpTB();
parameter N = 3;
reg [(N*2)+2:0] A;
wire [N:0] sonuc;
bibp #(N) uut (
.buyruk(A),
.sonuc(sonuc)
);
initial begin
$dumpfile("bibp.vcd");
$dumpvars;
A = 9'b000_001_001; #5;
A = 9'b001_100_001; #5;
A = 9'b010_100_101; #5;
A = 9'b011_100_011; #5;
A = 9'b100_111_111; #5;
A = 9'b100_100_001; #5;
A = 9'b101_100_001; #5;
A = 9'b110_100_001; #5;
A = 9'b111_100_001; #5;
end
endmodule

341
iverilog/tobb/lab7/bib3A Normal file
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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55a2c2765ba0 .scope module, "bib3AdvancedTB" "bib3AdvancedTB" 2 1;
.timescale 0 0;
v0x55a2c2780cc0_0 .var "basla", 0 0;
v0x55a2c2780d80_0 .net "bitti", 0 0, v0x55a2c27805f0_0; 1 drivers
v0x55a2c2780e50_0 .var "buyruk", 8 0;
v0x55a2c2780f50_0 .var "clk", 0 0;
v0x55a2c2781020_0 .var/i "i", 31 0;
v0x55a2c27810c0 .array "memory", 15 0, 8 0;
v0x55a2c2781160_0 .net "sonuc", 3 0, v0x55a2c2780b40_0; 1 drivers
S_0x55a2c2765d30 .scope module, "uut" "bib3Advanced" 2 10, 3 1 0, S_0x55a2c2765ba0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "basla";
.port_info 2 /INPUT 9 "buyruk";
.port_info 3 /OUTPUT 4 "sonuc";
.port_info 4 /OUTPUT 1 "bitti";
v0x55a2c2723c00_0 .var/i "a", 31 0;
v0x55a2c2780470_0 .var/i "b", 31 0;
v0x55a2c2780550_0 .net "basla", 0 0, v0x55a2c2780cc0_0; 1 drivers
v0x55a2c27805f0_0 .var "bitti", 0 0;
v0x55a2c27806b0_0 .net "buyruk", 8 0, v0x55a2c2780e50_0; 1 drivers
v0x55a2c27807e0_0 .var/i "c", 31 0;
v0x55a2c27808c0_0 .net "clk", 0 0, v0x55a2c2780f50_0; 1 drivers
v0x55a2c2780980_0 .var/i "count", 31 0;
v0x55a2c2780a60_0 .var/i "i", 31 0;
v0x55a2c2780b40_0 .var "sonuc", 3 0;
E_0x55a2c275ba20 .event posedge, v0x55a2c27808c0_0;
.scope S_0x55a2c2765d30;
T_0 ;
%wait E_0x55a2c275ba20;
%load/vec4 v0x55a2c2780550_0;
%flag_set/vec4 8;
%jmp/0xz T_0.0, 8;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%load/vec4 v0x55a2c27806b0_0;
%parti/s 3, 6, 4;
%dup/vec4;
%pushi/vec4 0, 0, 3;
%cmp/u;
%jmp/1 T_0.3, 6;
%dup/vec4;
%pushi/vec4 1, 0, 3;
%cmp/u;
%jmp/1 T_0.4, 6;
%dup/vec4;
%pushi/vec4 2, 0, 3;
%cmp/u;
%jmp/1 T_0.5, 6;
%dup/vec4;
%pushi/vec4 3, 0, 3;
%cmp/u;
%jmp/1 T_0.6, 6;
%dup/vec4;
%pushi/vec4 4, 0, 3;
%cmp/u;
%jmp/1 T_0.7, 6;
%dup/vec4;
%pushi/vec4 5, 0, 3;
%cmp/u;
%jmp/1 T_0.8, 6;
%dup/vec4;
%pushi/vec4 6, 0, 3;
%cmp/u;
%jmp/1 T_0.9, 6;
%dup/vec4;
%pushi/vec4 7, 0, 3;
%cmp/u;
%jmp/1 T_0.10, 6;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
%jmp T_0.11;
T_0.3 ;
%load/vec4 v0x55a2c27806b0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55a2c27806b0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%add;
%assign/vec4 v0x55a2c2780b40_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%jmp T_0.11;
T_0.4 ;
%load/vec4 v0x55a2c27806b0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55a2c27806b0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%sub;
%assign/vec4 v0x55a2c2780b40_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%jmp T_0.11;
T_0.5 ;
%load/vec4 v0x55a2c27806b0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55a2c27806b0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%and;
%assign/vec4 v0x55a2c2780b40_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%jmp T_0.11;
T_0.6 ;
%load/vec4 v0x55a2c27806b0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55a2c27806b0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%or;
%assign/vec4 v0x55a2c2780b40_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%jmp T_0.11;
T_0.7 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55a2c2780a60_0, 0, 32;
T_0.12 ;
%load/vec4 v0x55a2c2780a60_0;
%cmpi/s 4, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.13, 5;
%load/vec4 v0x55a2c27806b0_0;
%load/vec4 v0x55a2c2780a60_0;
%part/s 1;
%load/vec4 v0x55a2c27806b0_0;
%load/vec4 v0x55a2c2780a60_0;
%addi 1, 0, 32;
%part/s 1;
%cmp/e;
%jmp/0xz T_0.14, 4;
%pushi/vec4 15, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
%jmp T_0.15;
T_0.14 ;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
T_0.15 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55a2c2780a60_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55a2c2780a60_0, 0, 32;
%jmp T_0.12;
T_0.13 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%jmp T_0.11;
T_0.8 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55a2c2723c00_0, 0, 32;
T_0.16 ;
%load/vec4 v0x55a2c2723c00_0;
%cmpi/s 5, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.17, 5;
%load/vec4 v0x55a2c27806b0_0;
%load/vec4 v0x55a2c2723c00_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.18, 4;
%pushi/vec4 15, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
%jmp T_0.19;
T_0.18 ;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
T_0.19 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55a2c2723c00_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55a2c2723c00_0, 0, 32;
%jmp T_0.16;
T_0.17 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%jmp T_0.11;
T_0.9 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55a2c2780980_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55a2c2780470_0, 0, 32;
T_0.20 ;
%load/vec4 v0x55a2c2780470_0;
%cmpi/s 5, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.21, 5;
%load/vec4 v0x55a2c27806b0_0;
%load/vec4 v0x55a2c2780470_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.22, 4;
%load/vec4 v0x55a2c2780980_0;
%addi 1, 0, 32;
%store/vec4 v0x55a2c2780980_0, 0, 32;
T_0.22 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55a2c2780470_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55a2c2780470_0, 0, 32;
%jmp T_0.20;
T_0.21 ;
%load/vec4 v0x55a2c2780980_0;
%pushi/vec4 2, 0, 32;
%mod/s;
%cmpi/e 0, 0, 32;
%jmp/0xz T_0.24, 4;
%pushi/vec4 15, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
%jmp T_0.25;
T_0.24 ;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
T_0.25 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%jmp T_0.11;
T_0.10 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55a2c2780980_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55a2c27807e0_0, 0, 32;
T_0.26 ;
%load/vec4 v0x55a2c27807e0_0;
%cmpi/s 5, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.27, 5;
%load/vec4 v0x55a2c27806b0_0;
%load/vec4 v0x55a2c27807e0_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.28, 4;
%load/vec4 v0x55a2c2780980_0;
%addi 1, 0, 32;
%store/vec4 v0x55a2c2780980_0, 0, 32;
T_0.28 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55a2c27807e0_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55a2c27807e0_0, 0, 32;
%jmp T_0.26;
T_0.27 ;
%load/vec4 v0x55a2c2780980_0;
%pushi/vec4 2, 0, 32;
%mod/s;
%cmpi/e 0, 0, 32;
%jmp/0xz T_0.30, 4;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
%jmp T_0.31;
T_0.30 ;
%pushi/vec4 15, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
T_0.31 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%jmp T_0.11;
T_0.11 ;
%pop/vec4 1;
%jmp T_0.1;
T_0.0 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
T_0.1 ;
%jmp T_0;
.thread T_0;
.scope S_0x55a2c2765ba0;
T_1 ;
%load/vec4 v0x55a2c2780f50_0;
%inv;
%store/vec4 v0x55a2c2780f50_0, 0, 1;
%delay 5, 0;
%jmp T_1;
.thread T_1;
.scope S_0x55a2c2765ba0;
T_2 ;
%vpi_call 2 25 "$dumpfile", "bib3Advanced.vcd" {0 0 0};
%vpi_call 2 26 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a2c2780f50_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a2c2780cc0_0, 0, 1;
%pushi/vec4 0, 0, 9;
%store/vec4 v0x55a2c2780e50_0, 0, 9;
%vpi_call 2 28 "$readmemb", "memory.mem", v0x55a2c27810c0 {0 0 0};
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a2c2780cc0_0, 0, 1;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55a2c2781020_0, 0, 32;
T_2.0 ;
%load/vec4 v0x55a2c2781020_0;
%cmpi/s 16, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_2.1, 5;
%ix/getv/s 4, v0x55a2c2781020_0;
%load/vec4a v0x55a2c27810c0, 4;
%store/vec4 v0x55a2c2780e50_0, 0, 9;
%delay 10, 0;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55a2c2781020_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55a2c2781020_0, 0, 32;
%jmp T_2.0;
T_2.1 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a2c2780cc0_0, 0, 1;
%delay 10, 0;
%vpi_call 2 36 "$finish" {0 0 0};
%end;
.thread T_2;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"bib3AdvancedTB.v";
"bib3Advanced.v";

81
iverilog/tobb/lab7/bib3Advanced.v Normal file
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// REWRITE !!
module bib3Advanced (
input clk,
input basla,
input [8:0] buyruk,
output reg [3:0] sonuc,
output reg bitti
);
integer i, a, b, c, count;
always@(posedge clk) begin
if(basla) begin
bitti <= 1'b0;
case (buyruk[8:6])
default: begin
sonuc <= 4'b0000;
end
3'b000: begin
sonuc <= buyruk[5:3] + buyruk[2:0];
bitti <= 1'b1;
end
3'b001: begin
sonuc <= buyruk[5:3] - buyruk[2:0];
bitti <= 1'b1;
end
3'b010: begin
sonuc <= buyruk[5:3] & buyruk[2:0];
bitti <= 1'b1;
end
3'b011: begin
sonuc <= buyruk[5:3] | buyruk[2:0];
bitti <= 1'b1;
end
3'b100: begin
for (i = 0; i <= 4; i++) begin
if (buyruk[i] == buyruk[i+1])
sonuc <= 4'b1111;
else
sonuc <= 4'b0000;
end
bitti <= 1'b1;
end
3'b101: begin
for (a = 0; a <= 5; a++) begin
if (buyruk[a] == 1)
sonuc <= 4'b1111;
else
sonuc <= 4'b0000;
end
bitti <= 1'b1;
end
3'b110: begin
count = 0;
for (b = 0; b <= 5; b++) begin
if (buyruk[b] == 1)
count = count + 1;
end
if (count % 2 == 0)
sonuc <= 4'b1111;
else
sonuc <= 4'b0000;
bitti <= 1'b1;
end
3'b111: begin
count = 0;
for (c = 0; c <= 5; c++)
if (buyruk[c] == 1)
count = count + 1;
if (count % 2 == 0)
sonuc <= 4'b0000;
else
sonuc <= 4'b1111;
bitti <= 1'b1;
end
endcase
end
else begin
bitti <= 1'b0;
sonuc <= 4'b0000;
end
end
endmodule

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module bib3AdvancedTB();
reg clk;
reg basla;
reg [8:0] buyruk;
reg [8:0] memory [0:15];
wire [3:0] sonuc;
wire bitti;
bib3Advanced uut (
.clk(clk),
.basla(basla),
.buyruk(buyruk),
.sonuc(sonuc),
.bitti(bitti)
);
always begin
clk = ~clk; #5;
end
integer i;
initial begin
$dumpfile("bib3Advanced.vcd");
$dumpvars;
clk = 0; basla = 0; buyruk = 9'b0_0000_0000;
$readmemb("memory.mem", memory); #10;
basla = 1'b1;
for(i = 0; i <= 16; i++) begin
buyruk = memory[i]; #10;
end
basla = 1'b0; #10;
$finish;
end
endmodule

0
iverilog/tobb/lab7/bib3_gelismis.v Normal file
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16
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@ -0,0 +1,16 @@
000001001
001100001
010100101
011100011
100111111
100100001
101100001
110100001
111100001
000001001
001100001
010100101
011100011
100111111
100100001
101100001

12
iverilog/tobb/lab7/paramBib3Advanced.v Normal file
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@ -0,0 +1,12 @@
module paramBib3Advanced #(parameter N = 3) (
input clk,
input basla,
input [(N*2)+2:0] buyruk,
output reg [N:0] sonuc,
output reg bitti
);
genvar i;
generate
for (i = 0; i < N)
endgenerate

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module selector (
input [3:0] select,
input [7:0] Y,
input [3:0] A, B,
input [2:0] opCodeA,
output [7:0] s0
);
wire [3:0] a0, b0, tempAB, tempYO;
wire [7:0] y0;
wire [2:0] op0;
wire tempsO, temps;
// Select signals for A
and a00 (a0[0], select[0], A[0]);
and a01 (a0[1], select[0], A[1]);
and a02 (a0[2], select[0], A[2]);
and a03 (a0[3], select[0], A[3]);
// Select signals for B
and b00 (b0[0], select[1], B[0]);
and b01 (b0[1], select[1], B[1]);
and b02 (b0[2], select[1], B[2]);
and b03 (b0[3], select[1], B[3]);
// Select signals for Y
and y00 (y0[0], select[2], Y[0]);
and y01 (y0[1], select[2], Y[1]);
and y02 (y0[2], select[2], Y[2]);
and y03 (y0[3], select[2], Y[3]);
and y04 (y0[4], select[2], Y[4]);
and y05 (y0[5], select[2], Y[5]);
and y06 (y0[6], select[2], Y[6]);
and y07 (y0[7], select[2], Y[7]);
// Select signals for opCodeA
and op00 (op0[0], select[3], opCodeA[0]);
and op01 (op0[1], select[3], opCodeA[1]);
and op02 (op0[2], select[3], opCodeA[2]);
// Combine A and B
or or1 (tempAB[0], a0[0], b0[0]);
or or2 (tempAB[1], a0[1], b0[1]);
or or3 (tempAB[2], a0[2], b0[2]);
or or4 (tempAB[3], a0[3], b0[3]);
// Combine Y and opCodeA
or or5 (tempYO[0], y0[0], op0[0]);
or or6 (tempYO[1], y0[1], op0[1]);
or or7 (tempYO[2], y0[2], op0[2]);
or or8 (tempYO[3], y0[3], 1'b0);
// NOR for select logic
nor s01 (tempsO, select[0], select[1]);
nor s02 (temps, tempsO, select[3]);
// Final s0 connections
or or9 (s0[0], tempAB[0], tempYO[0]);
or or10 (s0[1], tempAB[1], tempYO[1]);
or or11 (s0[2], tempAB[2], tempYO[2]);
or or12 (s0[3], tempAB[3], tempYO[3]);
and and13 (s0[4], y0[4], temps);
and and14 (s0[5], y0[5], temps);
and and15 (s0[6], y0[6], temps);
and and16 (s0[7], y0[7], temps);
endmodule

4
project0.2/ALU.v
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@ -2,7 +2,7 @@ module ALU (
input [3:0] A, B, input [3:0] A, B,
input CarryIN, input CarryIN,
input [2:0] opCodeA, input [2:0] opCodeA,
output [11:0] bcd, output [7:0] Y,
output CarryOUT, overflow output CarryOUT, overflow
); );
@ -73,7 +73,7 @@ or o36 (Y[5], 1'b0, wireM[5]);
or o37 (Y[6], 1'b0, wireM[6]); or o37 (Y[6], 1'b0, wireM[6]);
or o38 (Y[7], 1'b0, wireM[7]); or o38 (Y[7], 1'b0, wireM[7]);
BinaryToBCD btod1(.binary(Y), .bcd(bcd)); // WIRE Y BINARY!!!! //BinaryToBCD btod1(.binary(Y), .bcd(bcd)); // WIRE Y BINARY!!!!
endmodule endmodule

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project0.2/divider.v Normal file
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module divider (
input [3:0] D,
input [1:0] d,
output [2:0] R,
output [3:0] Q
);
wire s1,y1,c1;
dividerpu d1 (.A(D[3]), .B(d[0]), .Cin(1'b1), .S(s1), .Y(y1), .COut(c1));
dividerpu d2 (.A(1'b0), .B(d[1]), .Cin(c1), .S(s1), .Y(y1), .COut(c1));

26
project0.2/selectorTB.v Normal file
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module selectorTB();
reg [3:0] select, A, B;
reg [7:0] Y;
reg [2:0] opCodeA;
wire [7:0] s0;
selector uut (
.select(select),
.A(A),
.B(B),
.opCodeA(opCodeA),
.s0(s0)
);
initial begin
$dumpfile("selector.vcd");
$dumpvars;
A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b1111_0000; select = 4'b0010; #5;
A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b1111_0000; select = 4'b0001; #5;
A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b0111_0000; select = 4'b0100; #5;
A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b0111_0000; select = 4'b1000; #5;
$finish;
end
endmodule

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module ALU (
input [3:0] A, B,
input CarryIN,
input [2:0] opCodeA,
output [11:0] bcd,
output CarryOUT, overflow
);
// Supports: ADD[0], SUB[1], MULT[2], AND[4], OR[5], XOR[6]
wire [7:0] opCode8;
wire [3:0] add_Y, sub_Y;
wire [3:0] resultA, resultO, resultX, lUOutput1;
wire [3:0] aUtemp1, aUtemp2, lUOutput2;
wire [3:0] wireY, wireLA;
wire [7:0] opwireM, wireM, Y;
opCode opCd (.A(opCodeA), .opCode(opCode8));
arithmeticUnit aU(.opCode(opCode8[1:0]), .A(A), .B(B), .CarryIN(CarryIN), .add_Y(add_Y), .sub_Y(sub_Y), .CarryOUT(CarryOUT), .overflow(overflow));
logicUnit lU (.opCode(opCode8[6:4]), .A(A), .B(B), .resultA(resultA), .resultO(resultO), .resultX(resultX));
multiplier mU (.A(A), .B(B), .Y(opwireM));
or o01 (lUOutput1[0], resultA[0], resultO[0]);
or o02 (lUOutput1[1], resultA[1], resultO[1]);
or o03 (lUOutput1[2], resultA[2], resultO[2]);
or o04 (lUOutput1[3], resultA[3], resultO[3]);
or o11 (lUOutput2[0], lUOutput1[0], resultX[0]);
or o12 (lUOutput2[1], lUOutput1[1], resultX[1]);
or o13 (lUOutput2[2], lUOutput1[2], resultX[2]);
or o14 (lUOutput2[3], lUOutput1[3], resultX[3]);
and a01 (aUtemp1[0], opCode8[0], add_Y[0]);
and a02 (aUtemp1[1], opCode8[0], add_Y[1]);
and a03 (aUtemp1[2], opCode8[0], add_Y[2]);
and a04 (aUtemp1[3], opCode8[0], add_Y[3]);
and a11 (aUtemp2[0], opCode8[1], sub_Y[0]);
and a12 (aUtemp2[1], opCode8[1], sub_Y[1]);
and a13 (aUtemp2[2], opCode8[1], sub_Y[2]);
and a14 (aUtemp2[3], opCode8[1], sub_Y[3]);
and a21 (wireM[0], opCode8[2], opwireM[0]);
and a22 (wireM[1], opCode8[2], opwireM[1]);
and a23 (wireM[2], opCode8[2], opwireM[2]);
and a24 (wireM[3], opCode8[2], opwireM[3]);
and a25 (wireM[4], opCode8[2], opwireM[4]);
and a26 (wireM[5], opCode8[2], opwireM[5]);
and a27 (wireM[6], opCode8[2], opwireM[6]);
and a28 (wireM[7], opCode8[2], opwireM[7]);
or o21 (wireY[0], aUtemp1[0], aUtemp2[0]);
or o22 (wireY[1], aUtemp1[1], aUtemp2[1]);
or o23 (wireY[2], aUtemp1[2], aUtemp2[2]);
or o24 (wireY[3], aUtemp1[3], aUtemp2[3]);
or o1 (wireLA[0], lUOutput2[0], wireY[0]);
or o2 (wireLA[1], lUOutput2[1], wireY[1]);
or o3 (wireLA[2], lUOutput2[2], wireY[2]);
or o4 (wireLA[3], lUOutput2[3], wireY[3]);
or o31 (Y[0], wireLA[0], wireM[0]);
or o32 (Y[1], wireLA[1], wireM[1]);
or o33 (Y[2], wireLA[2], wireM[2]);
or o34 (Y[3], wireLA[3], wireM[3]);
or o35 (Y[4], 1'b0, wireM[4]);
or o36 (Y[5], 1'b0, wireM[5]);
or o37 (Y[6], 1'b0, wireM[6]);
or o38 (Y[7], 1'b0, wireM[7]);
BinaryToBCD btod1(.binary(Y), .bcd(bcd)); // WIRE Y BINARY!!!!
endmodule

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26
tangTest/ALUtb.v Normal file
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@ -0,0 +1,26 @@
module ALUtb();
reg [3:0] A,B;
reg CarryIN;
reg [2:0] opCodeA;
wire CarryOUT, overflow;
wire [7:0] Y;
ALU uut (
.A(A),
.B(B),
.CarryIN(CarryIN),
.opCodeA(opCodeA),
.CarryOUT(CarryOUT),
.overflow(overflow),
.Y(Y)
);
initial begin
$dumpfile("ALU.vcd");
$dumpvars;
A = 4'b1111; B = 4'b0001; CarryIN = 1'b0; opCodeA = 3'b001; #5;
$finish;
end
endmodule

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module BinaryToBCD (
input [7:0] binary,
output [11:0] bcd
);
wire empty1, empty2;
wire [3:0] dab1, dab2, dab3, dab4, dab5;
and a111 (empty1, 1'b0, 1'b0);
and a000 (empty2, 1'b0, 1'b0);
and a222 (bcd[11], 1'b0, 1'b0);
and a223 (bcd[10], 1'b0, 1'b0);
dabble d1t (.A((empty1)),
.B(binary[7]),
.C(binary[6]),
.D(binary[5]),
.X(dab1[0]),
.Y(dab1[1]),
.Z(dab1[2]),
.E(dab1[3]));
dabble d2u (.A((dab1[1])),
.B(dab1[2]),
.C(dab1[3]),
.D(binary[4]),
.X(dab2[0]),
.Y(dab2[1]),
.Z(dab2[2]),
.E(dab2[3]));
dabble d3v (.A((dab2[1])),
.B(dab2[2]),
.C(dab2[3]),
.D(binary[3]),
.X(dab3[0]),
.Y(dab3[1]),
.Z(dab3[2]),
.E(dab3[3]));
dabble d4w (.A((empty2)),
.B(dab1[0]),
.C(dab2[0]),
.D(dab3[0]),
.X(bcd[9]),
.Y(dab4[1]),
.Z(dab4[2]),
.E(dab4[3]));
dabble d5x (.A((dab3[1])),
.B(dab3[2]),
.C(dab3[3]),
.D(binary[2]),
.X(dab5[0]),
.Y(dab5[1]),
.Z(dab5[2]),
.E(dab5[3]));
dabble d6y (.A((dab4[1])),
.B(dab4[2]),
.C(dab4[3]),
.D(dab5[0]),
.X(bcd[8]),
.Y(bcd[7]),
.Z(bcd[6]),
.E(bcd[5]));
dabble d7z (.A((dab5[1])),
.B(dab5[2]),
.C(dab5[3]),
.D(binary[1]),
.X(bcd[4]),
.Y(bcd[3]),
.Z(bcd[2]),
.E(bcd[1]));
or o1 (bcd[0], binary[0], 1'b0);
endmodule

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module addition (
input [3:0] A, B,
input CarryIN,
output [3:0] Y,
output CarryOUT,
output overflow
);
wire [2:0] Carry4;
fulladder f0(.A(A[0]), .B(B[0]), .Carry(CarryIN), .Sum(Y[0]), .CarryO(Carry4[0]));
fulladder f1(.A(A[1]), .B(B[1]), .Carry(Carry4[0]), .Sum(Y[1]), .CarryO(Carry4[1]));
fulladder f2(.A(A[2]), .B(B[2]), .Carry(Carry4[1]), .Sum(Y[2]), .CarryO(Carry4[2]));
fulladder f3(.A(A[3]), .B(B[3]), .Carry(Carry4[2]), .Sum(Y[3]), .CarryO(CarryOUT));
//overflowDetect od1 (.opCode(2'b01), .A(A), .B(B), .Y(Y), .CarryOUT(CarryOUT), .overflowDetect(overflow)); (KULLANILMAYACAK!!!!)
xor ov1 (overflow, Carry4[2], CarryOUT);
endmodule

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tangTest/arithmeticUnit.v Normal file
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module arithmeticUnit (
input [1:0] opCode,
input [3:0] A, B,
input CarryIN,
output [3:0] add_Y, sub_Y,
output CarryOUT,
output overflow
);
wire [3:0] addY, subY;
wire CarryOUTADD, CarryOUTSUB, tempCAdd, tempCSub, tempoverflow;
addition a1(.A(A), .B(B), .CarryIN(CarryIN), .Y(addY), .CarryOUT(CarryOUTADD), .overflow(tempoverflow));
subtraction s1(.A(A), .B(B), .BorrowIN(CarryIN), .Y(subY), .BorrowOUT(CarryOUTSUB));
and add1 (add_Y[0], opCode[0], addY[0]);
and add2 (add_Y[1], opCode[0], addY[1]);
and add3 (add_Y[2], opCode[0], addY[2]);
and add4 (add_Y[3], opCode[0], addY[3]);
and sub1 (sub_Y[0], opCode[1], subY[0]);
and sub2 (sub_Y[1], opCode[1], subY[1]);
and sub3 (sub_Y[2], opCode[1], subY[2]);
and sub4 (sub_Y[3], opCode[1], subY[3]);
// or or1 (CarryOUT, CarryOUTADD, CarryOUTSUB); (OLD!!!)
and and10 (tempCSub, CarryOUTSUB, opCode[1]);
and and11 (tempCAdd, CarryOUTADD, opCode[0]);
or or4 (CarryOUT, tempCAdd, tempCSub);
and add12 (overflow, opCode[0], tempoverflow);
endmodule

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tangTest/compile.sh Normal file
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#!/bin/bash
# Granting execute permissions to this script (one-time setup)
# chmod +x script_name.sh
# Using Icarus Verilog to compile Verilog files for simulation
iverilog -o top top.v topTB.v ALU.v selector.v BinaryToBCD.v arithmeticUnit.v logicUnit.v multiplier.v opCode.v addition.v dabble.v subtraction.v fulladder.v fullsubtraction.v halfadder.v halfsubtraction.v
# Running the simulation
vvp top

22
tangTest/dabble.v Normal file
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module dabble (
input A, B, C, D,
output X, Y, Z, E
);
wire xor1, nor1, xor2, nor2, nor3, or1;
xor xo1 (xor1, A, D);
nor no1 (nor1, A, B);
xor xo2 (xor2, A, C);
nor no2 (nor2, xor1, xor2);
nor no3 (nor3, nor2, nor1);
buf bu1 (X, nor3);
or o1 (or1, xor1, nor1);
nor no4 (Y, or1, C);
and an1 (Z, or1, xor2);
xor xo3 (E, nor3, D);
endmodule

12
tangTest/fulladder.v Normal file
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module fulladder (
input A, B, Carry,
output Sum, CarryO
);
wire xor1, and1, and2;
halfadder h1(.A(A), .B(B), .Sum(xor1), .Carry(and1));
halfadder h2 (.A(xor1), .B(Carry), .Sum(Sum), .Carry(and2));
or o1 (CarryO, and1, and2);
endmodule

12
tangTest/fullsubtraction.v Normal file
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module fullsubtraction (
input A, B, BorrowIN,
output Difference, BorrowOut
);
wire tempD, tempB1, tempB2;
halfsubtraction hf1(.A(A), .B(B), .Difference(tempD), .Borrow(tempB1));
halfsubtraction hf2(.A(tempD), .B(BorrowIN), .Difference(Difference), .Borrow(tempB2));
or o1 (BorrowOut, tempB1, tempB2);
endmodule

9
tangTest/halfadder.v Normal file
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module halfadder (
input A, B,
output Sum, Carry
);
and a1 (Carry, A, B);
xor xo1 (Sum, A, B);
endmodule

12
tangTest/halfsubtraction.v Normal file
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module halfsubtraction (
input A, B,
output Difference, Borrow
);
wire notA;
xor xo1 (Difference, A, B);
not a1 (notA, A);
and an1 (Borrow, notA, B);
endmodule

39
tangTest/logicUnit.v Normal file
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module logicUnit (
input [2:0] opCode,
input [3:0] A, B,
output [3:0] resultA, resultO, resultX
);
wire [3:0] and1, or1, xor1;
and a01 (and1[0], A[0], B[0]);
and a02 (and1[1], A[1], B[1]);
and a03 (and1[2], A[2], B[2]);
and a04 (and1[3], A[3], B[3]);
or o01 (or1[0], A[0], B[0]);
or o02 (or1[1], A[1], B[1]);
or o03 (or1[2], A[2], B[2]);
or o04 (or1[3], A[3], B[3]);
xor xor01 (xor1[0], A[0], B[0]);
xor xor02 (xor1[1], A[1], B[1]);
xor xor03 (xor1[2], A[2], B[2]);
xor xor04 (xor1[3], A[3], B[3]);
and a_o1 (resultA[0], opCode[0], and1[0]);
and a_o2 (resultA[1], opCode[0], and1[1]);
and a_o3 (resultA[2], opCode[0], and1[2]);
and a_o4 (resultA[3], opCode[0], and1[3]);
and o_o1 (resultO[0], opCode[1], or1[0]);
and o_o2 (resultO[1], opCode[1], or1[1]);
and o_o3 (resultO[2], opCode[1], or1[2]);
and o_o4 (resultO[3], opCode[1], or1[3]);
and x_o1 (resultX[0], opCode[2], xor1[0]);
and x_o2 (resultX[1], opCode[2], xor1[1]);
and x_o3 (resultX[2], opCode[2], xor1[2]);
and x_o4 (resultX[3], opCode[2], xor1[3]);
endmodule

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tangTest/mult Normal file
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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x560808805dd0 .scope module, "multTB" "multTB" 2 1;
.timescale 0 0;
v0x56080883b1b0_0 .var "A", 3 0;
v0x56080883b2a0_0 .var "B", 3 0;
v0x56080883b370_0 .net "Y", 7 0, L_0x560808846dd0; 1 drivers
S_0x560808804330 .scope module, "uut" "multiplier" 2 6, 3 1 0, S_0x560808805dd0;
.timescale 0 0;
.port_info 0 /INPUT 4 "A";
.port_info 1 /INPUT 4 "B";
.port_info 2 /OUTPUT 8 "Y";
L_0x56080883b470 .functor AND 1, L_0x56080883b570, L_0x56080883b660, C4<1>, C4<1>;
L_0x56080883b7a0 .functor AND 1, L_0x56080883b810, L_0x56080883b900, C4<1>, C4<1>;
L_0x56080883ba20 .functor AND 1, L_0x56080883ba90, L_0x56080883bb80, C4<1>, C4<1>;
L_0x56080883bc60 .functor AND 1, L_0x56080883bd00, L_0x56080883bda0, C4<1>, C4<1>;
L_0x7f3ea6b4d018 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
L_0x56080883c0c0 .functor NOT 1, L_0x7f3ea6b4d018, C4<0>, C4<0>, C4<0>;
L_0x56080883c1d0 .functor AND 1, L_0x56080883c280, L_0x56080883c3d0, C4<1>, C4<1>;
L_0x56080883c470 .functor AND 1, L_0x56080883c4e0, L_0x56080883c640, C4<1>, C4<1>;
L_0x56080883c730 .functor AND 1, L_0x56080883c7f0, L_0x56080883c960, C4<1>, C4<1>;
L_0x56080883c5d0 .functor AND 1, L_0x56080883cd10, L_0x56080883ce00, C4<1>, C4<1>;
L_0x56080883ef10 .functor AND 1, L_0x56080883f360, L_0x56080883cef0, C4<1>, C4<1>;
L_0x56080883f4b0 .functor AND 1, L_0x56080883f520, L_0x56080883f680, C4<1>, C4<1>;
L_0x56080883f720 .functor AND 1, L_0x56080883f800, L_0x56080883f9c0, C4<1>, C4<1>;
L_0x56080883fd70 .functor AND 1, L_0x56080883fe30, L_0x56080883ff20, C4<1>, C4<1>;
L_0x5608088423d0 .functor AND 1, L_0x5608088429c0, L_0x560808842a60, C4<1>, C4<1>;
L_0x56080883f790 .functor AND 1, L_0x560808842c10, L_0x560808842cb0, C4<1>, C4<1>;
L_0x560808842ec0 .functor AND 1, L_0x560808842fc0, L_0x5608088430b0, C4<1>, C4<1>;
L_0x5608088435d0 .functor AND 1, L_0x560808843690, L_0x5608088438c0, C4<1>, C4<1>;
L_0x7f3ea6b4d138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x560808845900 .functor OR 1, L_0x560808845f60, L_0x7f3ea6b4d138, C4<0>, C4<0>;
L_0x7f3ea6b4d180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x560808846160 .functor OR 1, L_0x5608088461d0, L_0x7f3ea6b4d180, C4<0>, C4<0>;
L_0x7f3ea6b4d1c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x560808846310 .functor OR 1, L_0x560808845ec0, L_0x7f3ea6b4d1c8, C4<0>, C4<0>;
L_0x7f3ea6b4d210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x560808846690 .functor OR 1, L_0x560808846700, L_0x7f3ea6b4d210, C4<0>, C4<0>;
L_0x7f3ea6b4d258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x560808846840 .functor OR 1, L_0x560808846970, L_0x7f3ea6b4d258, C4<0>, C4<0>;
L_0x7f3ea6b4d2a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x560808846c70 .functor OR 1, L_0x560808846ce0, L_0x7f3ea6b4d2a0, C4<0>, C4<0>;
L_0x7f3ea6b4d2e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x5608088472d0 .functor OR 1, L_0x560808847460, L_0x7f3ea6b4d2e8, C4<0>, C4<0>;
v0x560808836240_0 .net "A", 3 0, v0x56080883b1b0_0; 1 drivers
v0x560808836340_0 .net "B", 3 0, v0x56080883b2a0_0; 1 drivers
v0x560808836420_0 .net "S0", 4 0, L_0x56080883f1d0; 1 drivers
v0x5608088364e0_0 .net "S1", 4 0, L_0x560808842710; 1 drivers
v0x5608088365c0_0 .net "S2", 4 0, L_0x560808845d90; 1 drivers
v0x5608088366f0_0 .net "Y", 7 0, L_0x560808846dd0; alias, 1 drivers
v0x5608088367d0_0 .net *"_ivl_1", 0 0, L_0x56080883b470; 1 drivers
v0x5608088368b0_0 .net *"_ivl_10", 0 0, L_0x56080883b810; 1 drivers
v0x560808836990_0 .net *"_ivl_101", 0 0, L_0x560808842a60; 1 drivers
v0x560808836a70_0 .net *"_ivl_102", 0 0, L_0x56080883f790; 1 drivers
v0x560808836b50_0 .net *"_ivl_105", 0 0, L_0x560808842c10; 1 drivers
v0x560808836c30_0 .net *"_ivl_107", 0 0, L_0x560808842cb0; 1 drivers
v0x560808836d10_0 .net *"_ivl_108", 0 0, L_0x560808842ec0; 1 drivers
v0x560808836df0_0 .net *"_ivl_111", 0 0, L_0x560808842fc0; 1 drivers
v0x560808836ed0_0 .net *"_ivl_113", 0 0, L_0x5608088430b0; 1 drivers
v0x560808836fb0_0 .net *"_ivl_114", 0 0, L_0x5608088435d0; 1 drivers
v0x560808837090_0 .net *"_ivl_118", 0 0, L_0x560808843690; 1 drivers
v0x560808837170_0 .net *"_ivl_12", 0 0, L_0x56080883b900; 1 drivers
v0x560808837250_0 .net *"_ivl_120", 0 0, L_0x5608088438c0; 1 drivers
v0x560808837330_0 .net *"_ivl_13", 0 0, L_0x56080883ba20; 1 drivers
v0x560808837410_0 .net *"_ivl_130", 0 0, L_0x560808845900; 1 drivers
v0x5608088374f0_0 .net *"_ivl_133", 0 0, L_0x560808845f60; 1 drivers
v0x5608088375d0_0 .net/2u *"_ivl_134", 0 0, L_0x7f3ea6b4d138; 1 drivers
v0x5608088376b0_0 .net *"_ivl_136", 0 0, L_0x560808846160; 1 drivers
v0x560808837790_0 .net *"_ivl_139", 0 0, L_0x5608088461d0; 1 drivers
v0x560808837870_0 .net/2u *"_ivl_140", 0 0, L_0x7f3ea6b4d180; 1 drivers
v0x560808837950_0 .net *"_ivl_142", 0 0, L_0x560808846310; 1 drivers
v0x560808837a30_0 .net *"_ivl_145", 0 0, L_0x560808845ec0; 1 drivers
v0x560808837b10_0 .net/2u *"_ivl_146", 0 0, L_0x7f3ea6b4d1c8; 1 drivers
v0x560808837bf0_0 .net *"_ivl_148", 0 0, L_0x560808846690; 1 drivers
v0x560808837cd0_0 .net *"_ivl_151", 0 0, L_0x560808846700; 1 drivers
v0x560808837db0_0 .net/2u *"_ivl_152", 0 0, L_0x7f3ea6b4d210; 1 drivers
v0x560808837e90_0 .net *"_ivl_154", 0 0, L_0x560808846840; 1 drivers
v0x560808838180_0 .net *"_ivl_157", 0 0, L_0x560808846970; 1 drivers
v0x560808838260_0 .net/2u *"_ivl_158", 0 0, L_0x7f3ea6b4d258; 1 drivers
v0x560808838340_0 .net *"_ivl_16", 0 0, L_0x56080883ba90; 1 drivers
v0x560808838420_0 .net *"_ivl_160", 0 0, L_0x560808846c70; 1 drivers
v0x560808838500_0 .net *"_ivl_163", 0 0, L_0x560808846ce0; 1 drivers
v0x5608088385e0_0 .net/2u *"_ivl_164", 0 0, L_0x7f3ea6b4d2a0; 1 drivers
v0x5608088386c0_0 .net *"_ivl_166", 0 0, L_0x5608088472d0; 1 drivers
v0x5608088387a0_0 .net *"_ivl_170", 0 0, L_0x560808847460; 1 drivers
v0x560808838880_0 .net/2u *"_ivl_171", 0 0, L_0x7f3ea6b4d2e8; 1 drivers
v0x560808838960_0 .net *"_ivl_18", 0 0, L_0x56080883bb80; 1 drivers
v0x560808838a40_0 .net *"_ivl_19", 0 0, L_0x56080883bc60; 1 drivers
v0x560808838b20_0 .net *"_ivl_22", 0 0, L_0x56080883bd00; 1 drivers
v0x560808838c00_0 .net *"_ivl_24", 0 0, L_0x56080883bda0; 1 drivers
v0x560808838ce0_0 .net *"_ivl_25", 0 0, L_0x56080883c0c0; 1 drivers
v0x560808838dc0_0 .net/2u *"_ivl_28", 0 0, L_0x7f3ea6b4d018; 1 drivers
v0x560808838ea0_0 .net *"_ivl_30", 0 0, L_0x56080883c1d0; 1 drivers
v0x560808838f80_0 .net *"_ivl_33", 0 0, L_0x56080883c280; 1 drivers
v0x560808839060_0 .net *"_ivl_35", 0 0, L_0x56080883c3d0; 1 drivers
v0x560808839140_0 .net *"_ivl_36", 0 0, L_0x56080883c470; 1 drivers
v0x560808839220_0 .net *"_ivl_39", 0 0, L_0x56080883c4e0; 1 drivers
v0x560808839300_0 .net *"_ivl_4", 0 0, L_0x56080883b570; 1 drivers
v0x5608088393e0_0 .net *"_ivl_41", 0 0, L_0x56080883c640; 1 drivers
v0x5608088394c0_0 .net *"_ivl_42", 0 0, L_0x56080883c730; 1 drivers
v0x5608088395a0_0 .net *"_ivl_45", 0 0, L_0x56080883c7f0; 1 drivers
v0x560808839680_0 .net *"_ivl_47", 0 0, L_0x56080883c960; 1 drivers
v0x560808839760_0 .net *"_ivl_48", 0 0, L_0x56080883c5d0; 1 drivers
v0x560808839840_0 .net *"_ivl_52", 0 0, L_0x56080883cd10; 1 drivers
v0x560808839920_0 .net *"_ivl_54", 0 0, L_0x56080883ce00; 1 drivers
v0x560808839a00_0 .net *"_ivl_6", 0 0, L_0x56080883b660; 1 drivers
v0x560808839ae0_0 .net *"_ivl_62", 0 0, L_0x56080883ef10; 1 drivers
v0x560808839bc0_0 .net *"_ivl_65", 0 0, L_0x56080883f360; 1 drivers
v0x560808839ca0_0 .net *"_ivl_67", 0 0, L_0x56080883cef0; 1 drivers
v0x56080883a190_0 .net *"_ivl_68", 0 0, L_0x56080883f4b0; 1 drivers
v0x56080883a270_0 .net *"_ivl_7", 0 0, L_0x56080883b7a0; 1 drivers
v0x56080883a350_0 .net *"_ivl_71", 0 0, L_0x56080883f520; 1 drivers
v0x56080883a430_0 .net *"_ivl_73", 0 0, L_0x56080883f680; 1 drivers
v0x56080883a510_0 .net *"_ivl_74", 0 0, L_0x56080883f720; 1 drivers
v0x56080883a5f0_0 .net *"_ivl_77", 0 0, L_0x56080883f800; 1 drivers
v0x56080883a6d0_0 .net *"_ivl_79", 0 0, L_0x56080883f9c0; 1 drivers
v0x56080883a7b0_0 .net *"_ivl_80", 0 0, L_0x56080883fd70; 1 drivers
v0x56080883a890_0 .net *"_ivl_84", 0 0, L_0x56080883fe30; 1 drivers
v0x56080883a970_0 .net *"_ivl_86", 0 0, L_0x56080883ff20; 1 drivers
v0x56080883aa50_0 .net *"_ivl_96", 0 0, L_0x5608088423d0; 1 drivers
v0x56080883ab30_0 .net *"_ivl_99", 0 0, L_0x5608088429c0; 1 drivers
v0x56080883ac10_0 .net "a0", 3 0, L_0x56080883ca50; 1 drivers
v0x56080883acd0_0 .net "a1", 3 0, L_0x56080883fab0; 1 drivers
v0x56080883ada0_0 .net "a2", 3 0, L_0x560808842da0; 1 drivers
v0x56080883ae70_0 .net "b0", 3 0, L_0x56080883bee0; 1 drivers
v0x56080883af40_0 .net "overflow0", 0 0, L_0x56080883f020; 1 drivers
v0x56080883b010_0 .net "overflow1", 0 0, L_0x5608088424e0; 1 drivers
v0x56080883b0e0_0 .net "overflow2", 0 0, L_0x560808845a10; 1 drivers
L_0x56080883b570 .part v0x56080883b1b0_0, 0, 1;
L_0x56080883b660 .part v0x56080883b2a0_0, 0, 1;
L_0x56080883b810 .part v0x56080883b1b0_0, 1, 1;
L_0x56080883b900 .part v0x56080883b2a0_0, 0, 1;
L_0x56080883ba90 .part v0x56080883b1b0_0, 2, 1;
L_0x56080883bb80 .part v0x56080883b2a0_0, 0, 1;
L_0x56080883bd00 .part v0x56080883b1b0_0, 3, 1;
L_0x56080883bda0 .part v0x56080883b2a0_0, 0, 1;
L_0x56080883bee0 .concat8 [ 1 1 1 1], L_0x56080883b7a0, L_0x56080883ba20, L_0x56080883bc60, L_0x56080883c0c0;
L_0x56080883c280 .part v0x56080883b1b0_0, 0, 1;
L_0x56080883c3d0 .part v0x56080883b2a0_0, 1, 1;
L_0x56080883c4e0 .part v0x56080883b1b0_0, 1, 1;
L_0x56080883c640 .part v0x56080883b2a0_0, 1, 1;
L_0x56080883c7f0 .part v0x56080883b1b0_0, 2, 1;
L_0x56080883c960 .part v0x56080883b2a0_0, 1, 1;
L_0x56080883ca50 .concat8 [ 1 1 1 1], L_0x56080883c1d0, L_0x56080883c470, L_0x56080883c730, L_0x56080883c5d0;
L_0x56080883cd10 .part v0x56080883b1b0_0, 3, 1;
L_0x56080883ce00 .part v0x56080883b2a0_0, 1, 1;
L_0x56080883f1d0 .concat8 [ 4 1 0 0], L_0x56080883ef80, L_0x56080883e990;
L_0x56080883f360 .part v0x56080883b1b0_0, 0, 1;
L_0x56080883cef0 .part v0x56080883b2a0_0, 2, 1;
L_0x56080883f520 .part v0x56080883b1b0_0, 1, 1;
L_0x56080883f680 .part v0x56080883b2a0_0, 2, 1;
L_0x56080883f800 .part v0x56080883b1b0_0, 2, 1;
L_0x56080883f9c0 .part v0x56080883b2a0_0, 2, 1;
L_0x56080883fab0 .concat8 [ 1 1 1 1], L_0x56080883ef10, L_0x56080883f4b0, L_0x56080883f720, L_0x56080883fd70;
L_0x56080883fe30 .part v0x56080883b1b0_0, 3, 1;
L_0x56080883ff20 .part v0x56080883b2a0_0, 2, 1;
L_0x560808842670 .part L_0x56080883f1d0, 1, 4;
L_0x560808842710 .concat8 [ 4 1 0 0], L_0x560808842440, L_0x560808841dc0;
L_0x5608088429c0 .part v0x56080883b1b0_0, 0, 1;
L_0x560808842a60 .part v0x56080883b2a0_0, 3, 1;
L_0x560808842c10 .part v0x56080883b1b0_0, 1, 1;
L_0x560808842cb0 .part v0x56080883b2a0_0, 3, 1;
L_0x560808842fc0 .part v0x56080883b1b0_0, 2, 1;
L_0x5608088430b0 .part v0x56080883b2a0_0, 3, 1;
L_0x560808842da0 .concat8 [ 1 1 1 1], L_0x5608088423d0, L_0x56080883f790, L_0x560808842ec0, L_0x5608088435d0;
L_0x560808843690 .part v0x56080883b1b0_0, 3, 1;
L_0x5608088438c0 .part v0x56080883b2a0_0, 3, 1;
L_0x560808845ba0 .part L_0x560808842710, 1, 4;
L_0x560808845d90 .concat8 [ 4 1 0 0], L_0x560808845970, L_0x560808845330;
L_0x560808845f60 .part L_0x56080883f1d0, 0, 1;
L_0x5608088461d0 .part L_0x560808842710, 0, 1;
L_0x560808845ec0 .part L_0x560808845d90, 0, 1;
L_0x560808846700 .part L_0x560808845d90, 1, 1;
L_0x560808846970 .part L_0x560808845d90, 2, 1;
L_0x560808846ce0 .part L_0x560808845d90, 3, 1;
LS_0x560808846dd0_0_0 .concat8 [ 1 1 1 1], L_0x56080883b470, L_0x560808845900, L_0x560808846160, L_0x560808846310;
LS_0x560808846dd0_0_4 .concat8 [ 1 1 1 1], L_0x560808846690, L_0x560808846840, L_0x560808846c70, L_0x5608088472d0;
L_0x560808846dd0 .concat8 [ 4 4 0 0], LS_0x560808846dd0_0_0, LS_0x560808846dd0_0_4;
L_0x560808847460 .part L_0x560808845d90, 4, 1;
S_0x5608087fbca0 .scope module, "add0" "addition" 3 26, 4 1 0, S_0x560808804330;
.timescale 0 0;
.port_info 0 /INPUT 4 "A";
.port_info 1 /INPUT 4 "B";
.port_info 2 /INPUT 1 "CarryIN";
.port_info 3 /OUTPUT 4 "Y";
.port_info 4 /OUTPUT 1 "CarryOUT";
.port_info 5 /OUTPUT 1 "overflow";
L_0x56080883f020 .functor XOR 1, L_0x56080883f090, L_0x56080883e990, C4<0>, C4<0>;
v0x560808829b90_0 .net "A", 3 0, L_0x56080883ca50; alias, 1 drivers
v0x560808829c70_0 .net "B", 3 0, L_0x56080883bee0; alias, 1 drivers
v0x560808829d50_0 .net "Carry4", 2 0, L_0x56080883e400; 1 drivers
L_0x7f3ea6b4d060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x560808829e10_0 .net "CarryIN", 0 0, L_0x7f3ea6b4d060; 1 drivers
v0x560808829f00_0 .net "CarryOUT", 0 0, L_0x56080883e990; 1 drivers
v0x560808829ff0_0 .net "Y", 3 0, L_0x56080883ef80; 1 drivers
v0x56080882a0b0_0 .net *"_ivl_39", 0 0, L_0x56080883f090; 1 drivers
v0x56080882a190_0 .net "overflow", 0 0, L_0x56080883f020; alias, 1 drivers
L_0x56080883d300 .part L_0x56080883ca50, 0, 1;
L_0x56080883d3a0 .part L_0x56080883bee0, 0, 1;
L_0x56080883d830 .part L_0x56080883ca50, 1, 1;
L_0x56080883d9f0 .part L_0x56080883bee0, 1, 1;
L_0x56080883dbb0 .part L_0x56080883e400, 0, 1;
L_0x56080883dfe0 .part L_0x56080883ca50, 2, 1;
L_0x56080883e150 .part L_0x56080883bee0, 2, 1;
L_0x56080883e280 .part L_0x56080883e400, 1, 1;
L_0x56080883e400 .concat8 [ 1 1 1 0], L_0x56080883d290, L_0x56080883d7c0, L_0x56080883df50;
L_0x56080883ea90 .part L_0x56080883ca50, 3, 1;
L_0x56080883ec20 .part L_0x56080883bee0, 3, 1;
L_0x56080883ed50 .part L_0x56080883e400, 2, 1;
L_0x56080883ef80 .concat8 [ 1 1 1 1], L_0x56080883d220, L_0x56080883d700, L_0x56080883dec0, L_0x56080883e8b0;
L_0x56080883f090 .part L_0x56080883e400, 2, 1;
S_0x5608087fa200 .scope module, "f0" "fulladder" 4 11, 5 1 0, S_0x5608087fbca0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x56080883d290 .functor OR 1, L_0x56080883cf90, L_0x56080883d160, C4<0>, C4<0>;
v0x560808825840_0 .net "A", 0 0, L_0x56080883d300; 1 drivers
v0x560808825900_0 .net "B", 0 0, L_0x56080883d3a0; 1 drivers
v0x5608088259d0_0 .net "Carry", 0 0, L_0x7f3ea6b4d060; alias, 1 drivers
v0x560808825ad0_0 .net "CarryO", 0 0, L_0x56080883d290; 1 drivers
v0x560808825b70_0 .net "Sum", 0 0, L_0x56080883d220; 1 drivers
v0x560808825c60_0 .net "and1", 0 0, L_0x56080883cf90; 1 drivers
v0x560808825d30_0 .net "and2", 0 0, L_0x56080883d160; 1 drivers
v0x560808825e00_0 .net "xor1", 0 0, L_0x56080883d0f0; 1 drivers
S_0x5608087f1eb0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x5608087fa200;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x56080883cf90 .functor AND 1, L_0x56080883d300, L_0x56080883d3a0, C4<1>, C4<1>;
L_0x56080883d0f0 .functor XOR 1, L_0x56080883d300, L_0x56080883d3a0, C4<0>, C4<0>;
v0x56080880a2e0_0 .net "A", 0 0, L_0x56080883d300; alias, 1 drivers
v0x560808809740_0 .net "B", 0 0, L_0x56080883d3a0; alias, 1 drivers
v0x560808808a00_0 .net "Carry", 0 0, L_0x56080883cf90; alias, 1 drivers
v0x56080878a680_0 .net "Sum", 0 0, L_0x56080883d0f0; alias, 1 drivers
S_0x5608088252c0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x5608087fa200;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x56080883d160 .functor AND 1, L_0x56080883d0f0, L_0x7f3ea6b4d060, C4<1>, C4<1>;
L_0x56080883d220 .functor XOR 1, L_0x56080883d0f0, L_0x7f3ea6b4d060, C4<0>, C4<0>;
v0x5608088254c0_0 .net "A", 0 0, L_0x56080883d0f0; alias, 1 drivers
v0x560808825560_0 .net "B", 0 0, L_0x7f3ea6b4d060; alias, 1 drivers
v0x560808825600_0 .net "Carry", 0 0, L_0x56080883d160; alias, 1 drivers
v0x5608088256d0_0 .net "Sum", 0 0, L_0x56080883d220; alias, 1 drivers
S_0x560808825ef0 .scope module, "f1" "fulladder" 4 12, 5 1 0, S_0x5608087fbca0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x56080883d7c0 .functor OR 1, L_0x56080883d4d0, L_0x56080883d5b0, C4<0>, C4<0>;
v0x560808826c70_0 .net "A", 0 0, L_0x56080883d830; 1 drivers
v0x560808826d30_0 .net "B", 0 0, L_0x56080883d9f0; 1 drivers
v0x560808826e00_0 .net "Carry", 0 0, L_0x56080883dbb0; 1 drivers
v0x560808826f00_0 .net "CarryO", 0 0, L_0x56080883d7c0; 1 drivers
v0x560808826fa0_0 .net "Sum", 0 0, L_0x56080883d700; 1 drivers
v0x560808827090_0 .net "and1", 0 0, L_0x56080883d4d0; 1 drivers
v0x560808827160_0 .net "and2", 0 0, L_0x56080883d5b0; 1 drivers
v0x560808827230_0 .net "xor1", 0 0, L_0x56080883d540; 1 drivers
S_0x5608088260d0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808825ef0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x56080883d4d0 .functor AND 1, L_0x56080883d830, L_0x56080883d9f0, C4<1>, C4<1>;
L_0x56080883d540 .functor XOR 1, L_0x56080883d830, L_0x56080883d9f0, C4<0>, C4<0>;
v0x5608088262e0_0 .net "A", 0 0, L_0x56080883d830; alias, 1 drivers
v0x5608088263c0_0 .net "B", 0 0, L_0x56080883d9f0; alias, 1 drivers
v0x560808826480_0 .net "Carry", 0 0, L_0x56080883d4d0; alias, 1 drivers
v0x560808826550_0 .net "Sum", 0 0, L_0x56080883d540; alias, 1 drivers
S_0x5608088266c0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808825ef0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x56080883d5b0 .functor AND 1, L_0x56080883d540, L_0x56080883dbb0, C4<1>, C4<1>;
L_0x56080883d700 .functor XOR 1, L_0x56080883d540, L_0x56080883dbb0, C4<0>, C4<0>;
v0x5608088268c0_0 .net "A", 0 0, L_0x56080883d540; alias, 1 drivers
v0x560808826990_0 .net "B", 0 0, L_0x56080883dbb0; alias, 1 drivers
v0x560808826a30_0 .net "Carry", 0 0, L_0x56080883d5b0; alias, 1 drivers
v0x560808826b00_0 .net "Sum", 0 0, L_0x56080883d700; alias, 1 drivers
S_0x560808827320 .scope module, "f2" "fulladder" 4 13, 5 1 0, S_0x5608087fbca0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x56080883df50 .functor OR 1, L_0x56080883dce0, L_0x56080883ddc0, C4<0>, C4<0>;
v0x5608088280b0_0 .net "A", 0 0, L_0x56080883dfe0; 1 drivers
v0x560808828170_0 .net "B", 0 0, L_0x56080883e150; 1 drivers
v0x560808828240_0 .net "Carry", 0 0, L_0x56080883e280; 1 drivers
v0x560808828340_0 .net "CarryO", 0 0, L_0x56080883df50; 1 drivers
v0x5608088283e0_0 .net "Sum", 0 0, L_0x56080883dec0; 1 drivers
v0x5608088284d0_0 .net "and1", 0 0, L_0x56080883dce0; 1 drivers
v0x5608088285a0_0 .net "and2", 0 0, L_0x56080883ddc0; 1 drivers
v0x560808828670_0 .net "xor1", 0 0, L_0x56080883dd50; 1 drivers
S_0x560808827530 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808827320;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x56080883dce0 .functor AND 1, L_0x56080883dfe0, L_0x56080883e150, C4<1>, C4<1>;
L_0x56080883dd50 .functor XOR 1, L_0x56080883dfe0, L_0x56080883e150, C4<0>, C4<0>;
v0x560808827740_0 .net "A", 0 0, L_0x56080883dfe0; alias, 1 drivers
v0x560808827800_0 .net "B", 0 0, L_0x56080883e150; alias, 1 drivers
v0x5608088278c0_0 .net "Carry", 0 0, L_0x56080883dce0; alias, 1 drivers
v0x560808827990_0 .net "Sum", 0 0, L_0x56080883dd50; alias, 1 drivers
S_0x560808827b00 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808827320;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x56080883ddc0 .functor AND 1, L_0x56080883dd50, L_0x56080883e280, C4<1>, C4<1>;
L_0x56080883dec0 .functor XOR 1, L_0x56080883dd50, L_0x56080883e280, C4<0>, C4<0>;
v0x560808827d00_0 .net "A", 0 0, L_0x56080883dd50; alias, 1 drivers
v0x560808827dd0_0 .net "B", 0 0, L_0x56080883e280; alias, 1 drivers
v0x560808827e70_0 .net "Carry", 0 0, L_0x56080883ddc0; alias, 1 drivers
v0x560808827f40_0 .net "Sum", 0 0, L_0x56080883dec0; alias, 1 drivers
S_0x560808828760 .scope module, "f3" "fulladder" 4 14, 5 1 0, S_0x5608087fbca0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x56080883e990 .functor OR 1, L_0x56080883e4f0, L_0x56080883e720, C4<0>, C4<0>;
v0x5608088294e0_0 .net "A", 0 0, L_0x56080883ea90; 1 drivers
v0x5608088295a0_0 .net "B", 0 0, L_0x56080883ec20; 1 drivers
v0x560808829670_0 .net "Carry", 0 0, L_0x56080883ed50; 1 drivers
v0x560808829770_0 .net "CarryO", 0 0, L_0x56080883e990; alias, 1 drivers
v0x560808829810_0 .net "Sum", 0 0, L_0x56080883e8b0; 1 drivers
v0x560808829900_0 .net "and1", 0 0, L_0x56080883e4f0; 1 drivers
v0x5608088299d0_0 .net "and2", 0 0, L_0x56080883e720; 1 drivers
v0x560808829aa0_0 .net "xor1", 0 0, L_0x56080883e690; 1 drivers
S_0x560808828940 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808828760;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x56080883e4f0 .functor AND 1, L_0x56080883ea90, L_0x56080883ec20, C4<1>, C4<1>;
L_0x56080883e690 .functor XOR 1, L_0x56080883ea90, L_0x56080883ec20, C4<0>, C4<0>;
v0x560808828b50_0 .net "A", 0 0, L_0x56080883ea90; alias, 1 drivers
v0x560808828c30_0 .net "B", 0 0, L_0x56080883ec20; alias, 1 drivers
v0x560808828cf0_0 .net "Carry", 0 0, L_0x56080883e4f0; alias, 1 drivers
v0x560808828dc0_0 .net "Sum", 0 0, L_0x56080883e690; alias, 1 drivers
S_0x560808828f30 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808828760;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x56080883e720 .functor AND 1, L_0x56080883e690, L_0x56080883ed50, C4<1>, C4<1>;
L_0x56080883e8b0 .functor XOR 1, L_0x56080883e690, L_0x56080883ed50, C4<0>, C4<0>;
v0x560808829130_0 .net "A", 0 0, L_0x56080883e690; alias, 1 drivers
v0x560808829200_0 .net "B", 0 0, L_0x56080883ed50; alias, 1 drivers
v0x5608088292a0_0 .net "Carry", 0 0, L_0x56080883e720; alias, 1 drivers
v0x560808829370_0 .net "Sum", 0 0, L_0x56080883e8b0; alias, 1 drivers
S_0x56080882a310 .scope module, "add1" "addition" 3 42, 4 1 0, S_0x560808804330;
.timescale 0 0;
.port_info 0 /INPUT 4 "A";
.port_info 1 /INPUT 4 "B";
.port_info 2 /INPUT 1 "CarryIN";
.port_info 3 /OUTPUT 4 "Y";
.port_info 4 /OUTPUT 1 "CarryOUT";
.port_info 5 /OUTPUT 1 "overflow";
L_0x5608088424e0 .functor XOR 1, L_0x560808842550, L_0x560808841dc0, C4<0>, C4<0>;
v0x56080882fa20_0 .net "A", 3 0, L_0x56080883fab0; alias, 1 drivers
v0x56080882fb00_0 .net "B", 3 0, L_0x560808842670; 1 drivers
v0x56080882fbe0_0 .net "Carry4", 2 0, L_0x560808841830; 1 drivers
L_0x7f3ea6b4d0a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x56080882fca0_0 .net "CarryIN", 0 0, L_0x7f3ea6b4d0a8; 1 drivers
v0x56080882fd90_0 .net "CarryOUT", 0 0, L_0x560808841dc0; 1 drivers
v0x56080882fe80_0 .net "Y", 3 0, L_0x560808842440; 1 drivers
v0x56080882ff40_0 .net *"_ivl_39", 0 0, L_0x560808842550; 1 drivers
v0x560808830020_0 .net "overflow", 0 0, L_0x5608088424e0; alias, 1 drivers
L_0x560808840590 .part L_0x56080883fab0, 0, 1;
L_0x5608088406c0 .part L_0x560808842670, 0, 1;
L_0x560808840bf0 .part L_0x56080883fab0, 1, 1;
L_0x560808840db0 .part L_0x560808842670, 1, 1;
L_0x560808840ee0 .part L_0x560808841830, 0, 1;
L_0x560808841410 .part L_0x56080883fab0, 2, 1;
L_0x560808841580 .part L_0x560808842670, 2, 1;
L_0x5608088416b0 .part L_0x560808841830, 1, 1;
L_0x560808841830 .concat8 [ 1 1 1 0], L_0x560808840520, L_0x560808840b60, L_0x560808841380;
L_0x560808841ec0 .part L_0x56080883fab0, 3, 1;
L_0x560808842050 .part L_0x560808842670, 3, 1;
L_0x560808842210 .part L_0x560808841830, 2, 1;
L_0x560808842440 .concat8 [ 1 1 1 1], L_0x560808840420, L_0x560808840a80, L_0x5608088412a0, L_0x560808841ce0;
L_0x560808842550 .part L_0x560808841830, 2, 1;
S_0x56080882a5b0 .scope module, "f0" "fulladder" 4 11, 5 1 0, S_0x56080882a310;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x560808840520 .functor OR 1, L_0x560808840100, L_0x5608088402d0, C4<0>, C4<0>;
v0x56080882b430_0 .net "A", 0 0, L_0x560808840590; 1 drivers
v0x56080882b4f0_0 .net "B", 0 0, L_0x5608088406c0; 1 drivers
v0x56080882b5c0_0 .net "Carry", 0 0, L_0x7f3ea6b4d0a8; alias, 1 drivers
v0x56080882b6c0_0 .net "CarryO", 0 0, L_0x560808840520; 1 drivers
v0x56080882b760_0 .net "Sum", 0 0, L_0x560808840420; 1 drivers
v0x56080882b850_0 .net "and1", 0 0, L_0x560808840100; 1 drivers
v0x56080882b920_0 .net "and2", 0 0, L_0x5608088402d0; 1 drivers
v0x56080882b9f0_0 .net "xor1", 0 0, L_0x560808840260; 1 drivers
S_0x56080882a790 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x56080882a5b0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808840100 .functor AND 1, L_0x560808840590, L_0x5608088406c0, C4<1>, C4<1>;
L_0x560808840260 .functor XOR 1, L_0x560808840590, L_0x5608088406c0, C4<0>, C4<0>;
v0x56080882aa30_0 .net "A", 0 0, L_0x560808840590; alias, 1 drivers
v0x56080882ab10_0 .net "B", 0 0, L_0x5608088406c0; alias, 1 drivers
v0x56080882abd0_0 .net "Carry", 0 0, L_0x560808840100; alias, 1 drivers
v0x56080882aca0_0 .net "Sum", 0 0, L_0x560808840260; alias, 1 drivers
S_0x56080882ae10 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x56080882a5b0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x5608088402d0 .functor AND 1, L_0x560808840260, L_0x7f3ea6b4d0a8, C4<1>, C4<1>;
L_0x560808840420 .functor XOR 1, L_0x560808840260, L_0x7f3ea6b4d0a8, C4<0>, C4<0>;
v0x56080882b080_0 .net "A", 0 0, L_0x560808840260; alias, 1 drivers
v0x56080882b150_0 .net "B", 0 0, L_0x7f3ea6b4d0a8; alias, 1 drivers
v0x56080882b1f0_0 .net "Carry", 0 0, L_0x5608088402d0; alias, 1 drivers
v0x56080882b2c0_0 .net "Sum", 0 0, L_0x560808840420; alias, 1 drivers
S_0x56080882bae0 .scope module, "f1" "fulladder" 4 12, 5 1 0, S_0x56080882a310;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x560808840b60 .functor OR 1, L_0x5608088407f0, L_0x5608088408f0, C4<0>, C4<0>;
v0x56080882c940_0 .net "A", 0 0, L_0x560808840bf0; 1 drivers
v0x56080882ca00_0 .net "B", 0 0, L_0x560808840db0; 1 drivers
v0x56080882cad0_0 .net "Carry", 0 0, L_0x560808840ee0; 1 drivers
v0x56080882cbd0_0 .net "CarryO", 0 0, L_0x560808840b60; 1 drivers
v0x56080882cc70_0 .net "Sum", 0 0, L_0x560808840a80; 1 drivers
v0x56080882cd60_0 .net "and1", 0 0, L_0x5608088407f0; 1 drivers
v0x56080882ce30_0 .net "and2", 0 0, L_0x5608088408f0; 1 drivers
v0x56080882cf00_0 .net "xor1", 0 0, L_0x560808840860; 1 drivers
S_0x56080882bcc0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x56080882bae0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x5608088407f0 .functor AND 1, L_0x560808840bf0, L_0x560808840db0, C4<1>, C4<1>;
L_0x560808840860 .functor XOR 1, L_0x560808840bf0, L_0x560808840db0, C4<0>, C4<0>;
v0x56080882bf40_0 .net "A", 0 0, L_0x560808840bf0; alias, 1 drivers
v0x56080882c020_0 .net "B", 0 0, L_0x560808840db0; alias, 1 drivers
v0x56080882c0e0_0 .net "Carry", 0 0, L_0x5608088407f0; alias, 1 drivers
v0x56080882c1b0_0 .net "Sum", 0 0, L_0x560808840860; alias, 1 drivers
S_0x56080882c320 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x56080882bae0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x5608088408f0 .functor AND 1, L_0x560808840860, L_0x560808840ee0, C4<1>, C4<1>;
L_0x560808840a80 .functor XOR 1, L_0x560808840860, L_0x560808840ee0, C4<0>, C4<0>;
v0x56080882c590_0 .net "A", 0 0, L_0x560808840860; alias, 1 drivers
v0x56080882c660_0 .net "B", 0 0, L_0x560808840ee0; alias, 1 drivers
v0x56080882c700_0 .net "Carry", 0 0, L_0x5608088408f0; alias, 1 drivers
v0x56080882c7d0_0 .net "Sum", 0 0, L_0x560808840a80; alias, 1 drivers
S_0x56080882cff0 .scope module, "f2" "fulladder" 4 13, 5 1 0, S_0x56080882a310;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x560808841380 .functor OR 1, L_0x560808841010, L_0x560808841110, C4<0>, C4<0>;
v0x56080882de60_0 .net "A", 0 0, L_0x560808841410; 1 drivers
v0x56080882df20_0 .net "B", 0 0, L_0x560808841580; 1 drivers
v0x56080882dff0_0 .net "Carry", 0 0, L_0x5608088416b0; 1 drivers
v0x56080882e0f0_0 .net "CarryO", 0 0, L_0x560808841380; 1 drivers
v0x56080882e190_0 .net "Sum", 0 0, L_0x5608088412a0; 1 drivers
v0x56080882e280_0 .net "and1", 0 0, L_0x560808841010; 1 drivers
v0x56080882e350_0 .net "and2", 0 0, L_0x560808841110; 1 drivers
v0x56080882e420_0 .net "xor1", 0 0, L_0x560808841080; 1 drivers
S_0x56080882d200 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x56080882cff0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808841010 .functor AND 1, L_0x560808841410, L_0x560808841580, C4<1>, C4<1>;
L_0x560808841080 .functor XOR 1, L_0x560808841410, L_0x560808841580, C4<0>, C4<0>;
v0x56080882d480_0 .net "A", 0 0, L_0x560808841410; alias, 1 drivers
v0x56080882d540_0 .net "B", 0 0, L_0x560808841580; alias, 1 drivers
v0x56080882d600_0 .net "Carry", 0 0, L_0x560808841010; alias, 1 drivers
v0x56080882d6d0_0 .net "Sum", 0 0, L_0x560808841080; alias, 1 drivers
S_0x56080882d840 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x56080882cff0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808841110 .functor AND 1, L_0x560808841080, L_0x5608088416b0, C4<1>, C4<1>;
L_0x5608088412a0 .functor XOR 1, L_0x560808841080, L_0x5608088416b0, C4<0>, C4<0>;
v0x56080882dab0_0 .net "A", 0 0, L_0x560808841080; alias, 1 drivers
v0x56080882db80_0 .net "B", 0 0, L_0x5608088416b0; alias, 1 drivers
v0x56080882dc20_0 .net "Carry", 0 0, L_0x560808841110; alias, 1 drivers
v0x56080882dcf0_0 .net "Sum", 0 0, L_0x5608088412a0; alias, 1 drivers
S_0x56080882e510 .scope module, "f3" "fulladder" 4 14, 5 1 0, S_0x56080882a310;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x560808841dc0 .functor OR 1, L_0x560808841920, L_0x560808841b50, C4<0>, C4<0>;
v0x56080882f370_0 .net "A", 0 0, L_0x560808841ec0; 1 drivers
v0x56080882f430_0 .net "B", 0 0, L_0x560808842050; 1 drivers
v0x56080882f500_0 .net "Carry", 0 0, L_0x560808842210; 1 drivers
v0x56080882f600_0 .net "CarryO", 0 0, L_0x560808841dc0; alias, 1 drivers
v0x56080882f6a0_0 .net "Sum", 0 0, L_0x560808841ce0; 1 drivers
v0x56080882f790_0 .net "and1", 0 0, L_0x560808841920; 1 drivers
v0x56080882f860_0 .net "and2", 0 0, L_0x560808841b50; 1 drivers
v0x56080882f930_0 .net "xor1", 0 0, L_0x560808841ac0; 1 drivers
S_0x56080882e6f0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x56080882e510;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808841920 .functor AND 1, L_0x560808841ec0, L_0x560808842050, C4<1>, C4<1>;
L_0x560808841ac0 .functor XOR 1, L_0x560808841ec0, L_0x560808842050, C4<0>, C4<0>;
v0x56080882e970_0 .net "A", 0 0, L_0x560808841ec0; alias, 1 drivers
v0x56080882ea50_0 .net "B", 0 0, L_0x560808842050; alias, 1 drivers
v0x56080882eb10_0 .net "Carry", 0 0, L_0x560808841920; alias, 1 drivers
v0x56080882ebe0_0 .net "Sum", 0 0, L_0x560808841ac0; alias, 1 drivers
S_0x56080882ed50 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x56080882e510;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808841b50 .functor AND 1, L_0x560808841ac0, L_0x560808842210, C4<1>, C4<1>;
L_0x560808841ce0 .functor XOR 1, L_0x560808841ac0, L_0x560808842210, C4<0>, C4<0>;
v0x56080882efc0_0 .net "A", 0 0, L_0x560808841ac0; alias, 1 drivers
v0x56080882f090_0 .net "B", 0 0, L_0x560808842210; alias, 1 drivers
v0x56080882f130_0 .net "Carry", 0 0, L_0x560808841b50; alias, 1 drivers
v0x56080882f200_0 .net "Sum", 0 0, L_0x560808841ce0; alias, 1 drivers
S_0x5608088301a0 .scope module, "add2" "addition" 3 58, 4 1 0, S_0x560808804330;
.timescale 0 0;
.port_info 0 /INPUT 4 "A";
.port_info 1 /INPUT 4 "B";
.port_info 2 /INPUT 1 "CarryIN";
.port_info 3 /OUTPUT 4 "Y";
.port_info 4 /OUTPUT 1 "CarryOUT";
.port_info 5 /OUTPUT 1 "overflow";
L_0x560808845a10 .functor XOR 1, L_0x560808845a80, L_0x560808845330, C4<0>, C4<0>;
v0x560808835ac0_0 .net "A", 3 0, L_0x560808842da0; alias, 1 drivers
v0x560808835ba0_0 .net "B", 3 0, L_0x560808845ba0; 1 drivers
v0x560808835c80_0 .net "Carry4", 2 0, L_0x560808844e60; 1 drivers
L_0x7f3ea6b4d0f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x560808835d40_0 .net "CarryIN", 0 0, L_0x7f3ea6b4d0f0; 1 drivers
v0x560808835e30_0 .net "CarryOUT", 0 0, L_0x560808845330; 1 drivers
v0x560808835f20_0 .net "Y", 3 0, L_0x560808845970; 1 drivers
v0x560808835fe0_0 .net *"_ivl_39", 0 0, L_0x560808845a80; 1 drivers
v0x5608088360c0_0 .net "overflow", 0 0, L_0x560808845a10; alias, 1 drivers
L_0x560808843e40 .part L_0x560808842da0, 0, 1;
L_0x560808843f70 .part L_0x560808845ba0, 0, 1;
L_0x560808844360 .part L_0x560808842da0, 1, 1;
L_0x560808844520 .part L_0x560808845ba0, 1, 1;
L_0x560808844650 .part L_0x560808844e60, 0, 1;
L_0x560808844a40 .part L_0x560808842da0, 2, 1;
L_0x560808844bb0 .part L_0x560808845ba0, 2, 1;
L_0x560808844ce0 .part L_0x560808844e60, 1, 1;
L_0x560808844e60 .concat8 [ 1 1 1 0], L_0x560808843dd0, L_0x5608088442f0, L_0x5608088449d0;
L_0x5608088453f0 .part L_0x560808842da0, 3, 1;
L_0x560808845580 .part L_0x560808845ba0, 3, 1;
L_0x560808845740 .part L_0x560808844e60, 2, 1;
L_0x560808845970 .concat8 [ 1 1 1 1], L_0x560808843cd0, L_0x560808844280, L_0x560808844960, L_0x560808845270;
L_0x560808845a80 .part L_0x560808844e60, 2, 1;
S_0x560808830420 .scope module, "f0" "fulladder" 4 11, 5 1 0, S_0x5608088301a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x560808843dd0 .functor OR 1, L_0x5608088439b0, L_0x560808843b80, C4<0>, C4<0>;
v0x560808831350_0 .net "A", 0 0, L_0x560808843e40; 1 drivers
v0x560808831410_0 .net "B", 0 0, L_0x560808843f70; 1 drivers
v0x5608088314e0_0 .net "Carry", 0 0, L_0x7f3ea6b4d0f0; alias, 1 drivers
v0x5608088315e0_0 .net "CarryO", 0 0, L_0x560808843dd0; 1 drivers
v0x560808831680_0 .net "Sum", 0 0, L_0x560808843cd0; 1 drivers
v0x560808831770_0 .net "and1", 0 0, L_0x5608088439b0; 1 drivers
v0x560808831840_0 .net "and2", 0 0, L_0x560808843b80; 1 drivers
v0x560808831910_0 .net "xor1", 0 0, L_0x560808843b10; 1 drivers
S_0x5608088306b0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808830420;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x5608088439b0 .functor AND 1, L_0x560808843e40, L_0x560808843f70, C4<1>, C4<1>;
L_0x560808843b10 .functor XOR 1, L_0x560808843e40, L_0x560808843f70, C4<0>, C4<0>;
v0x560808830950_0 .net "A", 0 0, L_0x560808843e40; alias, 1 drivers
v0x560808830a30_0 .net "B", 0 0, L_0x560808843f70; alias, 1 drivers
v0x560808830af0_0 .net "Carry", 0 0, L_0x5608088439b0; alias, 1 drivers
v0x560808830bc0_0 .net "Sum", 0 0, L_0x560808843b10; alias, 1 drivers
S_0x560808830d30 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808830420;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808843b80 .functor AND 1, L_0x560808843b10, L_0x7f3ea6b4d0f0, C4<1>, C4<1>;
L_0x560808843cd0 .functor XOR 1, L_0x560808843b10, L_0x7f3ea6b4d0f0, C4<0>, C4<0>;
v0x560808830fa0_0 .net "A", 0 0, L_0x560808843b10; alias, 1 drivers
v0x560808831070_0 .net "B", 0 0, L_0x7f3ea6b4d0f0; alias, 1 drivers
v0x560808831110_0 .net "Carry", 0 0, L_0x560808843b80; alias, 1 drivers
v0x5608088311e0_0 .net "Sum", 0 0, L_0x560808843cd0; alias, 1 drivers
S_0x560808831a00 .scope module, "f1" "fulladder" 4 12, 5 1 0, S_0x5608088301a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x5608088442f0 .functor OR 1, L_0x5608088440a0, L_0x560808844180, C4<0>, C4<0>;
v0x5608088328e0_0 .net "A", 0 0, L_0x560808844360; 1 drivers
v0x5608088329a0_0 .net "B", 0 0, L_0x560808844520; 1 drivers
v0x560808832a70_0 .net "Carry", 0 0, L_0x560808844650; 1 drivers
v0x560808832b70_0 .net "CarryO", 0 0, L_0x5608088442f0; 1 drivers
v0x560808832c10_0 .net "Sum", 0 0, L_0x560808844280; 1 drivers
v0x560808832d00_0 .net "and1", 0 0, L_0x5608088440a0; 1 drivers
v0x560808832dd0_0 .net "and2", 0 0, L_0x560808844180; 1 drivers
v0x560808832ea0_0 .net "xor1", 0 0, L_0x560808844110; 1 drivers
S_0x560808831c60 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808831a00;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x5608088440a0 .functor AND 1, L_0x560808844360, L_0x560808844520, C4<1>, C4<1>;
L_0x560808844110 .functor XOR 1, L_0x560808844360, L_0x560808844520, C4<0>, C4<0>;
v0x560808831ee0_0 .net "A", 0 0, L_0x560808844360; alias, 1 drivers
v0x560808831fc0_0 .net "B", 0 0, L_0x560808844520; alias, 1 drivers
v0x560808832080_0 .net "Carry", 0 0, L_0x5608088440a0; alias, 1 drivers
v0x560808832150_0 .net "Sum", 0 0, L_0x560808844110; alias, 1 drivers
S_0x5608088322c0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808831a00;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808844180 .functor AND 1, L_0x560808844110, L_0x560808844650, C4<1>, C4<1>;
L_0x560808844280 .functor XOR 1, L_0x560808844110, L_0x560808844650, C4<0>, C4<0>;
v0x560808832530_0 .net "A", 0 0, L_0x560808844110; alias, 1 drivers
v0x560808832600_0 .net "B", 0 0, L_0x560808844650; alias, 1 drivers
v0x5608088326a0_0 .net "Carry", 0 0, L_0x560808844180; alias, 1 drivers
v0x560808832770_0 .net "Sum", 0 0, L_0x560808844280; alias, 1 drivers
S_0x560808832f90 .scope module, "f2" "fulladder" 4 13, 5 1 0, S_0x5608088301a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x5608088449d0 .functor OR 1, L_0x560808844780, L_0x560808844860, C4<0>, C4<0>;
v0x560808833e80_0 .net "A", 0 0, L_0x560808844a40; 1 drivers
v0x560808833f40_0 .net "B", 0 0, L_0x560808844bb0; 1 drivers
v0x560808834010_0 .net "Carry", 0 0, L_0x560808844ce0; 1 drivers
v0x560808834110_0 .net "CarryO", 0 0, L_0x5608088449d0; 1 drivers
v0x5608088341b0_0 .net "Sum", 0 0, L_0x560808844960; 1 drivers
v0x5608088342a0_0 .net "and1", 0 0, L_0x560808844780; 1 drivers
v0x560808834370_0 .net "and2", 0 0, L_0x560808844860; 1 drivers
v0x560808834440_0 .net "xor1", 0 0, L_0x5608088447f0; 1 drivers
S_0x560808833220 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808832f90;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808844780 .functor AND 1, L_0x560808844a40, L_0x560808844bb0, C4<1>, C4<1>;
L_0x5608088447f0 .functor XOR 1, L_0x560808844a40, L_0x560808844bb0, C4<0>, C4<0>;
v0x5608088334a0_0 .net "A", 0 0, L_0x560808844a40; alias, 1 drivers
v0x560808833560_0 .net "B", 0 0, L_0x560808844bb0; alias, 1 drivers
v0x560808833620_0 .net "Carry", 0 0, L_0x560808844780; alias, 1 drivers
v0x5608088336f0_0 .net "Sum", 0 0, L_0x5608088447f0; alias, 1 drivers
S_0x560808833860 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808832f90;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808844860 .functor AND 1, L_0x5608088447f0, L_0x560808844ce0, C4<1>, C4<1>;
L_0x560808844960 .functor XOR 1, L_0x5608088447f0, L_0x560808844ce0, C4<0>, C4<0>;
v0x560808833ad0_0 .net "A", 0 0, L_0x5608088447f0; alias, 1 drivers
v0x560808833ba0_0 .net "B", 0 0, L_0x560808844ce0; alias, 1 drivers
v0x560808833c40_0 .net "Carry", 0 0, L_0x560808844860; alias, 1 drivers
v0x560808833d10_0 .net "Sum", 0 0, L_0x560808844960; alias, 1 drivers
S_0x560808834530 .scope module, "f3" "fulladder" 4 14, 5 1 0, S_0x5608088301a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x560808845330 .functor OR 1, L_0x560808844f50, L_0x560808845120, C4<0>, C4<0>;
v0x560808835410_0 .net "A", 0 0, L_0x5608088453f0; 1 drivers
v0x5608088354d0_0 .net "B", 0 0, L_0x560808845580; 1 drivers
v0x5608088355a0_0 .net "Carry", 0 0, L_0x560808845740; 1 drivers
v0x5608088356a0_0 .net "CarryO", 0 0, L_0x560808845330; alias, 1 drivers
v0x560808835740_0 .net "Sum", 0 0, L_0x560808845270; 1 drivers
v0x560808835830_0 .net "and1", 0 0, L_0x560808844f50; 1 drivers
v0x560808835900_0 .net "and2", 0 0, L_0x560808845120; 1 drivers
v0x5608088359d0_0 .net "xor1", 0 0, L_0x5608088450b0; 1 drivers
S_0x560808834790 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808834530;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808844f50 .functor AND 1, L_0x5608088453f0, L_0x560808845580, C4<1>, C4<1>;
L_0x5608088450b0 .functor XOR 1, L_0x5608088453f0, L_0x560808845580, C4<0>, C4<0>;
v0x560808834a10_0 .net "A", 0 0, L_0x5608088453f0; alias, 1 drivers
v0x560808834af0_0 .net "B", 0 0, L_0x560808845580; alias, 1 drivers
v0x560808834bb0_0 .net "Carry", 0 0, L_0x560808844f50; alias, 1 drivers
v0x560808834c80_0 .net "Sum", 0 0, L_0x5608088450b0; alias, 1 drivers
S_0x560808834df0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808834530;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808845120 .functor AND 1, L_0x5608088450b0, L_0x560808845740, C4<1>, C4<1>;
L_0x560808845270 .functor XOR 1, L_0x5608088450b0, L_0x560808845740, C4<0>, C4<0>;
v0x560808835060_0 .net "A", 0 0, L_0x5608088450b0; alias, 1 drivers
v0x560808835130_0 .net "B", 0 0, L_0x560808845740; alias, 1 drivers
v0x5608088351d0_0 .net "Carry", 0 0, L_0x560808845120; alias, 1 drivers
v0x5608088352a0_0 .net "Sum", 0 0, L_0x560808845270; alias, 1 drivers
.scope S_0x560808805dd0;
T_0 ;
%vpi_call 2 13 "$dumpfile", "mult.vcd" {0 0 0};
%vpi_call 2 14 "$dumpvars" {0 0 0};
%pushi/vec4 8, 0, 4;
%store/vec4 v0x56080883b1b0_0, 0, 4;
%pushi/vec4 8, 0, 4;
%store/vec4 v0x56080883b2a0_0, 0, 4;
%delay 5, 0;
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 7;
"N/A";
"<interactive>";
"multTB.v";
"multiplier.v";
"addition.v";
"fulladder.v";
"halfadder.v";

449
tangTest/mult.vcd Normal file
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@ -0,0 +1,449 @@
$date
Sun Jan 19 14:35:11 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module multTB $end
$var wire 8 ! Y [7:0] $end
$var reg 4 " A [3:0] $end
$var reg 4 # B [3:0] $end
$scope module uut $end
$var wire 4 $ A [3:0] $end
$var wire 4 % B [3:0] $end
$var wire 1 & overflow2 $end
$var wire 1 ' overflow1 $end
$var wire 1 ( overflow0 $end
$var wire 4 ) b0 [3:0] $end
$var wire 4 * a2 [3:0] $end
$var wire 4 + a1 [3:0] $end
$var wire 4 , a0 [3:0] $end
$var wire 8 - Y [7:0] $end
$var wire 5 . S2 [4:0] $end
$var wire 5 / S1 [4:0] $end
$var wire 5 0 S0 [4:0] $end
$scope module add0 $end
$var wire 4 1 A [3:0] $end
$var wire 4 2 B [3:0] $end
$var wire 1 3 CarryIN $end
$var wire 1 ( overflow $end
$var wire 4 4 Y [3:0] $end
$var wire 1 5 CarryOUT $end
$var wire 3 6 Carry4 [2:0] $end
$scope module f0 $end
$var wire 1 7 A $end
$var wire 1 8 B $end
$var wire 1 3 Carry $end
$var wire 1 9 CarryO $end
$var wire 1 : xor1 $end
$var wire 1 ; and2 $end
$var wire 1 < and1 $end
$var wire 1 = Sum $end
$scope module h1 $end
$var wire 1 7 A $end
$var wire 1 8 B $end
$var wire 1 < Carry $end
$var wire 1 : Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 : A $end
$var wire 1 3 B $end
$var wire 1 ; Carry $end
$var wire 1 = Sum $end
$upscope $end
$upscope $end
$scope module f1 $end
$var wire 1 > A $end
$var wire 1 ? B $end
$var wire 1 @ Carry $end
$var wire 1 A CarryO $end
$var wire 1 B xor1 $end
$var wire 1 C and2 $end
$var wire 1 D and1 $end
$var wire 1 E Sum $end
$scope module h1 $end
$var wire 1 > A $end
$var wire 1 ? B $end
$var wire 1 D Carry $end
$var wire 1 B Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 B A $end
$var wire 1 @ B $end
$var wire 1 C Carry $end
$var wire 1 E Sum $end
$upscope $end
$upscope $end
$scope module f2 $end
$var wire 1 F A $end
$var wire 1 G B $end
$var wire 1 H Carry $end
$var wire 1 I CarryO $end
$var wire 1 J xor1 $end
$var wire 1 K and2 $end
$var wire 1 L and1 $end
$var wire 1 M Sum $end
$scope module h1 $end
$var wire 1 F A $end
$var wire 1 G B $end
$var wire 1 L Carry $end
$var wire 1 J Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 J A $end
$var wire 1 H B $end
$var wire 1 K Carry $end
$var wire 1 M Sum $end
$upscope $end
$upscope $end
$scope module f3 $end
$var wire 1 N A $end
$var wire 1 O B $end
$var wire 1 P Carry $end
$var wire 1 5 CarryO $end
$var wire 1 Q xor1 $end
$var wire 1 R and2 $end
$var wire 1 S and1 $end
$var wire 1 T Sum $end
$scope module h1 $end
$var wire 1 N A $end
$var wire 1 O B $end
$var wire 1 S Carry $end
$var wire 1 Q Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 Q A $end
$var wire 1 P B $end
$var wire 1 R Carry $end
$var wire 1 T Sum $end
$upscope $end
$upscope $end
$upscope $end
$scope module add1 $end
$var wire 4 U A [3:0] $end
$var wire 4 V B [3:0] $end
$var wire 1 W CarryIN $end
$var wire 1 ' overflow $end
$var wire 4 X Y [3:0] $end
$var wire 1 Y CarryOUT $end
$var wire 3 Z Carry4 [2:0] $end
$scope module f0 $end
$var wire 1 [ A $end
$var wire 1 \ B $end
$var wire 1 W Carry $end
$var wire 1 ] CarryO $end
$var wire 1 ^ xor1 $end
$var wire 1 _ and2 $end
$var wire 1 ` and1 $end
$var wire 1 a Sum $end
$scope module h1 $end
$var wire 1 [ A $end
$var wire 1 \ B $end
$var wire 1 ` Carry $end
$var wire 1 ^ Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 ^ A $end
$var wire 1 W B $end
$var wire 1 _ Carry $end
$var wire 1 a Sum $end
$upscope $end
$upscope $end
$scope module f1 $end
$var wire 1 b A $end
$var wire 1 c B $end
$var wire 1 d Carry $end
$var wire 1 e CarryO $end
$var wire 1 f xor1 $end
$var wire 1 g and2 $end
$var wire 1 h and1 $end
$var wire 1 i Sum $end
$scope module h1 $end
$var wire 1 b A $end
$var wire 1 c B $end
$var wire 1 h Carry $end
$var wire 1 f Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 f A $end
$var wire 1 d B $end
$var wire 1 g Carry $end
$var wire 1 i Sum $end
$upscope $end
$upscope $end
$scope module f2 $end
$var wire 1 j A $end
$var wire 1 k B $end
$var wire 1 l Carry $end
$var wire 1 m CarryO $end
$var wire 1 n xor1 $end
$var wire 1 o and2 $end
$var wire 1 p and1 $end
$var wire 1 q Sum $end
$scope module h1 $end
$var wire 1 j A $end
$var wire 1 k B $end
$var wire 1 p Carry $end
$var wire 1 n Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 n A $end
$var wire 1 l B $end
$var wire 1 o Carry $end
$var wire 1 q Sum $end
$upscope $end
$upscope $end
$scope module f3 $end
$var wire 1 r A $end
$var wire 1 s B $end
$var wire 1 t Carry $end
$var wire 1 Y CarryO $end
$var wire 1 u xor1 $end
$var wire 1 v and2 $end
$var wire 1 w and1 $end
$var wire 1 x Sum $end
$scope module h1 $end
$var wire 1 r A $end
$var wire 1 s B $end
$var wire 1 w Carry $end
$var wire 1 u Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 u A $end
$var wire 1 t B $end
$var wire 1 v Carry $end
$var wire 1 x Sum $end
$upscope $end
$upscope $end
$upscope $end
$scope module add2 $end
$var wire 4 y A [3:0] $end
$var wire 4 z B [3:0] $end
$var wire 1 { CarryIN $end
$var wire 1 & overflow $end
$var wire 4 | Y [3:0] $end
$var wire 1 } CarryOUT $end
$var wire 3 ~ Carry4 [2:0] $end
$scope module f0 $end
$var wire 1 !" A $end
$var wire 1 "" B $end
$var wire 1 { Carry $end
$var wire 1 #" CarryO $end
$var wire 1 $" xor1 $end
$var wire 1 %" and2 $end
$var wire 1 &" and1 $end
$var wire 1 '" Sum $end
$scope module h1 $end
$var wire 1 !" A $end
$var wire 1 "" B $end
$var wire 1 &" Carry $end
$var wire 1 $" Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 $" A $end
$var wire 1 { B $end
$var wire 1 %" Carry $end
$var wire 1 '" Sum $end
$upscope $end
$upscope $end
$scope module f1 $end
$var wire 1 (" A $end
$var wire 1 )" B $end
$var wire 1 *" Carry $end
$var wire 1 +" CarryO $end
$var wire 1 ," xor1 $end
$var wire 1 -" and2 $end
$var wire 1 ." and1 $end
$var wire 1 /" Sum $end
$scope module h1 $end
$var wire 1 (" A $end
$var wire 1 )" B $end
$var wire 1 ." Carry $end
$var wire 1 ," Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 ," A $end
$var wire 1 *" B $end
$var wire 1 -" Carry $end
$var wire 1 /" Sum $end
$upscope $end
$upscope $end
$scope module f2 $end
$var wire 1 0" A $end
$var wire 1 1" B $end
$var wire 1 2" Carry $end
$var wire 1 3" CarryO $end
$var wire 1 4" xor1 $end
$var wire 1 5" and2 $end
$var wire 1 6" and1 $end
$var wire 1 7" Sum $end
$scope module h1 $end
$var wire 1 0" A $end
$var wire 1 1" B $end
$var wire 1 6" Carry $end
$var wire 1 4" Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 4" A $end
$var wire 1 2" B $end
$var wire 1 5" Carry $end
$var wire 1 7" Sum $end
$upscope $end
$upscope $end
$scope module f3 $end
$var wire 1 8" A $end
$var wire 1 9" B $end
$var wire 1 :" Carry $end
$var wire 1 } CarryO $end
$var wire 1 ;" xor1 $end
$var wire 1 <" and2 $end
$var wire 1 =" and1 $end
$var wire 1 >" Sum $end
$scope module h1 $end
$var wire 1 8" A $end
$var wire 1 9" B $end
$var wire 1 =" Carry $end
$var wire 1 ;" Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 ;" A $end
$var wire 1 :" B $end
$var wire 1 <" Carry $end
$var wire 1 >" Sum $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1>"
0="
0<"
1;"
0:"
09"
18"
07"
06"
05"
04"
03"
02"
01"
00"
0/"
0."
0-"
0,"
0+"
0*"
0)"
0("
0'"
0&"
0%"
0$"
0#"
0""
0!"
b0 ~
0}
b1000 |
0{
b0 z
b1000 y
0x
0w
0v
0u
0t
0s
0r
0q
0p
0o
0n
0m
0l
0k
0j
0i
0h
0g
0f
0e
0d
0c
0b
0a
0`
0_
0^
0]
0\
0[
b0 Z
0Y
b0 X
0W
b0 V
b0 U
0T
0S
0R
0Q
0P
0O
0N
0M
0L
0K
0J
0I
0H
0G
0F
0E
0D
0C
0B
0A
0@
0?
0>
0=
0<
0;
0:
09
08
07
b0 6
05
b0 4
03
b0 2
b0 1
b0 0
b0 /
b1000 .
b1000000 -
b0 ,
b0 +
b1000 *
b0 )
0(
0'
0&
b1000 %
b1000 $
b1000 #
b1000 "
b1000000 !
$end
#5

18
tangTest/multTB.v Normal file
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@ -0,0 +1,18 @@
module multTB();
reg [3:0] A, B;
wire [7:0] Y;
multiplier uut (
.A(A),
.B(B),
.Y(Y)
);
initial begin
$dumpfile("mult.vcd");
$dumpvars;
A = 4'b1000; B = 4'b1000; #5;
end
endmodule

76
tangTest/multiplier.v Normal file
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module multiplier (
input [3:0] A, B,
output [7:0] Y
);
wire [3:0] b0, a0, a1, a2;
wire [4:0] S0, S1, S2;
wire carry0, carry1, carry2;
wire overflow0, overflow1, overflow2;
// Partial product generation
and (Y[0], A[0], B[0]); // LSB of the result
// Generate partial products for B[0] and B[1]
and ab00 (b0[0], A[1], B[0]);
and ab01 (b0[1], A[2], B[0]);
and ab02 (b0[2], A[3], B[0]);
not ab03 (b0[3], 1'b1); // Initialize b0[3] to 0
and aa00 (a0[0], A[0], B[1]);
and aa01 (a0[1], A[1], B[1]);
and aa02 (a0[2], A[2], B[1]);
and aa03 (a0[3], A[3], B[1]);
// First addition
addition add0 (
.A(a0),
.B(b0),
.CarryIN(1'b0),
.Y(S0[3:0]),
.CarryOUT(S0[4]),
.overflow(overflow0)
);
// Generate partial products for B[2]
and aa10 (a1[0], A[0], B[2]);
and aa11 (a1[1], A[1], B[2]);
and aa12 (a1[2], A[2], B[2]);
and aa13 (a1[3], A[3], B[2]);
// Second addition
addition add1 (
.A(a1),
.B(S0[4:1]),
.CarryIN(1'b0),
.Y(S1[3:0]),
.CarryOUT(S1[4]),
.overflow(overflow1)
);
// Generate partial products for B[3]
and aa20 (a2[0], A[0], B[3]);
and aa21 (a2[1], A[1], B[3]);
and aa22 (a2[2], A[2], B[3]);
and aa23 (a2[3], A[3], B[3]);
// Third addition
addition add2 (
.A(a2),
.B(S1[4:1]),
.CarryIN(1'b0),
.Y(S2[3:0]),
.CarryOUT(S2[4]),
.overflow(overflow2)
);
// Combine results into the final output Y
or o01 (Y[1], S0[0], 1'b0);
or o02 (Y[2], S1[0], 1'b0);
or o03 (Y[3], S2[0], 1'b0);
or o04 (Y[4], S2[1], 1'b0);
or o05 (Y[5], S2[2], 1'b0);
or o06 (Y[6], S2[3], 1'b0);
or o07 (Y[7], S2[4], 1'b0);
endmodule

25
tangTest/opCode.v Normal file
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module opCode (
input [2:0] A,
output [7:0] opCode
);
wire and1, and2, and3, and4, notA, notB, notC;
not n1(notA, A[2]);
not n2(notB, A[1]);
not n3(notC, A[0]);
and a01(and1, A[2], A[1]);
and a02(and2, notA, A[1]);
and a03(and3, A[2], notB);
and a04(and4, notA, notB);
and a1(opCode[0], and4, notC);
and a2(opCode[1], and4, A[0]);
and a3(opCode[2], and2, notC);
and a4(opCode[3], and2, A[0]);
and a5(opCode[4], and3, notC);
and a6(opCode[5], and3, A[0]);
and a7(opCode[6], and1, notC);
and a8(opCode[7], and1, A[0]);
endmodule

20
tangTest/selector.v Normal file
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module selector (
input [3:0] A,
input [3:0] B,
input [2:0] opCodeA,
input [1:0] select,
input [11:0] ALUY,
output reg [11:0] Y
);
always @(*) begin
case (select)
2'b00: Y = {8'b00000000, A}; // Zero-extend A to 8 bits
2'b01: Y = {8'b00000000, B}; // Zero-extend B to 8 bits
2'b10: Y = {9'b000000000, opCodeA}; // Zero-extend opCodeA to 8 bits
2'b11: Y = ALUY; // Directly assign ALUY
default: Y = ALUY; // Default case for safety
endcase
end
endmodule

16
tangTest/subtraction.v Normal file
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module subtraction (
input [3:0] A, B,
input BorrowIN,
output [3:0] Y,
output BorrowOUT //Overflow signal'ini yani negatif gonderecek
);
wire [3:0] tempB;
// Full Subtraction logic for each bit (borrow-in for each subsequent bit)
fullsubtraction f0 (.A(A[0]), .B(B[0]), .BorrowIN(BorrowIN), .Difference(Y[0]), .BorrowOut(tempB[0]));
fullsubtraction f1 (.A(A[1]), .B(B[1]), .BorrowIN(tempB[0]), .Difference(Y[1]), .BorrowOut(tempB[1]));
fullsubtraction f2 (.A(A[2]), .B(B[2]), .BorrowIN(tempB[1]), .Difference(Y[2]), .BorrowOut(tempB[2]));
fullsubtraction f3 (.A(A[3]), .B(B[3]), .BorrowIN(tempB[2]), .Difference(Y[3]), .BorrowOut(BorrowOUT));
endmodule

2220
tangTest/top Normal file
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20
tangTest/top.v Normal file
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@ -0,0 +1,20 @@
module top (
input [3:0] A, B,
input [2:0] opCodeA,
input [1:0] select,
output [1:0] led,
output [11:0] Y
);
wire wire1, wire2;
wire [11:0] selectY;
ALU a1( .A(A),
.B(B),
.opCodeA(opCodeA),
.CarryIN(1'b0),
.bcd(selectY),
.CarryOUT(led[0]),
.overflow(led[1]));
selector s1(.A(A), .B(B), .opCodeA(opCodeA), .select(select), .ALUY(selectY), .Y(Y));
endmodule

1493
tangTest/top.vcd Normal file
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28
tangTest/topTB.v Normal file
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module topTB();
reg [3:0] A,B;
reg [2:0] opCodeA;
reg [1:0] select;
wire [1:0] led;
wire [11:0] Y;
top uut (
.A(A),
.B(B),
.opCodeA(opCodeA),
.select(select),
.led(led),
.Y(Y)
);
initial begin
$dumpfile("top.vcd");
$dumpvars;
A = 4'b1111; B = 4'b1111; opCodeA = 3'b000; select = 2'b01; #5;
A = 4'b0000; B = 4'b1111; opCodeA = 3'b001; select = 2'b01; #5;
A = 4'b1111; B = 4'b0001; opCodeA = 3'b001; select = 2'b01; #5;
A = 4'b1111; B = 4'b0001; opCodeA = 3'b001; select = 2'b11; #5;
$finish;
end
endmodule