kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
41 Commits 1 Branch 0 Tags
e91a8471ac83616c512723908aaaed8a7bdbc518
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
k0rrluna e91a8471ac final fpga
2025-01-21 05:12:57 +03:00
gowin
final fpga
2025-01-21 05:12:57 +03:00
iverilog
subtraction & multiplier
2024-12-20 21:28:15 +03:00
project
opCode fixes
2024-12-15 04:25:43 +03:00
project0.2
selector&bcd
2025-01-15 22:21:50 +03:00
tangTest
bttnTB
2025-01-20 15:16:37 +03:00
Description
No description provided
2 MiB
Languages
Verilog 99.2%
Shell 0.5%
Coq 0.3%