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final fpga

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This commit is contained in:
k0rrluna 2025-01-21 05:12:57 +03:00
parent 6b83c0f2e7
commit e91a8471ac
92 changed files with 15650 additions and 199 deletions
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25
gowin/bttn/bttn.gprj Normal file
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@ -0,0 +1,25 @@
<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
<FileList>
<File path="src/ALU.v" type="file.verilog" enable="1"/>
<File path="src/BinaryToBCD.v" type="file.verilog" enable="1"/>
<File path="src/addition.v" type="file.verilog" enable="1"/>
<File path="src/arithmeticUnit.v" type="file.verilog" enable="1"/>
<File path="src/bttn.v" type="file.verilog" enable="1"/>
<File path="src/dabble.v" type="file.verilog" enable="1"/>
<File path="src/fulladder.v" type="file.verilog" enable="1"/>
<File path="src/fullsubtraction.v" type="file.verilog" enable="1"/>
<File path="src/halfadder.v" type="file.verilog" enable="1"/>
<File path="src/halfsubtraction.v" type="file.verilog" enable="1"/>
<File path="src/logicUnit.v" type="file.verilog" enable="1"/>
<File path="src/multiplier.v" type="file.verilog" enable="1"/>
<File path="src/opCode.v" type="file.verilog" enable="1"/>
<File path="src/selector.v" type="file.verilog" enable="1"/>
<File path="src/subtraction.v" type="file.verilog" enable="1"/>
<File path="src/bttn.cst" type="file.cst" enable="1"/>
</FileList>
</Project>

9
gowin/bttn/bttn.gprj.user
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@ -7,8 +7,6 @@
<Process ID="Pnr" State="2"/>
<Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/>
<Process ID="Gvio" State="2"/>
<Process ID="Place" State="2"/>
</FlowState>
<ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/bttn.vg"/>
@ -22,10 +20,5 @@
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/bttn_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/bttn_syn_rsc.xml"/>
</ResultFileList>
<<<<<<< HEAD
<Ui>000000ff00000001fd00000002000000000000018e0000051efc0200000001fc000000630000051e0000011201000027fa000000000200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff000000c000fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff000000bc00fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff000000ea00ffffff0000000300000ab000000145fc0100000001fc0000000000000ab0000000e700fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000009e00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000e700ffffff0000091a0000051e00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000bdffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c007301000001a5ffffffff0000000000000000ffffffff0100000275ffffffff0000000000000000</Ui>
=======
<Ui>000000ff00000001fd00000002000000000000018e0000025dfc0200000001fc000000370000025d0000000000fffffffaffffffff0200000004fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000000000030000078000000145fc0100000001fc00000000000007800000009b00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000009b00ffffff000005ee0000025d00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000000000280043006f00720065002e0054006f006f006c006200610072002e00500072006f00630065007300730100000245ffffffff0000000000000000</Ui>
<FpUi></FpUi>
>>>>>>> 15916a2c534beff06a16239dd4912b40b7f837b6
<Ui>000000ff00000001fd00000002000000000000018e0000051efc0200000001fc000000630000051e0000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff00000000000000000000000300000ab000000145fc0100000001fc0000000000000ab0000000e700fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000009e00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000e700ffffff0000091a0000051e00000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000bdffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c007301000001a5ffffffff0000000000000000</Ui>
</UserConfig>

2
gowin/bttn/bttn.gprj.userZone.Identifier Normal file
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@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

2
gowin/bttn/bttn.gprjZone.Identifier Normal file
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@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

6
gowin/bttn/impl/bttn_process_config.json
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@ -4,7 +4,6 @@
"CPU" : false,
"CRC_CHECK" : true,
"Clock_Route_Order" : 0,
"Convert_SDP32_36_to_SDP16_18" : true,
"Correct_Hold_Violation" : true,
"DONE" : false,
"DOWNLOAD_SPEED" : "default",
@ -19,7 +18,7 @@
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
"Enable_DSRM" : false,
"FORMAT" : "binary",
"FREQUENCY_DIVIDER" : "1",
"FREQUENCY_DIVIDER" : "",
"Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false,
@ -32,8 +31,6 @@
"HOTBOOT" : false,
"I2C" : false,
"I2C_SLAVE_ADDR" : "00",
"INCREMENTAL_PLACE_AND_ROUTING" : "0",
"INCREMENTAL_PLACE_ONLY" : "0",
"IncludePath" : [
],
@ -81,7 +78,6 @@
"TopModule" : "",
"USERCODE" : "default",
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
"VCC" : "1.0",
"VCCAUX" : 3.3,
"VCCX" : "3.3",
"VHDL_Standard" : "VHDL_Std_1993",

2
gowin/bttn/impl/bttn_process_config.jsonZone.Identifier Normal file
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@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

130
gowin/bttn/impl/gwsynthesis/bttn.log Normal file
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@ -0,0 +1,130 @@
GowinSynthesis start
Running parser ...
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v'
Compiling module 'bttn'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v":1)
Compiling module 'ALU'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":1)
Compiling module 'opCode'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v":1)
Compiling module 'arithmeticUnit'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v":1)
Compiling module 'addition'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":1)
Compiling module 'fulladder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":1)
Compiling module 'halfadder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v":1)
Compiling module 'subtraction'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":1)
Compiling module 'fullsubtraction'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":1)
Compiling module 'halfsubtraction'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v":1)
Compiling module 'logicUnit'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v":1)
Compiling module 'multiplier'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":1)
Compiling module 'BinaryToBCD'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":1)
Compiling module 'dabble'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v":1)
Compiling module 'selector'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v":1)
NOTE (EX0101) : Current top module is "bttn"
[5%] Running netlist conversion ...
Running device independent optimization ...
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "ALU" instantiated to "a1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v":13)
WARN (NL0002) : The module "arithmeticUnit" instantiated to "aU" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":20)
WARN (NL0002) : The module "addition" instantiated to "a1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v":13)
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "subtraction" instantiated to "s1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v":14)
WARN (NL0002) : The module "fullsubtraction" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":11)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
WARN (NL0002) : The module "fullsubtraction" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":12)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
WARN (NL0002) : The module "fullsubtraction" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":13)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
WARN (NL0002) : The module "fullsubtraction" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":14)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
WARN (NL0002) : The module "BinaryToBCD" instantiated to "btod1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":76)
WARN (NL0002) : The module "dabble" instantiated to "d1t" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":21)
WARN (NL0002) : The module "dabble" instantiated to "d2u" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":30)
WARN (NL0002) : The module "dabble" instantiated to "d3v" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":39)
WARN (NL0002) : The module "dabble" instantiated to "d4w" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":48)
WARN (NL0002) : The module "dabble" instantiated to "d5x" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":57)
WARN (NL0002) : The module "dabble" instantiated to "d6y" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":66)
WARN (NL0002) : The module "dabble" instantiated to "d7z" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":75)
WARN (NL0002) : The module "logicUnit" instantiated to "lU" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":21)
WARN (NL0002) : The module "multiplier" instantiated to "mU" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":22)
WARN (NL0002) : The module "addition" instantiated to "add0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":33)
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "addition" instantiated to "add1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":49)
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "addition" instantiated to "add2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":65)
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "opCode" instantiated to "opCd" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":18)
[95%] Generate netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg" completed
[100%] Generate report file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn_syn.rpt.html" completed
GowinSynthesis finish

2
gowin/bttn/impl/gwsynthesis/bttn.logZone.Identifier Normal file
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@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

33
gowin/bttn/impl/gwsynthesis/bttn.prj Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
<Version>beta</Version>
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
<FileList>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v" type="verilog"/>
</FileList>
<OptionList>
<Option type="disable_insert_pad" value="0"/>
<Option type="global_freq" value="100.000"/>
<Option type="looplimit" value="2000"/>
<Option type="output_file" value="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg"/>
<Option type="print_all_synthesis_warning" value="0"/>
<Option type="ram_rw_check" value="0"/>
<Option type="verilog_language" value="verilog-2001"/>
<Option type="vhdl_language" value="vhdl-1993"/>
</OptionList>
</Project>

2
gowin/bttn/impl/gwsynthesis/bttn.prjZone.Identifier Normal file
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@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

465
gowin/bttn/impl/gwsynthesis/bttn.vg Normal file
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@ -0,0 +1,465 @@
//
//Written by GowinSynthesis
//Tool Version "V1.9.9.03 Education (64-bit)"
//Mon Jan 20 18:30:58 2025
//Source file index table:
//file0 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v"
//file1 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v"
//file2 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v"
//file3 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v"
//file4 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v"
//file5 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v"
//file6 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v"
//file7 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v"
//file8 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v"
//file9 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v"
//file10 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/logicUnit.v"
//file11 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v"
//file12 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/opCode.v"
//file13 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/selector.v"
//file14 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v"
`pragma protect begin_protected
`pragma protect version="2.3"
`pragma protect author="default"
`pragma protect author_info="default"
`pragma protect encrypt_agent="GOWIN"
`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
`pragma protect key_block
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`pragma protect encoding=(enctype="base64", line_length=76, bytes=24000)
`pragma protect data_keyowner="default-ip-vendor"
`pragma protect data_keyname="default-ip-key"
`pragma protect data_method="aes128-cfb"
`pragma protect data_block
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`pragma protect end_protected

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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>synthesis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper{ width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
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div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td { border: 1px solid #aaa; }
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th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table td.label { min-width: 100px; width: 8%;}
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.9.03 Education (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Mon Jan 20 18:30:58 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>bttn</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.315s, Peak memory usage = 175.059MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 175.059MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 175.059MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 175.059MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 175.059MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 175.059MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 175.059MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 175.059MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 175.059MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 175.059MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 175.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 3s, Peak memory usage = 206.203MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 206.203MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 206.203MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 2s, Elapsed time = 0h 0m 3s, Peak memory usage = 206.203MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>28</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>28</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>14</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>14</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>141</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>16</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>36</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>89</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>141(141 LUT, 0 ALU) / 20736</td>
<td><1%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>0 / 46</td>
<td>0%</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Hierarchy Module Resource</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
div#main_wrapper{ width: 100%; }
h1 {text-align: center; }
h1 {margin-top: 36px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { align = "center"; padding: 5px 2px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="content">
<h1>Hierarchy Module Resource</h1>
<table>
<tr>
<th class="label">MODULE NAME</th>
<th class="label">REG NUMBER</th>
<th class="label">ALU NUMBER</th>
<th class="label">LUT NUMBER</th>
<th class="label">DSP NUMBER</th>
<th class="label">BSRAM NUMBER</th>
<th class="label">SSRAM NUMBER</th>
<th class="label">ROM16 NUMBER</th>
</tr>
<tr>
<td class="label">bttn (//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">13</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp|--s1
(//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">128</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<Module name="bttn" Lut="13" T_Lut="141(13)">
<SubModule name="s1" Lut="128" T_Lut="128(128)"/>
</Module>

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Reading netlist file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg"
Parsing netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg" completed
Processing netlist completed
Reading constraint file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst"
Physical Constraint parsed completed
Running placement......
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
[30%] Placement Phase 2 completed
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.power.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.pin.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.rpt.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.rpt.txt" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.tr.html" completed
Mon Jan 20 18:31:08 2025

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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//ENhttp://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Power Analysis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper { width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td {white-space:pre; border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.thermal_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.Configure_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table th.label { min-width: 8%; width: 8%; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#Message" style=" font-size: 16px;">Power Messages</a>
<ul>
<li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li>
</ul>
</li>
<li><a href="#Summary" style=" font-size: 16px;">Power Summary</a>
<ul>
<li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li>
<li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li>
<li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li>
</ul>
</li>
<li><a href="#Detail" style=" font-size: 16px;">Power Details</a>
<ul>
<li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li>
<li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li>
<li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="Message">Power Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Power Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.9.03 Education (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Mon Jan 20 18:31:05 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h2><a name="Configure_Info">Configure Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Grade</td>
<td>Commercial</td>
</tr>
<tr>
<td class="label">Process</td>
<td>Typical</td>
</tr>
<tr>
<td class="label">Ambient Temperature</td>
<td>25.000
</tr>
<tr>
<td class="label">Use Custom Theta JA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Heat Sink</td>
<td>None</td>
</tr>
<tr>
<td class="label">Air Flow</td>
<td>LFM_0</td>
</tr>
<tr>
<td class="label">Use Custom Theta SA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Board Thermal Model</td>
<td>None</td>
</tr>
<tr>
<td class="label">Use Custom Theta JB</td>
<td>false</td>
</tr>
<tr>
<td class="label">Related Vcd File</td>
<td></td>
</tr>
<tr>
<td class="label">Related Saif File</td>
<td></td>
</tr>
<tr>
<td class="label">Filter Glitches</td>
<td>false</td>
</tr>
<tr>
<td class="label">Default IO Toggle Rate</td>
<td>0.125</td>
</tr>
<tr>
<td class="label">Default Remain Toggle Rate</td>
<td>0.125</td>
</tr>
</table>
<h1><a name="Summary">Power Summary</a></h1>
<h2><a name="Power_Info">Power Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Total Power (mW)</td>
<td>124.522</td>
</tr>
<tr>
<td class="label">Quiescent Power (mW)</td>
<td>121.169</td>
</tr>
<tr>
<td class="label">Dynamic Power (mW)</td>
<td>3.353</td>
</tr>
</table>
<h2><a name="Thermal_Info">Thermal Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Junction Temperature</td>
<td>28.987</td>
</tr>
<tr>
<td class="label">Theta JA</td>
<td>32.020</td>
</tr>
<tr>
<td class="label">Max Allowed Ambient Temperature</td>
<td>81.013</td>
</tr>
</table>
<h2><a name="Supply_Summary">Supply Information:</a></h2>
<table class="summary_table">
<tr>
<th class="label">Voltage Source</th>
<th class="label">Voltage</th>
<th class="label">Dynamic Current(mA)</th>
<th class="label">Quiescent Current(mA)</th>
<th class="label">Power(mW)</th>
</tr>
<tr>
<td>VCC</td>
<td>1.000</td>
<td>0.552</td>
<td>69.981</td>
<td>70.533</td>
</tr>
<tr>
<td>VCCX</td>
<td>3.300</td>
<td>0.552</td>
<td>15.000</td>
<td>51.322</td>
</tr>
<tr>
<td>VCCIO18</td>
<td>1.800</td>
<td>0.544</td>
<td>0.938</td>
<td>2.668</td>
</tr>
</table>
<h1><a name="Detail">Power Details</a></h1>
<h2><a name="By_Block_Type">Power By Block Type:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Block Type</th>
<th class="label">Total Power(mW)</th>
<th class="label">Static Power(mW)</th>
<th class="label">Average Toggle Rate(millions of transitions/sec)</th>
</tr>
<tr>
<td>IO</td>
<td>8.544
<td>5.191
<td>6.250
</tr>
</table>
<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Hierarchy Entity</th>
<th class="label">Total Power(mW)</th>
<th class="label">Block Dynamic Power(mW)</th>
</tr>
<tr>
<td>bttn</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>bttn/s1/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
</table>
<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Domain</th>
<th class="label">Clock Frequency(Mhz)</th>
<th class="label">Total Dynamic Power(mW)</th>
</tr>
<tr>
<td>NO CLOCK DOMAIN</td>
<td>0.000</td>
<td>0.000</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
1. PnR Messages
<Report Title>: PnR Report
<Design File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg
<Physical Constraints File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst
<Timing Constraints File>: ---
<Tool Version>: V1.9.9.03 Education (64-bit)
<Part Number>: GW2A-LV18PG256C8/I7
<Device>: GW2A-18
<Device Version>: C
<Created Time>:Mon Jan 20 18:31:08 2025
2. PnR Details
Running placement:
Placement Phase 0: CPU time = 0h 0m 0.025s, Elapsed time = 0h 0m 0.025s
Placement Phase 1: CPU time = 0h 0m 0.346s, Elapsed time = 0h 0m 0.345s
Placement Phase 2: CPU time = 0h 0m 0.008s, Elapsed time = 0h 0m 0.008s
Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Running routing:
Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Routing Phase 1: CPU time = 0h 0m 0.178s, Elapsed time = 0h 0m 0.177s
Routing Phase 2: CPU time = 0h 0m 0.228s, Elapsed time = 0h 0m 0.228s
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Total Routing: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.405s
Generate output files:
CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s
Total Time and Memory Usage: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 433MB
3. Resource Usage Summary
----------------------------------------------------------
Resources | Usage
----------------------------------------------------------
Logic | 141/20736 <1%
--LUT,ALU,ROM16 | 141(141 LUT, 0 ALU, 0 ROM16)
--SSRAM(RAM16) | 0
Register | 0/16173 0%
--Logic Register as Latch | 0/15552 0%
--Logic Register as FF | 0/15552 0%
--I/O Register as Latch | 0/621 0%
--I/O Register as FF | 0/621 0%
CLS | 75/10368 <1%
I/O Port | 28
I/O Buf | 28
--Input Buf | 14
--Output Buf | 14
--Inout Buf | 0
IOLOGIC | 0%
BSRAM | 0%
DSP | 0%
PLL | 0/4 0%
DCS | 0/8 0%
DQCE | 0/24 0%
OSC | 0/1 0%
CLKDIV | 0/8 0%
DLLDLY | 0/8 0%
DQS | 0/9 0%
DHCEN | 0/16 0%
==========================================================
4. I/O Bank Usage Summary
-----------------------
I/O Bank | Usage
-----------------------
bank 0 | 1/29(3%)
bank 1 | 5/20(25%)
bank 2 | 2/20(10%)
bank 3 | 8/32(25%)
bank 4 | 2/36(5%)
bank 5 | 0/36(0%)
bank 6 | 2/18(11%)
bank 7 | 8/16(50%)
=======================
5. Global Clock Usage Summary
-------------------------------
Global Clock | Usage
-------------------------------
PRIMARY | 0/8(0%)
LW | 0/8(0%)
GCLK_PIN | 1/8(13%)
PLL | 0/4(0%)
CLKDIV | 0/8(0%)
DLLDLY | 0/8(0%)
===============================
6. Global Clock Signals
-------------------------------------------
Signal | Global Clock | Location
-------------------------------------------
===========================================
7. Pinout by Port Name
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | BankVccio
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
A[0] | | A11/7 | Y | in | IOL15[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
A[1] | | N6/3 | Y | in | IOR51[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
A[2] | | E15/1 | Y | in | IOT44[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | NA | NA | 1.8
A[3] | | L9/3 | Y | in | IOR40[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
B[0] | | B11/7 | Y | in | IOL13[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
B[1] | | D11/7 | Y | in | IOL22[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
B[2] | | N7/3 | Y | in | IOR47[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
B[3] | | N8/3 | Y | in | IOR40[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
opCodeA[0] | | T5/4 | Y | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
opCodeA[1] | | T4/4 | Y | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
opCodeA[2] | | E8/6 | Y | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
select[0] | | A15/7 | Y | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
select[1] | | A14/7 | Y | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
Cin | | E9/6 | Y | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
leds[0] | | L16/1 | Y | out | IOT34[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
leds[1] | | L14/1 | Y | out | IOT34[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
Y[0] | | P6/3 | Y | out | IOR53[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[1] | | T7/3 | Y | out | IOR29[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[2] | | P8/3 | Y | out | IOR42[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[3] | | P9/3 | Y | out | IOR38[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[4] | | T11/2 | Y | out | IOR24[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[5] | | T12/2 | Y | out | IOR17[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[6] | | M14/1 | Y | out | IOT40[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
Y[7] | | J14/0 | Y | out | IOT22[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
Y[8] | | D14/1 | Y | out | IOT44[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
Y[9] | | B14/7 | Y | out | IOL2[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[10] | | B13/7 | Y | out | IOL8[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[11] | | B12/7 | Y | out | IOL7[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
===================================================================================================================================================================================================================
8. All Package Pins
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | Bank Vccio
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
L15/0 | - | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D16/0 | - | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E14/0 | - | in | IOT4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C16/0 | - | in | IOT5[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D15/0 | - | in | IOT5[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E16/0 | - | in | IOT6[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F15/0 | - | in | IOT6[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F13/0 | - | in | IOT8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G12/0 | - | in | IOT8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F14/0 | - | in | IOT9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F16/0 | - | in | IOT9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F12/0 | - | in | IOT12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G13/0 | - | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G15/0 | - | in | IOT13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G14/0 | - | in | IOT13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G11/0 | - | in | IOT14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H12/0 | - | in | IOT14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G16/0 | - | in | IOT16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H15/0 | - | in | IOT16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H13/0 | - | in | IOT18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J12/0 | - | in | IOT18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H14/0 | - | in | IOT20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H16/0 | - | in | IOT20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J16/0 | - | in | IOT22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J14/0 | Y[7] | out | IOT22[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
J15/0 | - | in | IOT24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K16/0 | - | in | IOT24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H11/0 | - | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J13/0 | - | in | IOT27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K14/1 | - | in | IOT30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K15/1 | - | in | IOT30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J11/1 | - | in | IOT32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L12/1 | - | in | IOT32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L16/1 | leds[0] | out | IOT34[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
L14/1 | leds[1] | out | IOT34[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
K13/1 | - | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K12/1 | - | in | IOT36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K11/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L13/1 | - | in | IOT38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M14/1 | Y[6] | out | IOT40[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
M15/1 | - | in | IOT40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D14/1 | Y[8] | out | IOT44[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
E15/1 | A[2] | in | IOT44[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | NA | NA | 1.8
N15/1 | - | in | IOT48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P16/1 | - | in | IOT48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N16/1 | - | in | IOT52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N14/1 | - | in | IOT52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P15/1 | - | in | IOT54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R16/1 | - | in | IOT54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
A4/5 | - | in | IOB2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C5/5 | - | in | IOB2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D6/5 | - | in | IOB3[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E7/5 | - | in | IOB3[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A3/5 | - | in | IOB4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B4/5 | - | in | IOB4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A5/5 | - | in | IOB7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B6/5 | - | in | IOB7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B1/5 | - | in | IOB8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C2/5 | - | in | IOB8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D3/5 | - | in | IOB9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D1/5 | - | in | IOB9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E2/5 | - | in | IOB12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E3/5 | - | in | IOB12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B3/5 | - | in | IOB13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A2/5 | - | in | IOB13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C1/5 | - | in | IOB14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D2/5 | - | in | IOB14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E1/5 | - | in | IOB16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F2/5 | - | in | IOB16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F4/5 | - | in | IOB18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G6/5 | - | in | IOB18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F3/5 | - | in | IOB19[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F1/5 | - | in | IOB19[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G5/5 | - | in | IOB20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G4/5 | - | in | IOB20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G2/5 | - | in | IOB21[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G3/5 | - | in | IOB21[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F5/5 | - | in | IOB22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H6/5 | - | in | IOB22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G1/5 | - | in | IOB24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H2/5 | - | in | IOB24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H4/5 | - | in | IOB26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J6/5 | - | in | IOB26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J1/5 | - | in | IOB27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J3/5 | - | in | IOB27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L2/4 | - | in | IOB30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M1/4 | - | in | IOB30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H3/4 | - | in | IOB32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H1/4 | - | in | IOB32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J2/4 | - | in | IOB34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K1/4 | - | in | IOB34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H5/4 | - | in | IOB35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J4/4 | - | in | IOB35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K3/4 | - | in | IOB36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K2/4 | - | in | IOB36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J5/4 | - | in | IOB37[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K6/4 | - | in | IOB37[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L1/4 | - | in | IOB38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L3/4 | - | in | IOB38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K4/4 | - | in | IOB39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L5/4 | - | in | IOB39[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K5/4 | - | in | IOB40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L4/4 | - | in | IOB40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N2/4 | - | in | IOB41[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P1/4 | - | in | IOB41[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M3/4 | - | in | IOB42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N1/4 | - | in | IOB42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M2/4 | - | in | IOB43[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N3/4 | - | in | IOB43[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R1/4 | - | in | IOB44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P2/4 | - | in | IOB44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P4/4 | - | in | IOB45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T4/4 | opCodeA[1] | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R3/4 | - | in | IOB48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T2/4 | - | in | IOB48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P5/4 | - | in | IOB50[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R5/4 | - | in | IOB50[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R4/4 | - | in | IOB52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T3/4 | - | in | IOB52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R6/4 | - | in | IOB54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T5/4 | opCodeA[0] | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
B14/7 | Y[9] | out | IOL2[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
A15/7 | select[0] | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
C12/7 | - | in | IOL7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B12/7 | Y[11] | out | IOL7[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
B13/7 | Y[10] | out | IOL8[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
A14/7 | select[1] | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
F10/7 | - | in | IOL11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B11/7 | B[0] | in | IOL13[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
A12/7 | - | in | IOL13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A11/7 | A[0] | in | IOL15[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
C11/7 | - | in | IOL15[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D10/7 | - | in | IOL17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E10/7 | - | in | IOL17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D11/7 | B[1] | in | IOL22[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
A9/7 | - | in | IOL27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C9/7 | - | in | IOL27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C8/6 | - | in | IOL29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A8/6 | - | in | IOL29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F9/6 | - | in | IOL31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E11/6 | - | in | IOL31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B9/6 | - | in | IOL33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A10/6 | - | in | IOL33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F8/6 | - | in | IOL35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D9/6 | - | in | IOL35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D8/6 | - | in | IOL38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E9/6 | Cin | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
B7/6 | - | in | IOL40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C7/6 | - | in | IOL40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F7/6 | - | in | IOL45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E8/6 | opCodeA[2] | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
C4/6 | - | in | IOL47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B5/6 | - | in | IOL47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E6/6 | - | in | IOL53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D7/6 | - | in | IOL53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
T15/2 | - | in | IOR7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R14/2 | - | in | IOR7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P12/2 | - | in | IOR8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T13/2 | - | in | IOR8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R12/2 | - | in | IOR11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P13/2 | - | in | IOR11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R11/2 | - | in | IOR17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T12/2 | Y[5] | out | IOR17[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
R13/2 | - | in | IOR20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T14/2 | - | in | IOR20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M10/2 | - | in | IOR22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N11/2 | - | in | IOR22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T11/2 | Y[4] | out | IOR24[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
P11/2 | - | in | IOR24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C6/2 | - | out | IOR25[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
B8/2 | - | in | IOR25[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A7/2 | - | in | IOR26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A6/2 | - | in | IOR26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N10/2 | - | in | IOR27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M11/2 | - | in | IOR27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T7/3 | Y[1] | out | IOR29[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
R8/3 | - | in | IOR29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M16/3 | - | in | IOR30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B16/3 | - | in | IOR30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C15/3 | - | in | IOR31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B10/3 | - | in | IOR31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A13/3 | - | in | IOR32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C13/3 | - | in | IOR32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P10/3 | - | in | IOR33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R10/3 | - | in | IOR33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M9/3 | - | in | IOR34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L10/3 | - | in | IOR34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R9/3 | - | in | IOR35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T10/3 | - | in | IOR35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M8/3 | - | in | IOR36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N9/3 | - | in | IOR36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T9/3 | - | in | IOR38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P9/3 | Y[3] | out | IOR38[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
C10/3 | - | in | IOR39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N8/3 | B[3] | in | IOR40[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
L9/3 | A[3] | in | IOR40[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
P8/3 | Y[2] | out | IOR42[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
T8/3 | - | in | IOR42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M6/3 | - | in | IOR44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L8/3 | - | in | IOR44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M7/3 | - | in | IOR47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N7/3 | B[2] | in | IOR47[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
R7/3 | - | in | IOR49[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P7/3 | - | in | IOR49[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N6/3 | A[1] | in | IOR51[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
P6/3 | Y[0] | out | IOR53[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
T6/3 | - | in | IOR53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
========================================================================================================================================================================================

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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.9.03 Education (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Mon Jan 20 18:31:08 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.95V 85C C8/I7</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.05V 0C C8/I7</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>158</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>14</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
</table>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h4>Nothing to report!</h4>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h4>No setup paths to report!</h4>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h4>No hold paths to report!</h4>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>No recovery paths to report!</h4>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>No removal paths to report!</h4>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h4>Nothing to report!</h4>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R27C30</td>
<td>43.06%</td>
</tr>
<tr>
<td>R29C29</td>
<td>43.06%</td>
</tr>
<tr>
<td>R27C29</td>
<td>40.28%</td>
</tr>
<tr>
<td>R26C29</td>
<td>33.33%</td>
</tr>
<tr>
<td>R26C30</td>
<td>31.94%</td>
</tr>
<tr>
<td>R29C28</td>
<td>30.56%</td>
</tr>
<tr>
<td>R29C30</td>
<td>29.17%</td>
</tr>
<tr>
<td>R27C28</td>
<td>26.39%</td>
</tr>
<tr>
<td>R27C31</td>
<td>25.00%</td>
</tr>
<tr>
<td>R26C28</td>
<td>25.00%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
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-d \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg
-p GW2A-18C-PBGA256-8
-pn GW2A-LV18PG256C8/I7
-cst \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst
-cfg \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\device.cfg
-bit
-tr
-ph
-timing
-cst_error
-correct_hold 1
-route_maxfan 23
-global_freq 100.000

2
gowin/bttn/impl/pnr/cmd.doZone.Identifier Normal file
View File

@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

21
gowin/bttn/impl/pnr/device.cfg Normal file
View File

@ -0,0 +1,21 @@
set JTAG regular_io = false
set SSPI regular_io = false
set MSPI regular_io = false
set READY regular_io = false
set DONE regular_io = false
set I2C regular_io = false
set RECONFIG_N regular_io = false
set CRC_check = true
set compress = false
set encryption = false
set security_bit_enable = true
set bsram_init_fuse_print = true
set background_programming = off
set secure_mode = false
set program_done_bypass = false
set wake_up = 0
set format = binary
set power_on_reset_monitor = true
set multiboot_spi_flash_address = 0x00000000
set vccx = 3.3
set unused_pin = default

2
gowin/bttn/impl/pnr/device.cfgZone.Identifier Normal file
View File

@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

330
gowin/bttn/impl/temp/rtl_parser.result
View File

@ -1,148 +1,143 @@
[
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"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
"InstLine" : 1,
"InstName" : "bttn",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
"ModuleLine" : 1,
"ModuleName" : "bttn",
"SubInsts" : [
{
<<<<<<< HEAD
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
"InstLine" : 11,
=======
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
"InstLine" : 10,
>>>>>>> 15916a2c534beff06a16239dd4912b40b7f837b6
"InstLine" : 13,
"InstName" : "a1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
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"ModuleName" : "ALU",
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"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/opCode.v",
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},
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}
]
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{
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},
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}
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},
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}
]
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{
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"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
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},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
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"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
@ -151,112 +146,112 @@
]
},
{
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"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
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},
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}
@ -267,128 +262,128 @@
]
},
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"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
@ -627,66 +622,66 @@
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
"InstLine" : 76,
"InstName" : "btod1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"ModuleLine" : 1,
"ModuleName" : "BinaryToBCD",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 14,
"InstName" : "d1t",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 23,
"InstName" : "d2u",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 32,
"InstName" : "d3v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 41,
"InstName" : "d4w",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 50,
"InstName" : "d5x",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 59,
"InstName" : "d6y",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 68,
"InstName" : "d7z",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
}
@ -695,15 +690,10 @@
]
},
{
<<<<<<< HEAD
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
"InstLine" : 12,
=======
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
"InstLine" : 11,
>>>>>>> 15916a2c534beff06a16239dd4912b40b7f837b6
"InstLine" : 14,
"InstName" : "s1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/selector.v",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/selector.v",
"ModuleLine" : 1,
"ModuleName" : "selector"
}

2
gowin/bttn/impl/temp/rtl_parser.resultZone.Identifier Normal file
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@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

32
gowin/bttn/impl/temp/rtl_parser_arg.json
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@ -2,63 +2,63 @@
"Device" : "GW2A-18C",
"Files" : [
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/logicUnit.v",
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/logicUnit.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/multiplier.v",
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/opCode.v",
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/opCode.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/selector.v",
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/selector.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
"Type" : "verilog"
}
],
@ -66,7 +66,7 @@
],
"LoopLimit" : 2000,
"ResultFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/impl/temp/rtl_parser.result",
"ResultFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/impl/temp/rtl_parser.result",
"Top" : "",
"VerilogStd" : "verilog_2001",
"VhdlStd" : "vhdl_93"

2
gowin/bttn/impl/temp/rtl_parser_arg.jsonZone.Identifier Normal file
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@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

0
gowin/bttn/impl/temp/style.css Normal file
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2
gowin/bttn/impl/temp/style.cssZone.Identifier Normal file
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@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

79
gowin/bttn/src/ALU.v Normal file
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@ -0,0 +1,79 @@
module ALU (
input [3:0] A, B,
input CarryIN,
input [2:0] opCodeA,
output [11:0] bcd,
output CarryOUT, overflow
);
// Supports: ADD[0], SUB[1], MULT[2], AND[4], OR[5], XOR[6]
wire [7:0] opCode8;
wire [3:0] add_Y, sub_Y;
wire [3:0] resultA, resultO, resultX, lUOutput1;
wire [3:0] aUtemp1, aUtemp2, lUOutput2;
wire [3:0] wireY, wireLA;
wire [7:0] opwireM, wireM, Y;
opCode opCd (.A(opCodeA), .opCode(opCode8));
arithmeticUnit aU(.opCode(opCode8[1:0]), .A(A), .B(B), .CarryIN(CarryIN), .add_Y(add_Y), .sub_Y(sub_Y), .CarryOUT(CarryOUT), .overflow(overflow));
logicUnit lU (.opCode(opCode8[6:4]), .A(A), .B(B), .resultA(resultA), .resultO(resultO), .resultX(resultX));
multiplier mU (.A(A), .B(B), .Y(opwireM));
or o01 (lUOutput1[0], resultA[0], resultO[0]);
or o02 (lUOutput1[1], resultA[1], resultO[1]);
or o03 (lUOutput1[2], resultA[2], resultO[2]);
or o04 (lUOutput1[3], resultA[3], resultO[3]);
or o11 (lUOutput2[0], lUOutput1[0], resultX[0]);
or o12 (lUOutput2[1], lUOutput1[1], resultX[1]);
or o13 (lUOutput2[2], lUOutput1[2], resultX[2]);
or o14 (lUOutput2[3], lUOutput1[3], resultX[3]);
and a01 (aUtemp1[0], opCode8[0], add_Y[0]);
and a02 (aUtemp1[1], opCode8[0], add_Y[1]);
and a03 (aUtemp1[2], opCode8[0], add_Y[2]);
and a04 (aUtemp1[3], opCode8[0], add_Y[3]);
and a11 (aUtemp2[0], opCode8[1], sub_Y[0]);
and a12 (aUtemp2[1], opCode8[1], sub_Y[1]);
and a13 (aUtemp2[2], opCode8[1], sub_Y[2]);
and a14 (aUtemp2[3], opCode8[1], sub_Y[3]);
and a21 (wireM[0], opCode8[2], opwireM[0]);
and a22 (wireM[1], opCode8[2], opwireM[1]);
and a23 (wireM[2], opCode8[2], opwireM[2]);
and a24 (wireM[3], opCode8[2], opwireM[3]);
and a25 (wireM[4], opCode8[2], opwireM[4]);
and a26 (wireM[5], opCode8[2], opwireM[5]);
and a27 (wireM[6], opCode8[2], opwireM[6]);
and a28 (wireM[7], opCode8[2], opwireM[7]);
or o21 (wireY[0], aUtemp1[0], aUtemp2[0]);
or o22 (wireY[1], aUtemp1[1], aUtemp2[1]);
or o23 (wireY[2], aUtemp1[2], aUtemp2[2]);
or o24 (wireY[3], aUtemp1[3], aUtemp2[3]);
or o1 (wireLA[0], lUOutput2[0], wireY[0]);
or o2 (wireLA[1], lUOutput2[1], wireY[1]);
or o3 (wireLA[2], lUOutput2[2], wireY[2]);
or o4 (wireLA[3], lUOutput2[3], wireY[3]);
or o31 (Y[0], wireLA[0], wireM[0]);
or o32 (Y[1], wireLA[1], wireM[1]);
or o33 (Y[2], wireLA[2], wireM[2]);
or o34 (Y[3], wireLA[3], wireM[3]);
or o35 (Y[4], 1'b0, wireM[4]);
or o36 (Y[5], 1'b0, wireM[5]);
or o37 (Y[6], 1'b0, wireM[6]);
or o38 (Y[7], 1'b0, wireM[7]);
BinaryToBCD btod1(.binary(Y), .bcd(bcd)); // WIRE Y BINARY!!!!
endmodule

2
gowin/bttn/src/ALU.vZone.Identifier Normal file
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@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

79
gowin/bttn/src/BinaryToBCD.v Normal file
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@ -0,0 +1,79 @@
module BinaryToBCD (
input [7:0] binary,
output [11:0] bcd
);
wire empty1, empty2;
wire [3:0] dab1, dab2, dab3, dab4, dab5;
and a111 (empty1, 1'b0, 1'b0);
and a000 (empty2, 1'b0, 1'b0);
and a222 (bcd[11], 1'b0, 1'b0);
and a223 (bcd[10], 1'b0, 1'b0);
dabble d1t (.A((empty1)),
.B(binary[7]),
.C(binary[6]),
.D(binary[5]),
.X(dab1[0]),
.Y(dab1[1]),
.Z(dab1[2]),
.E(dab1[3]));
dabble d2u (.A((dab1[1])),
.B(dab1[2]),
.C(dab1[3]),
.D(binary[4]),
.X(dab2[0]),
.Y(dab2[1]),
.Z(dab2[2]),
.E(dab2[3]));
dabble d3v (.A((dab2[1])),
.B(dab2[2]),
.C(dab2[3]),
.D(binary[3]),
.X(dab3[0]),
.Y(dab3[1]),
.Z(dab3[2]),
.E(dab3[3]));
dabble d4w (.A((empty2)),
.B(dab1[0]),
.C(dab2[0]),
.D(dab3[0]),
.X(bcd[9]),
.Y(dab4[1]),
.Z(dab4[2]),
.E(dab4[3]));
dabble d5x (.A((dab3[1])),
.B(dab3[2]),
.C(dab3[3]),
.D(binary[2]),
.X(dab5[0]),
.Y(dab5[1]),
.Z(dab5[2]),
.E(dab5[3]));
dabble d6y (.A((dab4[1])),
.B(dab4[2]),
.C(dab4[3]),
.D(dab5[0]),
.X(bcd[8]),
.Y(bcd[7]),
.Z(bcd[6]),
.E(bcd[5]));
dabble d7z (.A((dab5[1])),
.B(dab5[2]),
.C(dab5[3]),
.D(binary[1]),
.X(bcd[4]),
.Y(bcd[3]),
.Z(bcd[2]),
.E(bcd[1]));
or o1 (bcd[0], binary[0], 1'b0);
endmodule

2
gowin/bttn/src/BinaryToBCD.vZone.Identifier Normal file
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@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

20
gowin/bttn/src/addition.v Normal file
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@ -0,0 +1,20 @@
module addition (
input [3:0] A, B,
input CarryIN,
output [3:0] Y,
output CarryOUT,
output overflow
);
wire [2:0] Carry4;
fulladder f0(.A(A[0]), .B(B[0]), .Carry(CarryIN), .Sum(Y[0]), .CarryO(Carry4[0]));
fulladder f1(.A(A[1]), .B(B[1]), .Carry(Carry4[0]), .Sum(Y[1]), .CarryO(Carry4[1]));
fulladder f2(.A(A[2]), .B(B[2]), .Carry(Carry4[1]), .Sum(Y[2]), .CarryO(Carry4[2]));
fulladder f3(.A(A[3]), .B(B[3]), .Carry(Carry4[2]), .Sum(Y[3]), .CarryO(CarryOUT));
//overflowDetect od1 (.opCode(2'b01), .A(A), .B(B), .Y(Y), .CarryOUT(CarryOUT), .overflowDetect(overflow)); (KULLANILMAYACAK!!!!)
xor ov1 (overflow, Carry4[2], CarryOUT);
endmodule

2
gowin/bttn/src/addition.vZone.Identifier Normal file
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@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

33
gowin/bttn/src/arithmeticUnit.v Normal file
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@ -0,0 +1,33 @@
module arithmeticUnit (
input [1:0] opCode,
input [3:0] A, B,
input CarryIN,
output [3:0] add_Y, sub_Y,
output CarryOUT,
output overflow
);
wire [3:0] addY, subY;
wire CarryOUTADD, CarryOUTSUB, tempCAdd, tempCSub, tempoverflow;
addition a1(.A(A), .B(B), .CarryIN(CarryIN), .Y(addY), .CarryOUT(CarryOUTADD), .overflow(tempoverflow));
subtraction s1(.A(A), .B(B), .BorrowIN(CarryIN), .Y(subY), .BorrowOUT(CarryOUTSUB));
and add1 (add_Y[0], opCode[0], addY[0]);
and add2 (add_Y[1], opCode[0], addY[1]);
and add3 (add_Y[2], opCode[0], addY[2]);
and add4 (add_Y[3], opCode[0], addY[3]);
and sub1 (sub_Y[0], opCode[1], subY[0]);
and sub2 (sub_Y[1], opCode[1], subY[1]);
and sub3 (sub_Y[2], opCode[1], subY[2]);
and sub4 (sub_Y[3], opCode[1], subY[3]);
// or or1 (CarryOUT, CarryOUTADD, CarryOUTSUB); (OLD!!!)
and and10 (tempCSub, CarryOUTSUB, opCode[1]);
and and11 (tempCAdd, CarryOUTADD, opCode[0]);
or or4 (CarryOUT, tempCAdd, tempCSub);
and add12 (overflow, opCode[0], tempoverflow);
endmodule

2
gowin/bttn/src/arithmeticUnit.vZone.Identifier Normal file
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@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

2191
gowin/bttn/src/bttn Normal file
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File diff suppressed because it is too large Load Diff

65
gowin/bttn/src/bttn.cst Normal file
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@ -0,0 +1,65 @@
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Physical Constraints file
//Tool Version: V1.9.9.03 Education (64-bit)
//Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18
//Device Version: C
//Created Time: Mon 01 20 17:48:00 2025
IO_LOC "Y[11]" B12;
IO_PORT "Y[11]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[10]" B13;
IO_PORT "Y[10]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[9]" B14;
IO_PORT "Y[9]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[8]" D14;
IO_PORT "Y[8]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[7]" J14;
IO_PORT "Y[7]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[6]" M14;
IO_PORT "Y[6]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[5]" T12;
IO_PORT "Y[5]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[4]" T11;
IO_PORT "Y[4]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[3]" P9;
IO_PORT "Y[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[2]" P8;
IO_PORT "Y[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[1]" T7;
IO_PORT "Y[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[0]" P6;
IO_PORT "Y[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[1]" L14;
IO_PORT "leds[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[0]" L16;
IO_PORT "leds[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Cin" E9;
IO_PORT "Cin" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "select[1]" A14;
IO_PORT "select[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "select[0]" A15;
IO_PORT "select[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[2]" E8;
IO_PORT "opCodeA[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[1]" T4;
IO_PORT "opCodeA[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[0]" T5;
IO_PORT "opCodeA[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "B[3]" N8;
IO_PORT "B[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[2]" N7;
IO_PORT "B[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[1]" D11;
IO_PORT "B[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[0]" B11;
IO_PORT "B[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[3]" L9;
IO_PORT "A[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[2]" E15;
IO_PORT "A[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[1]" N6;
IO_PORT "A[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[0]" A11;
IO_PORT "A[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;

2
gowin/bttn/src/bttn.cstZone.Identifier Normal file
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@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

19
gowin/bttn/src/bttn.v Normal file
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module bttn (
input [3:0] A, B,
input [2:0] opCodeA,
input [1:0] select,
input Cin,
output [1:0] leds,
output [11:0] Y
);
wire wire1, wire2;
wire [11:0] selectY;
ALU a1(.A(A), .B(B), .opCodeA(opCodeA), .CarryIN(Cin), .bcd(selectY), .CarryOUT(wire2), .overflow(wire1));
selector s1(.A(A), .B(B), .opCodeA(opCodeA), .select(select), .ALUY(selectY), .Y(Y));
assign leds[0] = ~wire1;
assign leds[1] = ~wire2;
endmodule

1103
gowin/bttn/src/bttn.vcd Normal file
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2
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@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

2
gowin/bttn/src/bttn.vZone.Identifier Normal file
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@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

23
gowin/bttn/src/bttnTB.v Normal file
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module bttnTB();
reg [3:0] A,B;
reg [2:0] opCodeA;
reg [1:0] select;
wire [11:0] Y;
bttn uut (
.A(A),
.B(B),
.opCodeA(opCodeA),
.select(select),
.Y(Y)
);
initial begin
$dumpfile("bttn.vcd");
$dumpvars;
A = 4'b0001; B = 4'b0110; opCodeA = 3'b000; select = 2'b01; #5;
$finish;
end
endmodule

2
gowin/bttn/src/bttnTB.vZone.Identifier Normal file
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[ZoneTransfer]
ZoneId=3

2
gowin/bttn/src/bttnZone.Identifier Normal file
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@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

22
gowin/bttn/src/dabble.v Normal file
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module dabble (
input A, B, C, D,
output X, Y, Z, E
);
wire xor1, nor1, xor2, nor2, nor3, or1;
xor xo1 (xor1, A, D);
nor no1 (nor1, A, B);
xor xo2 (xor2, A, C);
nor no2 (nor2, xor1, xor2);
nor no3 (nor3, nor2, nor1);
buf bu1 (X, nor3);
or o1 (or1, xor1, nor1);
nor no4 (Y, or1, C);
and an1 (Z, or1, xor2);
xor xo3 (E, nor3, D);
endmodule

2
gowin/bttn/src/dabble.vZone.Identifier Normal file
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[ZoneTransfer]
ZoneId=3

12
gowin/bttn/src/fulladder.v Normal file
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module fulladder (
input A, B, Carry,
output Sum, CarryO
);
wire xor1, and1, and2;
halfadder h1(.A(A), .B(B), .Sum(xor1), .Carry(and1));
halfadder h2 (.A(xor1), .B(Carry), .Sum(Sum), .Carry(and2));
or o1 (CarryO, and1, and2);
endmodule

2
gowin/bttn/src/fulladder.vZone.Identifier Normal file
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[ZoneTransfer]
ZoneId=3

12
gowin/bttn/src/fullsubtraction.v Normal file
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module fullsubtraction (
input A, B, BorrowIN,
output Difference, BorrowOut
);
wire tempD, tempB1, tempB2;
halfsubtraction hf1(.A(A), .B(B), .Difference(tempD), .Borrow(tempB1));
halfsubtraction hf2(.A(tempD), .B(BorrowIN), .Difference(Difference), .Borrow(tempB2));
or o1 (BorrowOut, tempB1, tempB2);
endmodule

2
gowin/bttn/src/fullsubtraction.vZone.Identifier Normal file
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[ZoneTransfer]
ZoneId=3

9
gowin/bttn/src/halfadder.v Normal file
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module halfadder (
input A, B,
output Sum, Carry
);
and a1 (Carry, A, B);
xor xo1 (Sum, A, B);
endmodule

2
gowin/bttn/src/halfadder.vZone.Identifier Normal file
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[ZoneTransfer]
ZoneId=3

12
gowin/bttn/src/halfsubtraction.v Normal file
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module halfsubtraction (
input A, B,
output Difference, Borrow
);
wire notA;
xor xo1 (Difference, A, B);
not a1 (notA, A);
and an1 (Borrow, notA, B);
endmodule

2
gowin/bttn/src/halfsubtraction.vZone.Identifier Normal file
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[ZoneTransfer]
ZoneId=3

39
gowin/bttn/src/logicUnit.v Normal file
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module logicUnit (
input [2:0] opCode,
input [3:0] A, B,
output [3:0] resultA, resultO, resultX
);
wire [3:0] and1, or1, xor1;
and a01 (and1[0], A[0], B[0]);
and a02 (and1[1], A[1], B[1]);
and a03 (and1[2], A[2], B[2]);
and a04 (and1[3], A[3], B[3]);
or o01 (or1[0], A[0], B[0]);
or o02 (or1[1], A[1], B[1]);
or o03 (or1[2], A[2], B[2]);
or o04 (or1[3], A[3], B[3]);
xor xor01 (xor1[0], A[0], B[0]);
xor xor02 (xor1[1], A[1], B[1]);
xor xor03 (xor1[2], A[2], B[2]);
xor xor04 (xor1[3], A[3], B[3]);
and a_o1 (resultA[0], opCode[0], and1[0]);
and a_o2 (resultA[1], opCode[0], and1[1]);
and a_o3 (resultA[2], opCode[0], and1[2]);
and a_o4 (resultA[3], opCode[0], and1[3]);
and o_o1 (resultO[0], opCode[1], or1[0]);
and o_o2 (resultO[1], opCode[1], or1[1]);
and o_o3 (resultO[2], opCode[1], or1[2]);
and o_o4 (resultO[3], opCode[1], or1[3]);
and x_o1 (resultX[0], opCode[2], xor1[0]);
and x_o2 (resultX[1], opCode[2], xor1[1]);
and x_o3 (resultX[2], opCode[2], xor1[2]);
and x_o4 (resultX[3], opCode[2], xor1[3]);
endmodule

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[ZoneTransfer]
ZoneId=3

76
gowin/bttn/src/multiplier.v Normal file
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module multiplier (
input [3:0] A, B,
output [7:0] Y
);
wire [3:0] b0, a0, a1, a2;
wire [4:0] S0, S1, S2;
wire carry0, carry1, carry2;
wire overflow0, overflow1, overflow2;
// Partial product generation
and (Y[0], A[0], B[0]); // LSB of the result
// Generate partial products for B[0] and B[1]
and ab00 (b0[0], A[1], B[0]);
and ab01 (b0[1], A[2], B[0]);
and ab02 (b0[2], A[3], B[0]);
not ab03 (b0[3], 1'b1); // Initialize b0[3] to 0
and aa00 (a0[0], A[0], B[1]);
and aa01 (a0[1], A[1], B[1]);
and aa02 (a0[2], A[2], B[1]);
and aa03 (a0[3], A[3], B[1]);
// First addition
addition add0 (
.A(a0),
.B(b0),
.CarryIN(1'b0),
.Y(S0[3:0]),
.CarryOUT(S0[4]),
.overflow(overflow0)
);
// Generate partial products for B[2]
and aa10 (a1[0], A[0], B[2]);
and aa11 (a1[1], A[1], B[2]);
and aa12 (a1[2], A[2], B[2]);
and aa13 (a1[3], A[3], B[2]);
// Second addition
addition add1 (
.A(a1),
.B(S0[4:1]),
.CarryIN(1'b0),
.Y(S1[3:0]),
.CarryOUT(S1[4]),
.overflow(overflow1)
);
// Generate partial products for B[3]
and aa20 (a2[0], A[0], B[3]);
and aa21 (a2[1], A[1], B[3]);
and aa22 (a2[2], A[2], B[3]);
and aa23 (a2[3], A[3], B[3]);
// Third addition
addition add2 (
.A(a2),
.B(S1[4:1]),
.CarryIN(1'b0),
.Y(S2[3:0]),
.CarryOUT(S2[4]),
.overflow(overflow2)
);
// Combine results into the final output Y
or o01 (Y[1], S0[0], 1'b0);
or o02 (Y[2], S1[0], 1'b0);
or o03 (Y[3], S2[0], 1'b0);
or o04 (Y[4], S2[1], 1'b0);
or o05 (Y[5], S2[2], 1'b0);
or o06 (Y[6], S2[3], 1'b0);
or o07 (Y[7], S2[4], 1'b0);
endmodule

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[ZoneTransfer]
ZoneId=3

25
gowin/bttn/src/opCode.v Normal file
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module opCode (
input [2:0] A,
output [7:0] opCode
);
wire and1, and2, and3, and4, notA, notB, notC;
not n1(notA, A[2]);
not n2(notB, A[1]);
not n3(notC, A[0]);
and a01(and1, A[2], A[1]);
and a02(and2, notA, A[1]);
and a03(and3, A[2], notB);
and a04(and4, notA, notB);
and a1(opCode[0], and4, notC);
and a2(opCode[1], and4, A[0]);
and a3(opCode[2], and2, notC);
and a4(opCode[3], and2, A[0]);
and a5(opCode[4], and3, notC);
and a6(opCode[5], and3, A[0]);
and a7(opCode[6], and1, notC);
and a8(opCode[7], and1, A[0]);
endmodule

2
gowin/bttn/src/opCode.vZone.Identifier Normal file
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[ZoneTransfer]
ZoneId=3

20
gowin/bttn/src/selector.v Normal file
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module selector (
input [3:0] A,
input [3:0] B,
input [2:0] opCodeA,
input [1:0] select,
input [11:0] ALUY,
output reg [11:0] Y
);
always @(*) begin
case (select)
2'b00: Y = {8'b00000000, A}; // Zero-extend A to 8 bits
2'b01: Y = {8'b00000000, B}; // Zero-extend B to 8 bits
2'b10: Y = {9'b000000000, opCodeA}; // Zero-extend opCodeA to 8 bits
2'b11: Y = ALUY; // Directly assign ALUY
default: Y = ALUY; // Default case for safety
endcase
end
endmodule

2
gowin/bttn/src/selector.vZone.Identifier Normal file
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[ZoneTransfer]
ZoneId=3

16
gowin/bttn/src/subtraction.v Normal file
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module subtraction (
input [3:0] A, B,
input BorrowIN,
output [3:0] Y,
output BorrowOUT //Overflow signal'ini yani negatif gonderecek
);
wire [3:0] tempB;
// Full Subtraction logic for each bit (borrow-in for each subsequent bit)
fullsubtraction f0 (.A(A[0]), .B(B[0]), .BorrowIN(BorrowIN), .Difference(Y[0]), .BorrowOut(tempB[0]));
fullsubtraction f1 (.A(A[1]), .B(B[1]), .BorrowIN(tempB[0]), .Difference(Y[1]), .BorrowOut(tempB[1]));
fullsubtraction f2 (.A(A[2]), .B(B[2]), .BorrowIN(tempB[1]), .Difference(Y[2]), .BorrowOut(tempB[2]));
fullsubtraction f3 (.A(A[3]), .B(B[3]), .BorrowIN(tempB[2]), .Difference(Y[3]), .BorrowOut(BorrowOUT));
endmodule

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gowin/bttn/src/subtraction.vZone.Identifier Normal file
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[ZoneTransfer]
ZoneId=3