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f# fix

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This commit is contained in:
k0rrluna 2025-01-23 07:58:44 +03:00
parent 8003e7f253
commit 0f359fa8a4
76 changed files with 2250 additions and 19410 deletions
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4
gowin/bttn/bttn.gprj
View File

@ -9,7 +9,6 @@
<File path="src/BinaryToBCD.v" type="file.verilog" enable="1"/>
<File path="src/addition.v" type="file.verilog" enable="1"/>
<File path="src/arithmeticUnit.v" type="file.verilog" enable="1"/>
<File path="src/bttn.v" type="file.verilog" enable="1"/>
<File path="src/dabble.v" type="file.verilog" enable="1"/>
<File path="src/fulladder.v" type="file.verilog" enable="1"/>
<File path="src/fullsubtraction.v" type="file.verilog" enable="1"/>
@ -20,6 +19,7 @@
<File path="src/opCode.v" type="file.verilog" enable="1"/>
<File path="src/selector.v" type="file.verilog" enable="1"/>
<File path="src/subtraction.v" type="file.verilog" enable="1"/>
<File path="src/bttn.cst" type="file.cst" enable="1"/>
<File path="src/top.v" type="file.verilog" enable="1"/>
<File path="src/top.cst" type="file.cst" enable="1"/>
</FileList>
</Project>

5
gowin/bttn/bttn.gprj.user
View File

@ -7,6 +7,8 @@
<Process ID="Pnr" State="2"/>
<Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/>
<Process ID="Gvio" State="2"/>
<Process ID="Place" State="2"/>
</FlowState>
<ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/bttn.vg"/>
@ -20,5 +22,6 @@
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/bttn_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/bttn_syn_rsc.xml"/>
</ResultFileList>
<Ui>000000ff00000001fd00000002000000000000018e0000051efc0200000001fc000000630000051e0000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff00000000000000000000000300000ab000000145fc0100000001fc0000000000000ab0000000da00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000009e00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000da00ffffff0000091a0000051e00000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000bdffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c007301000001a5ffffffff0000000000000000</Ui>
<Ui>000000ff00000001fd00000002000000000000018e0000025dfc0200000001fc000000370000025d0000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000078000000145fc0100000001fc0000000000000780000000a100fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100ffffff000005ee0000025d00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000000000280043006f00720065002e0054006f006f006c006200610072002e00500072006f00630065007300730100000245ffffffff0000000000000000</Ui>
<FpUi></FpUi>
</UserConfig>

2
gowin/bttn/bttn.gprj.userZone.Identifier
View File

@ -1,2 +0,0 @@
[ZoneTransfer]
ZoneId=3

2
gowin/bttn/bttn.gprjZone.Identifier
View File

@ -1,2 +0,0 @@
[ZoneTransfer]
ZoneId=3

88
gowin/bttn/impl/bttn_process_config.json
View File

@ -1,88 +0,0 @@
{
"BACKGROUND_PROGRAMMING" : "off",
"COMPRESS" : false,
"CPU" : false,
"CRC_CHECK" : true,
"Clock_Route_Order" : 0,
"Correct_Hold_Violation" : true,
"DONE" : false,
"DOWNLOAD_SPEED" : "default",
"Disable_Insert_Pad" : false,
"ENABLE_CTP" : false,
"ENABLE_MERGE_MODE" : false,
"ENCRYPTION_KEY" : false,
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
"ERROR_DECTION_AND_CORRECTION" : false,
"ERROR_DECTION_ONLY" : false,
"ERROR_INJECTION" : false,
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
"Enable_DSRM" : false,
"FORMAT" : "binary",
"FREQUENCY_DIVIDER" : "1",
"Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false,
"Generate_Post_PNR_Simulation_Model_File" : false,
"Generate_Post_Place_File" : false,
"Generate_SDF_File" : false,
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
"Global_Freq" : "default",
"GwSyn_Loop_Limit" : 2000,
"HOTBOOT" : false,
"I2C" : false,
"I2C_SLAVE_ADDR" : "00",
"IncludePath" : [
],
"Incremental_Compile" : "",
"Initialize_Primitives" : false,
"JTAG" : false,
"MODE_IO" : false,
"MSPI" : false,
"MSPI_JUMP" : false,
"MULTIBOOT_ADDRESS_WIDTH" : "24",
"MULTIBOOT_MODE" : "Normal",
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
"MULTIJUMP_ADDRESS_WIDTH" : "24",
"MULTIJUMP_MODE" : "Normal",
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
"Multi_Boot" : true,
"OUTPUT_BASE_NAME" : "bttn",
"POWER_ON_RESET_MONITOR" : true,
"PRINT_BSRAM_VALUE" : true,
"PROGRAM_DONE_BYPASS" : false,
"PlaceInRegToIob" : true,
"PlaceIoRegToIob" : true,
"PlaceOutRegToIob" : true,
"Place_Option" : "0",
"Process_Configuration_Verion" : "1.0",
"Promote_Physical_Constraint_Warning_to_Error" : true,
"READY" : false,
"RECONFIG_N" : false,
"Ram_RW_Check" : false,
"Replicate_Resources" : false,
"Report_Auto-Placed_Io_Information" : false,
"Route_Maxfan" : 23,
"Route_Option" : "0",
"Run_Timing_Driven" : true,
"SECURE_MODE" : false,
"SECURITY_BIT" : true,
"SEU_HANDLER" : false,
"SEU_HANDLER_CHECKSUM" : false,
"SEU_HANDLER_MODE" : "auto",
"SSPI" : false,
"STOP_SEU_HANDLER" : false,
"Show_All_Warnings" : false,
"Synthesize_tool" : "GowinSyn",
"TclPre" : "",
"TopModule" : "",
"USERCODE" : "default",
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
"VCCAUX" : 3.3,
"VCCX" : "3.3",
"VHDL_Standard" : "VHDL_Std_1993",
"Verilog_Standard" : "Vlg_Std_2001",
"WAKE_UP" : "0",
"show_all_warnings" : false,
"turn_off_bg" : false
}

2
gowin/bttn/impl/bttn_process_config.jsonZone.Identifier
View File

@ -1,2 +0,0 @@
[ZoneTransfer]
ZoneId=3

130
gowin/bttn/impl/gwsynthesis/bttn.log
View File

@ -1,130 +0,0 @@
GowinSynthesis start
Running parser ...
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v'
Compiling module 'bttn'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v":1)
Compiling module 'ALU'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":1)
Compiling module 'opCode'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v":1)
Compiling module 'arithmeticUnit'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v":1)
Compiling module 'addition'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":1)
Compiling module 'fulladder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":1)
Compiling module 'halfadder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v":1)
Compiling module 'subtraction'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":1)
Compiling module 'fullsubtraction'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":1)
Compiling module 'halfsubtraction'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v":1)
Compiling module 'logicUnit'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v":1)
Compiling module 'multiplier'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":1)
Compiling module 'BinaryToBCD'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":1)
Compiling module 'dabble'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v":1)
Compiling module 'selector'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v":1)
NOTE (EX0101) : Current top module is "bttn"
[5%] Running netlist conversion ...
Running device independent optimization ...
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "ALU" instantiated to "a1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v":13)
WARN (NL0002) : The module "arithmeticUnit" instantiated to "aU" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":20)
WARN (NL0002) : The module "addition" instantiated to "a1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v":13)
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "subtraction" instantiated to "s1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v":14)
WARN (NL0002) : The module "fullsubtraction" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":11)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
WARN (NL0002) : The module "fullsubtraction" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":12)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
WARN (NL0002) : The module "fullsubtraction" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":13)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
WARN (NL0002) : The module "fullsubtraction" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":14)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
WARN (NL0002) : The module "BinaryToBCD" instantiated to "btod1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":76)
WARN (NL0002) : The module "dabble" instantiated to "d1t" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":21)
WARN (NL0002) : The module "dabble" instantiated to "d2u" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":30)
WARN (NL0002) : The module "dabble" instantiated to "d3v" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":39)
WARN (NL0002) : The module "dabble" instantiated to "d4w" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":48)
WARN (NL0002) : The module "dabble" instantiated to "d5x" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":57)
WARN (NL0002) : The module "dabble" instantiated to "d6y" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":66)
WARN (NL0002) : The module "dabble" instantiated to "d7z" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":75)
WARN (NL0002) : The module "logicUnit" instantiated to "lU" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":21)
WARN (NL0002) : The module "multiplier" instantiated to "mU" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":22)
WARN (NL0002) : The module "addition" instantiated to "add0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":33)
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "addition" instantiated to "add1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":49)
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "addition" instantiated to "add2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":65)
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "opCode" instantiated to "opCd" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":18)
[95%] Generate netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg" completed
[100%] Generate report file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn_syn.rpt.html" completed
GowinSynthesis finish

2
gowin/bttn/impl/gwsynthesis/bttn.logZone.Identifier
View File

@ -1,2 +0,0 @@
[ZoneTransfer]
ZoneId=3

33
gowin/bttn/impl/gwsynthesis/bttn.prj
View File

@ -1,33 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
<Version>beta</Version>
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
<FileList>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v" type="verilog"/>
</FileList>
<OptionList>
<Option type="disable_insert_pad" value="0"/>
<Option type="global_freq" value="100.000"/>
<Option type="looplimit" value="2000"/>
<Option type="output_file" value="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg"/>
<Option type="print_all_synthesis_warning" value="0"/>
<Option type="ram_rw_check" value="0"/>
<Option type="verilog_language" value="verilog-2001"/>
<Option type="vhdl_language" value="vhdl-1993"/>
</OptionList>
</Project>

2
gowin/bttn/impl/gwsynthesis/bttn.prjZone.Identifier
View File

@ -1,2 +0,0 @@
[ZoneTransfer]
ZoneId=3

465
gowin/bttn/impl/gwsynthesis/bttn.vg
View File

@ -1,465 +0,0 @@
//
//Written by GowinSynthesis
//Tool Version "V1.9.9.03 Education (64-bit)"
//Tue Jan 21 15:29:04 2025
//Source file index table:
//file0 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v"
//file1 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v"
//file2 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v"
//file3 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v"
//file4 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v"
//file5 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v"
//file6 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v"
//file7 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v"
//file8 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v"
//file9 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v"
//file10 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/logicUnit.v"
//file11 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v"
//file12 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/opCode.v"
//file13 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/selector.v"
//file14 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v"
`pragma protect begin_protected
`pragma protect version="2.3"
`pragma protect author="default"
`pragma protect author_info="default"
`pragma protect encrypt_agent="GOWIN"
`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
`pragma protect key_block
W/rX/bP/Nzz5m0fT0C4evTN1uvzoTob2oYF98exCLComjUoBXif/gF36jWHuaUKq9Ni9kH58gEXc
1xII4vImZCwZEphYOUEf9eHCaks0VXJTQKl6P2EtjzfRD6xft3ySUZsq76xN6jwY5Mf7sr6wv1/m
fLfh/x8wqFs7Mas7tmPdqrJt/fWahMrXFU1pRBKwK7hBy3/w9h9lnvN6uR3VXZbZrXQHefrhZqnt
Zqn6Hj3peZa9fMJaqVPq8xMQ7UZgUdgh5qb/5M3fx3vFEBo3VdhnKfytVYFCMOHb+50WzrDsr3J9
NEgNWCYT/u78SDWL9DJKk37yY5BKZoxXJ0pu0g==
`pragma protect encoding=(enctype="base64", line_length=76, bytes=24000)
`pragma protect data_keyowner="default-ip-vendor"
`pragma protect data_keyname="default-ip-key"
`pragma protect data_method="aes128-cfb"
`pragma protect data_block
s7rCAC8Ybu/THsvMnd5yYtwkf1kvu3PX9BLQxOEPDrubChcoh44WASZDnfQkrp6J0P2Oy6CedC8v
gLrfrx6kWQLzCTcW+C5pKgEQxmoX4f6IoI85gX+NbS83xBBIgs5bJPecVPRra6waD6sMeJVFOnlC
dkffEkwXJihuDaCJg12q77VQzg1dZriDy+dI4nHB3GdMNNV6YTau+D6vRZRvgzgd0iRB/eJyKED9
kMjVIe+oB4F3DMwqSCaxb4M1xK4MnYLxyxAi3Pt6cWKs7ru8uFqspU76xuKMvd/IH+ih2vDQuEY9
HwflF/BxFyzR2lWglGOaMcg5zUEwiW/VgyXHbW/75KPt3RPhvlakCkAIzvlPj4EqAsch/aZUMKEY
u23Rer87BIGGx6tV7IhU7YUJ9lAEejpzKjVqngHvHi/4URuka8YyRbH0TzS8Dk3GbeXFsk9HR0Q2
zEIPGwvYP6+u77gcb+/vduzZGrbkJOhI8bgjSxZX8b4ZcR6fFDpHuUaxKTxT43GrOxHGGkiBH/1R
lKFaBDKrYccfEVcmm7hOReoQD4BebIJfO3iG72tVeccPxatpZu+fSeJWwR3YajAXwYSSRvCoIR1g
qya6BpeyG7FI3U8R3FngyLNDjBin4dRD0/kkM03StOV8bUyS9z42IpNq4PU2WtuV2f4j7bgvVY1X
WNa5c5T8gm1X+9wOf0Svgvor6jBECtguIIc5U//yyx6lIRPKAtkek9GavCspzN2HFPgHlmXoF8Ww
l4ElZNJSzM4QDEgcogkk5skjAUe1FhB3pqxc3FVv4xMAd9DDmG1DACaqRFWQIUyv5ZGcYYz4+9kN
OoC/9FOmmvbYR2snXb4L8gDUiiruEvhOAotzl497vAqVsR4lg9Hg3r4cX4VIfvdm7EVrlwmR8AfK
HThtmDKTNsOsYK7sg1yc+SG6s1S5nPGnBS97vTTccIvbDkdxLSVxBGZ/tgvBCmWCmOU9FEnO3RlG
zNoEgETddCGQZP60nGjxyNCxU6CvBI80ZhmymABMkVhoUH6GzRbmMFmFwvMqL/3x9PIPCrow8YFF
Go1mxruEyR7EfYhooNwMcesnJkIrBYTSfbDyzwp1dBiLLm7M3p1otqOBJEHyu93ajG7PRPhdkEZk
9aPAO7DRk3CtXyq4VjV5+4Tb7gCYsTi7g2d6AzjDOBwuuuyUXL8kk/b/YznqlM2C0ZLgCYb7mwno
SHRgqoUtoSJGjOrdyt10oOtrrV2gjeV1aUMIozd/FQkpVkz/IkeN7MT1YTQcIrPKdj5V3dl27T53
4NUZ77FQXlZQiRS7gpMOOcEzhjV3jg241jj1QhYx8VAcIgrRH0LPNRO8+lE65Wfd8oPlhD/lrkji
m/OU2zy/4t1sWD1qUheMhPuWKWf4hdeMRsDfYSRf0plgGD37qpYotrjR1weXDkoaRNb28LK9zvBW
Xwvv6jGy+7aNQOiGNuu2+i2yRJIZX6lcucLsSVKzFXFUL71Ir8OR+k+SmvUajYpSi311pC1o+MS3
KRD231EmQkSCQcdKlYcil6SU7vuiJ5YiCxOSO9tsXf5d/FAn/6tZvBWozDmakR/SDi8BVZc624Mo
IZ11c4WMCX/8svq7TCrDZMZlNCOnvqXwhTs74eJzwkRJ5NmYX9w8uV00bCIOVRi/yAuQRv6J4ATR
iHzPzi/TcqgfUPoqo3gLw+pMW7pkLFysUNjwkZNK8wGBWX0lbZSpBXVfFT1nEasTBPVgC44o5iGa
A5kyK5VMYMji79d8yNEYSfp5VmH4WJjHNJruOemHgFtYxjrqiyzg0TJP8iwLs14GiseWtpsNMIUI
7jG0bmZ01oXd1s5StsdDanmpiDlUbvFUWZ/qQPQWBTepSeEbGju9EQ6o2IDm0pxO1TP//zRTlBCr
7uOaUBxKvtoS1fPVcPyQQPZGv+OD20TAa9i6jJsjcP2CjGoSoh74tXK6kowdaen/J9/Gtt3hRZVJ
Q3u43r7oqzH04hpIgncf9x3a/EDBZKQSTXhR8+wrPeOqy8YAA3AEC5PEE2uJSU6+Okv28jnqC9DK
kdhu0fTvyvIYBKbDpxCaWGX4GpM4N4SciEisSb5hKZaOEeC1P0kN522Xref/3rCu81BJ3WntNAps
kvTbx8BLHGUSsdpeodMgFQvo8q986dumlz3tD7WEOhcN0iOttAqyxrelB247/RXZGR8X5VuP51Im
4wToMUVX9OJQU/Rffxt8h9iGbMX8YsXSEapJ/u7bf76Bdxr1EvFxh0hxtPTFmrRRFP8pO20qjxoW
wgllLuql4bCvB27yA+HRZq5QvCuRXWTSQ79UtB9hMLgLZaZJjNQWyCUaBNc7IvVlk+x+oo7K/0fp
0X/9Z5Rf/IuF8KPioxC+1PzUxsjABUj60Axp3VA0lNonJxH5HbEd/cQj/Ns0IfBe6JvKpkqEtd6j
d93n5V75rYVzzNwUro77bv7073iiDC4OU77UcFUA3ZudLyVgYScuVLAM28bkwu9eScsjAIm2yqA0
4XICnHuW0hEFzhqbaGkDB2w7VEfU8QbgBMDbtdl+clHumDV/xaD7jJ3GZU8DWFTmY/d70BAcK+yr
QZZJ4h0POTx3nQbHFZZuR/gewe4XkTqBbbv6CbTkRSLCPXluJtBAk7rNj+zmqIOSNj2cUnkNjATI
wQxWcDl7jhPZu2L0TUa1IIcDh69S+DyOVCOCpHOQgwu5Fuh7d4f2+rr5Hpb7wE1vCITwJ6RaPMOH
lrypFJVaWh/6tWW1HIdRUlaSPnzRoBD5l+1N/rTif+lnfNSbbLuMPV/qBMFUXaTodb6j69PpKGQJ
Lp8Tunpl+x7gTeSI8r3Vdv32Pzs9azNSwNRUIIrmAyyB+tklF5xH1I5db39FEf06wOKWBk0fR/dV
HWj2YLCfxKWjquYd6RY1oHezU4OtcazfVtezV2ZDe5r/6KKpoNrPO6p1fNDv1GCtwRYvDs+9VUtj
+j29nVTKGMsoTEJHZj7NtQCIogb4Ly4t3u1zakn9awgobZdNb1FgHVCq3Ocvambm7UIlVLtUeVzS
l2wy2sl9P8Z3cFSAxAFDVx1o1GvTptTRo/p61+OgaEPKkDoUWc7NgmTNjpQtRLQ+w3D8HXVSzMds
LrCPqWclZChR+6EuseuEbryfDk2tZ0Ylx/60WXIxW+/oFpIe2O0lDna7uTBa/+mpdCx3Db0rRKgB
D7aNm3q2f+UBUjfjfo8CPt06E9TRoE5ZWeSvlAp9nNfeB2T0BZRmIRwIWcOI0qdK95t1jJxurUMP
BGd8pg2Kuf4YmaSR76SUGp1UToNexlu9e3icMzjXKEn3kAdK/PHT9qDLaEsevFRCJDLbmKA7OMAK
ur4BFr8bzQCsHZaObfY22MgRE6mCEySaqUcTwrfJ0N3jSl54JrKj2I3mn+AKbMyDpa5Ib9ardjC6
JXtBJ+ZZaTtGaS+FpYUUSQmbgElKYdeB7oUbNzosYB8csiBlE/kpWO9taQY6NtjNETuli39bpmbk
TmmNfVE7ONhI486QIOv1Z3p2RyOidEvS89dWopDLAJew0Pel4e4/F3ujKLrGfn83EZODAmoHvR6F
XdStVFyI08w7LuZ2685bGp9rFewx6+RSAgMqeNk8MkW1Efu3YqFb5u90kRLXlN1lDGlzax9rC/Du
LBlL8P6lydlWkYgbx5gEcDMZg7IKfT39fpiEzmKuwMp3tOdHUoiI0Joh7+p8v42cJzK8D/dS/QLo
hPXPOHhKcZbcGG2knYztJfBA9iEe+wP919XgqfUQJeH6KAJIiNbvzWUSn9R/EserZDNw1opt4LDD
CgPR5mEN42d+M0cqmZCefpm+buHS3ZWry/NOPJ9sXVvY3oROtdThVJeduT7gSvCshOzFpgPl79uv
FVXFxHOy6G6WxZu4WUIXznqvCcI56fzDdF17yeuL2dHddYBW8v0Rr5wYCU+hT4Q9YMdim8LuIdGk
42TynP4fODKRkg2ofKJNuMrPnAd3gYGkMUcVnuONCYKcgA67Sk0xofdPOiOC4Kk3xBzpDZmkLU3N
gtKKmpvJ/4BJjAdNMBxkLFiWOR9vgmAmhH+duQn2Gai0zXKAdbWLFwg3dC//pKhCZrovUbgjQvAC
p0x3HGGskoxhx2lK9ISPXCmGqTNauJL62E9ylrjPaDaguCJdNxO/HJoB8oS5BmU73SmxtbNP9QG6
zss9b5e+KY3sXclk9On6SdaF35mu6kvzj68mCJZ1Jg/1HbtE4CrRvQw9HLvoWEDdwWkgRn1d2lqT
moUhrKX4CXArbpzsF3NmKxjNphtvLX3vb/A6BbVpBGoX+vV0hXns5MD13OLdUwy8k0QCKnnYGYAa
KfeyJCpM2Krh/pC4DTxy4Ll2vCnGgXfsDUzeTYbFNyDIZ8O3kTa4S10gKQWI/f/uXyQ0dkIJEsyc
Rb8b4RTjcOpyswfA535IfxGcLgElpIwnll0aeyzjc8Wkh1OfgwImrB0l1MoavB5zLXxrFX5dG/bU
NRb0TcVJLpvTd+UktZL6FyOaKZ7Txqsyko0wvCcLvxcH7xQrAzzGptWFXJlqAszM5f71VSTN0Ia3
LalpksMdqvvElhBVeHdfxxwr6T3ap2OOs9kO+OQi7KA1BlDFz3B92ur+cDi4Olh2dVdBHV2jK+Gj
aZMiPr1+KrUd3fYwdB2UWAueAA4byozWUKPXW1VpuJDqqDrpjurdUwindHLRDTZFL5DYw/JG01oZ
qz4q4xsQhoKUBOr8pqjZK0cBOY2QdPJhm1jeLLmJVPsOKarHLub5/b5dxt7sKPKM3NjEEWZmEnO6
dCPMRlGDZ7h4uX8RnXO9PSanq+0Bc+Js743iEgEiU3Fr+85qMWSfxrjlWc6c+UAdPF1siqa3U1IK
JtgIvNB/v5G1iS1v5v0Nk4KE4fFc5rv1/yq64DOO6ylv6KNUiGuHxqUeCn+73c8oIdWVRwXVBk1j
fp+7oqwhCPCfh5RQf2wKCvqldUvIDtpUFgf9hny7U8ZESKUugNIwOUSCelSaH4VGmUv/qK7/n/tg
q4Whd4FevJkh2UWGALXqlN6SpzAfkO8WQvd88ktoBM7+syxmVG+t9HXHP3Ns9BokK+N1+M71HriR
wj0L+in8plLoRU9TgfEpB79vvMBAjlBalG2d9/n0qMs0+lbwkLfpovtTYcX/BQMuDArQQZYsMtQx
bYkoyZxAnz/JiOSucfmtyfNPzSKLFidAXkoBVVrQARK5DJ4mCiPbPt09CvbtW1Lg/0HvomUOBmA6
hjFbbUwt6ZxR+C3d9NDxZRE0qsep5CSMic/ummA8opJcAyDqS+IyFvWAwhyQC8F+P3N0rQ+pxpWY
OHJ5rUMK8tN4AJExpMCf3ewM2HKo5aIfcOxezFw4gnINuIpHEADIJtIAVQ8Sc2ozoL5tWjCwGuoE
iseB+jDTaQazwKN7xURcGgJD0pe4VQ2EM2Ujz1TT5NrMwfhSpsTNeOrlX5aZDyClUJfDza/jLlqM
dnk3aJt3npNWXo91+f7sDJxGb4Zn8PVDhRaFsGUHHH/OEmAxFxjiaGCCun6glrbwqMcXDDmhETOC
WGTCfIExUO9X+c850SqM+3rgfM4efn9Q1lJRTiBMfxLQv3Fid6dnPIzupS7cFr6Mf6MP1jR8wffN
9P5MAKn5oo78buS0Sf04TPmmEiDqYxgXfa/qUPzLG14K/vkF88o1HUiAmbs2P0btgCmu+AYzbTzR
98kxjrH2Ns2ywmK6lFAWWb5quJAFXQaiDE1FFdvOcOgWBqFrovxajWdxF8zYhrd8SQfFtCSb+Xfu
jWZuExuyciSqo86wUMZIxHXWQeKI4n9/sFc0TUO2YPk1RjhQR3uur1BCrRreufFw+HPx1JkfjXtw
2cDSa309850G1vXZ15YDw6f7JxiuFam+qKNjurJ/pzE2Voex8evbjF6EorjloZeMgdSMRUynGmm6
MVrZ+CMTcRMI2pcN17BNrnnHXPGB2yqKfr6VlJQxkjrEcDZKTkZ9MOdzvFIz6Amu7gHVLHXvew14
ebcoUpjo5dki6E31ZHWL135pw0bF4OL6Grq5CbFkosKGE/FltuMsX3pKkQgquS1vTCSsV2gNeZ6b
VeK0gjwEbP84U9FrhiKzK5ESyjvSfNsvpNOdAktz1TLNoqIPsY9i8eGq9Gru99ZpGPSYuqS3EiPk
9Pe1ZCJPUuw2zLyisW9nn+GEMoCab5urnDImicXpEVDjBrn/mRvWQqqXy1n/bTtuK04pqBPFbmI4
U7xDKHwm26s/bgaDvdDDhDze42Zxh6foQ9zYq4+3ugDsKKE7fTdhJdoiWaCRi3jbvVUSORwuLXet
NqjSikAx8PhGBpoT0FtNCbShFoxfGTeiKtGkkSVmitgDORQM7k8DwqpRo8Nx39kaYrpVjLYVnmoG
dzaBxKhdJ/xvbXnivPp8c9r8PD/tLniIRugpkQgbqu5dCUzrSUf8EZXDWQpVBasTPVC6oYUu31WO
yDngEfTsYfxLCkevFuowzKWe31bTd6Aa9KVQ2P+WpmICB2zAI1DUPrXrz2ahIUsh1IqKjHJp7pG/
5RW0xRlzTyly/IfrVB2qNay+ByvOozWI+JucvFVcQinpoweoOjxEbYhU12qzt+nWq6Rl7Xpt9k1Q
xFXgAxH9rkwpDfWerZ7t76AGC5jxa3fORZlcHlNYCHGE9v1nmTkDtQf1T1Gm4Z8XCb68VvPA+1KT
UyCgvxNNE5rKQ8LpWZRo+QBaPGPh2Bl2e2AuwK5MJ3V7c6grSD171sq0p0rsW2vl5Kyu9fqFam5B
p+Z4r0bkciwlnpisVSsX8QIbGCWE+eGYEMTKHO6pJXQVazXPh+cll3XDuX1j472Ph0AqnNN0L8AL
uV7S2vs2x7Us4KsiNLIogSX6H+gb40inoT6m/QXoKMBg6cggMGLRdt+B9ZRU4tN847dmFgPEecia
38mjtpS6683d98QFkHy2hTJHJtXzXQLfJ7O7hvaWfIWyksJAVO9STr7vvH+dL6P+yFqxtCfiaCra
R7lXyDsO8zmZffQnR25NVF0m+V8uhlU47pU49lBElHGBmz3p22somd6J5WTUQztP6TnarDI7f01c
wj1PycALScTRXVgaUypeLU3vynJpEzxNyv1plM67leRdNAlgY12BncY+jeIwL9JJyDblPB84PWyU
4dmHVo9sbO42rU9edjOn1lanLctel9VEBGkaYI6+SyImUXr35C6zR4L5a78gfNRn1UUnjNHIMday
oyx4hUSOv27w20YauC45IBflJqX2uYLBh2YFWWW+/qFZzzmVisN/qf7HBGL0YF3z6Go4d4ZCYO43
kNzWQJgfUAeNvuPd1IQ1iFvjC78Hj7KrWDp75dd9Y4zgc6MYCF0QrGwQD1eF/Jju7Tlsd0AxEmLB
edZROmS26IVvnN5jFlIeXNHlmwRsnWOoP74GP/+Zf2TEtGhiPlSbx44pFpem2bVTtL28t5qW/962
y5owOYC9CIvWH0S0otU0Ds+2utjl8jIDXrrh0Nrb0V7So5HviiYXd92bbFDSzdoEN4ffQNiYA3w9
zdMjh3wLfPvJ1JhfUFPQ4iTk/Ako412ssQBqpDkDWepQutB0JvpqdCADcvHMNO4CX9i+RiPyqwX5
PPRMi3GmY4ErCTNqfiyEmUksAiDVaMIH9eeUTLBU+35wKU/xyRbGaOSGpqjjz7eQ3VTbuDeXHVwY
wKD5Q5PZ/RAfrP4r53Mdj+l9BBzPBbdrdTc92fpl20V05J9IdeZP2M6OtWV9w0bwagfyJWwoI4+A
A5zP69gvWWPbrmU8RRxTvBUq9Pewz3UDRnwQsIFxjj7sCYHobUPwBFu8ulAJnL24VCt8GAXbYnws
rD71STQSdENIIQ0us5uyYERUvuaDUFo9KwlnH77D7YrNH40HjadH+AkjGJrR79Hjs4y7mPP94yYq
6cvy6bKtvdagciNnhjxg/aw7e5Viv+X4m5aS3hTVoPMgY+MG+1xLt+4wFxbh603iMrSYYFzAesyy
zhF8+A4uXCj8zuTHsOXoqUNUEFWDaIT9c6lxZgtL2urvxxKQ0Zb2XKqWnMhKq4QtaBxjZwJWbHrA
jCB8dFj7Csw2IupcKRyWbI6ImcJCa6dxtSt3f+DU7KUWJrWF5h/mVECgolcWGe5Mj7hTz0lNjpDJ
r4BfEkFHGFOrXP/KxPIMeS3r6ARyfkkzrAJTcUyda7uPOenqcs3ZtqO1u4jXrD2ixD0Ujj8Edhsb
AUuCZSqLEyE/AXGvnbhtH8d+a0uMhhYQcqXpnkbcqbS8siXgdSBrA2JAChmL7bRjmlXc5raECFqA
Qmc5myil4R3GTdscHXI3R3YhQpiw8pGPO5fdKwMNwxue+gdJ6oAd3tDBe+CJhZpEkvdU4CxRcXJv
XOeXlSNKvdA5wdlaF2h6BNu0EyAj1LwV0upbrxhEsSBeWAvdS9qvdT9ygBi+nVCAVIBOTl1QzLbI
jpWtcDY9t17OzcaXYKMAoDB3NtWuoy3mVL1JOq/wOjZ81Ons+ohE0iN+bc5FqbX8veeqB7Y4Nz3i
4UUplQT63mA+VQnDBUqMUIfB3i8mnz5ldfWaBuzkymOmnDUL2zKAIwlxXusMy+9Z5/8yogXaxbD8
hbcbTAYGKB6ClirYPZJNkh4lknaZNvaagKyjlI6LaE30b3WoF2+kyQH+7+kT+IP1PIkWUqYqM0vm
LfAQYB3sr1h2LLM7M++e4CwPPrRPehJl7DHGXEduZtaNdtfvyEm0wePHqK1HwdhHTq/tvxOjV/ay
G+ALEeEa8j8NF4egwVAGO/OGbm3tIWtb5X1y182/aedJ8agF8XgK88+ZFfwjGak181uLab9fWTWL
OrUWap59G65CoCntIr4x2n2PT2K+3Map2I6Qh99FrU4t3uXdpNIzzfX9av3/5YOIEYGSpMR8igUk
R+LBRIUKkeGLnboWRMzCXgcr6VIoxLW8c5RNWygRgVvNlyzro2tR4KXv2cY5rmaxUYryWtdFpI7W
OpUTlUb01ZlhDp+Zswx2e+/V3mDvRvJe7QDnIpUzI2hgS8k7jlG8YK6TNgpJKD1Ie9i7fUQcKFa1
qr+ai9OXnlbJzLKAdTNvuvp/xLs5JhbbsMec2BTDsX0rrJLNG1Wnk8lbdERep4aPWJnPYKuqphR2
UkwaTcNFHk81uZL9h1G6m0v/Wqjtc7nPXtbFpmg56N9Mrfs+4adtGi5/cwgBPgMyAekYPh3D6vfG
PLGshgZ7zqDuQ6K/qgMjZ8xeqYnfv6XtK7CbTDEP+NIGostARrPx1i9O5cUEkfVEWWaYT2DpUjZv
o8GvDDYHzVoN1wwO+jWDJAUxveicUG6k2po9PWf6hA7GbDIlFOTXp5Uq9bLiW6lOJq1dglElPifO
pmTm15iJChJoIwrBT/Mk01TmjlB3Gh6NYLjs/h0p+yvgmsWj9DccQnWYNJ++71WWbiDanS1sd+8V
MzgC759RAFEznvFs2fblHnsL7VYIaRnOmo/OGY7gy2YSKwp+yvQpDOR0FC43lm30RRV+GUndMuHZ
goIMbVAMcN3Eezba1fgEmmw5UdnsfYxodQ/F7ENmV+etXpHstiPD64XZ/ZxoLLX9VDvMsXOMxqS4
ItmAdEBYOg3wDZbyZJytBeLT8lbi2yzQHDJeIijQWa7zbmGz6E/XIGZMt2pagdp1GRYtaVjZa8gC
Wn+YZK06eGQqX/8CUqnplM24rqNyINGHnRUv3YeNcKcPwjl1+/UDsz/Qp33CyCjPCSzYSo3YFVDJ
Bn59fVQUv0BuInLrKzsK1sYS6onxF42AqhEPFKMEa5daQy0Y+aLyH2cRl316iSHBiT23p+6klGzc
IfKc4YqsvnmRnpuJ60VucuJyncVS04ViaR3d7xY0OsBeI8p5sSxlK+AgGI/lesv5Pb68+Ec0bPiM
EtNP6Q9a0YGsrQUbLPzuwmNtSZliGwTJCo0IJTPVRfC3Le6jvMmucUucHtXAQmLJLJji04vKCvzx
ki5nYzhbO9EE4X/r7ibTo0X0gsxg53soFreQdurq6Y5wiqQdVpWSLmbH8I5hIa/hkXHWyEFqb6vh
l28l84QZIXCP9gCICk+4C3W2qC56HbWhW8QALF9rl4cTsmgacsg233wLP/+X7kpf9chvGxIuMgCl
d04IeOaD9PzRtxLj+VOag7eDSWgnrIYNgW+BPQnGK2Os5f5orOJ0o/RfYFxP7E7oxHVU8PaO0W99
3wP1V3IISDSq+it/I/bmDUJJpT4nguWjAa2aohes/0SB+rm4FXKXK9zfADMsLQhs0fchMkE4NYfQ
DwIhmsW33kv5DNl8xpef/wt3CGMdkPHAKbLXSK9YjnhzQrQb6lI5GJn88m2nHl0Dh7awbNLndwid
wWzZKUj2TulbxhU7I99dZcdiz5VjB2cptHm5nV3xe8T/Y8xebsDKvRly/g2e/I53JUJt2h/nWaS4
nV10eCyQfDkMWbpy3BU1NlqJ7rHlgs8ss6YMERmdY9SaMdSGjHt9AZxzOK3wmHFMExb29Lwz9/hq
9g9vPwTzm7+gFW/QV9tnUU6NCrUpO3Q3BN5NEv21rPh/1TAtYSLMzq3wtVNwfGslCbfdsBp/INyy
JGZSGxEYcU8sddcUF1oC2mjZmy4wTSFbFZVFldCCqhqN+sEaUvjOIHcQ1sk6FUhQublyZu1zO+m4
fejvvIq/Ocn129Gl8lxb391lKgfVi63dceIcD+OV03Q62zpRsOUgoYQkOXMEvjQNeNKA5KhVqZb5
manqo2PqhKmYa7qniQGM9R1i8b0guIzT9+Kdu7mnJPDZ0N2dpbyeSH6EbCwKi/OFc0ShZws31Z56
q6n/CB9abl3zzZ2a8xN6CQC4sLWzeaqvRhmQF9MJ4kObWoMXqa3Nc6EL/bPhtZyx5kzigqVrEeu4
2tLJVcAtAmNWt9Brrt/xYxh1zINE49PeosppS+Mz7gmcShrWy0DEyqVHnNlVwJIj6Cvjvb5a8ZxV
3WiqCuWSGFceXKasMDzVmNFtjaiRAfR+mzIsAYtXD10dFUYIkZ85tu/cyLfpdcUg2nxd3EkR6d/V
Qtb41guqO2apdcs3A9w6oKyg2FzONX0I0v5zL1VlF87QyFYZWnt1q2S8WcuuNPYUrBGlxDsRTkci
9SlsreMLG0S1oEsLRhxoyy5hiILP1vSz/jw6ykd0AvgnzFyDo93Kaw4vmoVra5thO1AQETmmCqoF
T6Y4T2uI1B/tJYpY5VuprBdoIaKEu0wQGw1GqHWFgjvr2r0YVVT13nqOykMp1RABlopjsbsLjXjt
3zYElulDYvUjKQgPnwGUsSFbrMoL0G1AF4ihelXGe2v79sqyogOJN+oAqs8J4ODgyFbPfspsn+5V
9vSPawleN+9OCZyNmPBumLGl/yC6L7oKhAgqnXPE262J+zjob6UUtvlaC1j4qkljf8mOoyDZzLL6
TTs9+QEUIdVtgosfR0XAun7cIftRK8UHCmx5B+PJpkNR34lZcshaLwKApdzQjl2Q1enZYYjSEYj8
5mDKVyBXPSHKApbdkHowGuBoa1psdGizDrqJUSk7raYXKBqRz0f7sIczx2dUFuV/ZDLiS+LJ3ojs
CmhHV2S7i3q0BLLJ1HmKHhahihhqchyUkvhYoM8VcpNoCFP+FPsyPuDQqBRbOyQihMbAT3cPxyfT
w3LhdAcZI+GwvbdUg9o2zlEMNuRnYvTwOcYntH8fwjSn5MaXUfcwpVyfujQRitFYNyTvwHIAl+Kz
wjpd7vIiwiJbkCe9MW0E8J+6g6N+G4ti27Q5hOCSeLQWHObn7rHgB8mv3BXA21C2YFSE9Zx7EeXW
qPLNKYHX69ry5WgCoRLBDSjNjXMqiVVIKlKtjwtCJlDMPJU6M1ckw2ZfSc2tuXgFQ777rrMDcxAT
v+ePlUl+6VJWqnZdMHJFsenrb2TkThDeGFCi69S2ibgFngTtYLpFJs+TRMjX+A8E+8+GDaFgE0ps
KnnBkAqHpZtts6F8tj/qt8vtZwm5jxjeXyPk4hRe4kL4NOrpyWPu+OF1IpkjAT7csZfn8zBUTNOu
gmnQjTAb/WM96bFNST32axue9cBdYKb7ForBaVmpYXfgLpgaQaFhtRNoAkmaoivWNMZtPoIDRG6J
iPiBwWsjncJr+hofeBHJxHpC6zKfxVtB1Ofpew5xGBT6gA+RU0jj339R/lA44nMFbwGfeeUJUNFa
VESHPBGUHSvIdjW0n1AWSOx7YwCwREC9XdZFyH1F+dO3kak7eFFFOLVHlWVM8RLjHzIvMu1KcLTJ
f8zDL0X0L2Ol5+MmYzcZT952n8MRHKfe2wyhHmLOnpdWgqxxPqZbS4OSNR4+R5PtAHmOoXmed1qw
RU5IToRYAGMdyxSnJMIRpxvB7QMLR/dIYekwZ359qhtk9mbiK8fLt7ktnBlWo88ots9WXr0VzyP2
dTCRRFuU82/hG+mh0PVJ2KJkri+I/COMB6tlOvjsN3bLDca6YDSpjdJdgr+B8LeMA1kf3nCoI6gF
hO7GyzQrj9TrEVTqywiATTiN5qI1zGj+AzuqAxoBM0crgJrEdAyL8o3NsE04H9l1qvr9dI0oW/S1
9eBlP/kldvOKEj0wlAy7af1soS0r0t4wWufD8rlM3Sga0KbC3oA1c3JU9XKgb5XO0iIBDtNXbdXZ
0HAA+r2Souo/HC894/9HSfeuITCyxQ7SDVDrGdYiP5PjYPGOyNC+v5PkmtgKBVf9RHihg747MsuK
9MQNIP6iGUQ1jMgQhzhW5HvgZxSa3/mAhjb6WOVeDTvc3PnY55KyCPmlrrO0cv2oTV1NSW+WtRmj
Kqslqg7oGhNcvdyLFv94YmxBzOkKQeBuQGW7FtOZTTwsvehB7Evg26p8L5hy+z+h6TA4vKa3TR49
eLQ8tvATYvdnm3abEjdesaxINzrg6+SjQoP2fBWLzCMUYRhhukbG2AlppklAzMpfuvy9by3uU94P
nLgJ7eg8tFnWG7Ubm88e+KHmHJqOxHVTpjy76/yHgZeaSYuXUbP89B6zhH6GpB9nQcYYHCVV20oA
vtGIu3mtP2hWtpUEmZWo/DF7DKoaj5SZVd0nYpoGA4oVKgzexYQJRaHWUa/WQLQIPbGU0w+S7sWq
6qQrzT1vnv9ehYR2mWjpTAK/zWwMl3kJb2DOp3Pev0OTDq25ufrPO+rz2F68abKEDE3aAC5HbaAR
EsBgc+KsfcAeoUveibb0kxd1aTfKzn3ZZbfNvO85FFcLJl9obdXZpjkAmrJ4RLfeGruMCNi0Dv8o
OGqQxcK/DTXIq/w7qodmbyRdicAgns7dVj2kOCPZhWYcLTPHH2P7CJf69tmEIrAdNykcW+CJ5Vv/
hZNI9BtaSgmTq9qYg/yyQBo9+UFOh4eN2RJxCtKKkTImmnz9vI2nwCzT4cIRHCUxteMO9fOrUozL
Bpm76P/FLBS22T0FPO8OJ+hjb7/NbsjMPrchwuhfyFeDAynuhrGnjfu6YtJNGYMJpp79RMeXutFU
BpwhV2W7asNFwBvfdwBcwexhq2S6OrUgwxrgbYCA6Lf1iv7Twyh3Ibl2z9iQrJxbVG3TJcLewSX0
oC/j20QmDPdwr7og5zYDK5/Loh7XlZ9aBvD+/q0l6objxHpINsJqitv1jXJEIzVh+MqHwVceQbvF
ryW7xN+eKyXrEWa1Z3M4wvIAi18F/2rnf2RPyriRIcjfHODn+UaPrEkY1wI/2O1ejH5mhgWaXK32
98PCZprCrgWBjp1v8deKq9P1LrP8rWn21xQVIWH5p5y4TLXnFb0g/FnHI28OlAJ8Ajl33NX3XOW7
+t4ipz2hpV3QEfqbNN6xJvvgX8QWDQGw/sB9Vnkkn2JR5a9p9ik04zkVD/NbkV/xyLuof8tgbMVs
ze2V73HZdqPdoc7PXLx9jhN3YyvmJGa161i+zXlu1sKvQF+POqXYrk1Q+rhnItxRYUeFxF2iQnDG
3UUwKX2BYFAKjHbUZiMy15TJSswyjdQdi8FjJGsb0xxMI3mNbYIj3eO+cnUZr/KzhMhXIRCBr4vF
nj+alOwFnxIQxTDs/ADSE519/HWfoJAeLBBnj2XEhhWZC+MbGPRly/OT5k/HN2eqQ3dDKnPmTkqr
EELiFnCpL2ybetBH089VHU0ztbHrqvH3vPk49QePdusYHT6pOf90hs6LoEkzVuLFizf9ObM6Un6l
sP6ItHqvHEZ6X4ZnC3d+B1buUlWt/lR6Oj4mVfeWkSXelSVqRVwA0w1bn0rO8Eb7jj/EEd+U3fIR
8GCSA/Qk0kVdHH6EfigUTbX0C1Aru8QDfV+rrvcX3gLJgzWecB1hFwOutRPryaITzfspsUJpTe0J
DgA/s0KiXGWQAcAxPs7wZ9lOMK/S+IpWAFDomlM0eNjp7H9z69kv11RkQmedIyNFbWhFkYR+1CzC
98TyhgJf+XVlq1aVT8jnCsKOekGZ7PKgoe6MvanJebIzw0btr/5Wh2CBCL0sJF2kBVEm2OkTqFY8
BnRNiMkXiH56BBUaI7z3FXay7bqzOuPkGaalB9l2Z8JB99lTCShZrJzhO6+Y0YBjjM+Cry13Stvo
fXRCeMzo6vxRu7qKBaCozXCdvJFPCqvbbaUATgOmftgE73l/YiIdcDG5KsFMVAUfXEU3YeQebz0E
KU8D7x6tChJGa74KUGAxAz5EveCNZi7Vgk/NAiOgKgo+TcoDWMy8mDI6RPBOOzsFlxvel6xkHCZs
xDVgeIEEU8etMmmr7tBU1Hm0pGqS4CLB/BBQVuD4QnYvuoiGT4BqyuU1P82Bke9mDxqBVWQqYc9z
jgMu6uLoen2LdiASlAKRsvw89c8bI8bmCTygt3Gr2CAYjQC6rrQdSpSo59CDKOms9uoyPrxx18a5
IvKyl1JkxWoA9BRn+QKo8CWvrx79uxCSguVW8UyEpo2INvbsZLWA8U63BVcepp2UlRiqWW9REDPB
tE1pgTIAmkOiTNCCL58twExYSOqdyTqPcPVCcUg//xoBuyKFTRTA3oRlAXs+dFezcmHpBEJXyHvN
UNKAXDSA+PImFVN9KVwJqCriI87Ft/37O/5zxB5MQ5WsFLdQy/2qHNuxnIXDvbUwTUuoaD/oKpL+
Jj5/O3T0ojIzfpMB4ghws48k8M/jIX8jqYlkEemQxPMc1W21/WkBdkPqE5L+/Y3W4uHWq6hpSruc
akrjRxCIxZhhj6/CoY4XABJPd4gCKMzlj8u+RWbFRr4USOkf1I+1OQkJc2XPvVhTy0QqqOPsWIqS
8sOJP+o5oXb2WHlkP1j2DKXCCmxH8TFro/4mthiLMj1Az9AMZv+agt5poIDZtBN+LLpiICfnJduq
PRTXDO2PrWXFXN1vdDtLWf24fNK2EMv0vB+sA6EUPM01UqAVc1G61l5vTec56CWREQGC3hv2DTWo
U+cuPYcYEW/km2bheKxGVF3mZWmPi8DQIHGZTdyD9g7HgR3sYvt7f8KjUZZOrJ31XVF9i02Lr7ue
fZAEwhFokAwkWEHgLsWN34B9PcvXH9M8BgbznYTba8f2eHXkny6aBjMF7c99xqqkEeso6lvwdJCX
CDEtZR5ElaKX2MysBgE+RuYUht71c6oLC36LzLXibC3rNHGmZwaVHHeP6pUvo045i8p9P5pgQkB5
/YudfGCmL0cCdb8enFckFBf2wxWKeRjFcQqO6MWbXRSbLTFXJmOktZKd9QCOpI23ykACbNDNFLvN
nSagyihyS/dXwZWrlIDWzFS2zFTQZJWsLB+Qvp4WyxJJymC/x2YeKifcP7rI6TgH0skVh5bnEs7F
1w9KTsFuuTjZ+HLlMZSd6LicoC3J2PWGCCHSkKQ9lneop9RagToFOTzMiNxSEAtN5zUfUlHzzFlF
P/Sd/wZ5d+u8TobpxpaO2KYIg5RVZySrpaEBBcyV789vM+/YBzLzp25+LLd2l3zg/21ZJU9kOpdn
Hqch+NLO2Up9INSZw8SYnENNs1dPzEiQcc2JilvI9gCh+sHfHSigHKchb+4c3eGkzAWiSnypnCPd
QUeGsmthoLIomLPWZUX+KMv9tCtTzvvP+F/sOcp9O/AFHoky6bdSzrPvWN85G+XCqNeOQPG/3pIo
magL7M7NOHeWcg4sDA3BibDn6ChB6gnF66e5SqBDba8VMTXq4+DfjPv/jM2Tmpa9LbxzLWBoCqE1
6DYONZg6cyI74P9+rwJtK7AbnqAVeW5TJbFdUBf8fdxQWU6Nc96s+Nm4T6ghKHpbtQPp6FAQ5pO2
BlXZBxAhcie8g+aQveLf66O/Ac93aqVW3sLp61V6mC2HTlq4HJXerQ8Z6XWLYLGkw3YFbeUjOjKg
RqbwEd1X4T1WjHfFwlcCTx3fwrrYAT12X/8fZq2EteiFuWDV0pomg0ELNInHhbUNGha8mugxXg9x
5I0AT3xuBxqo3v4wuS1iAKLOT3NqF9VRSV5ElTkd2LuQAsZGE6ay1MZIyQ/87A1dOMWwyn1ogPdS
zzm1HU4Tf+44fxI4LyQPnJ9hPoWsvv5jwCc2RDdORSkkTg+PZxWgENGrnjGYoYcVLwM/yqUyAeUb
UFj7HVqDaNbrNZ90dV4jDSKqlY+6W7d3jtqjAoZbHsmeEXGhGNBX78faMvz5Rl5t0j9MPBoGlrk+
8ku4kvlvCl8+EZoPtwIPzjydLX39e9oNMQrUNoBEx+0qQQ5UK/5BWCZ4fBn3BrAQuODc+QyA0fG+
cQV7R3tCO/QoLkTqTBHf6MTifWLx9eQKB85Y7suWisBDDZljU/Pnpq0crpuCUFtpdWvRln/sLTEW
n3GWpEy7hncR5k4hoF2A4VkZlLOPpI5WEpca36T39D5YfvfvcJ/T5ZRCQvKuW3tJJe0K9ft38zjA
0FSExaLpnSmW9Q6Klmp/wsrqJS3rdjOdu6qsXUEkEkd/DtEJTBKeYfQBxIxlUBUUq3EfW41hR4h7
iojj+l5WoKW9y0SMzULiOQdAWvdlDJlvWmDMgoF1wGlx0Ah2vcdMgLjnOKRS/x5Yd6KAqEy6Faoo
GTaE3ARlNUXb8pAVYv5TqOIrTHSbkfgz5J91XI2PMmiBWWYDn3zsaG677IzDSjU9Ezt6zn4YCT+L
5Dr2/CUU4Ff7iX1bwPYHtxQKIQxGPZwcCQgJRoRQmf7zB3N9xULwK4bauf2v6rP0/sRKVguhhIvc
epF+tN3qbSoz9DlDo5MYCMFTHrdA1B3hcOxfC5o4tknXRS9if/5HJallDVmDEjK7Uwe9ppgJI/gi
iaM+MhbBw6YvVjVorlLkNdUXCFT/GoXC8OnSmLHCONuu7bs/x6xwnnV+m/Nlyu64DPMmR2HXNWCf
H4rZuvTjEy/NNV+G3lN+XuxAU6eKayEm/Rmysza4U/GDhpeKvA6ef3JUmZppFL8TWFKdnO7jyZNj
lNjkDEwwo6R5mZXq6ZUv9+02HiAP275iXP/aoV+P8xbNa2IuKSEZx6BsExVxt+HtfduKku8niLHv
/ZZW8KsVFi4orJ9jHK+KAyeyNXaYsKx2UEoWpXv19wDaQgI4n3J7Fs+DJCJFb4pfSZBlgSYyqrXE
tG/GWwvPFqctjLZFLeVo6G4VfbD+hstp4/OHCevNtEZk8LW8g2l0pYhKmK28/BJg1L9QVs96GNe1
xdvKU/8xTWXrEGmcibFcAfQBKO4TIuC3+Gk+PnNFCh8MKh0qeJ0//gcf5FWQWOxWTxT01lac9wPe
1EihhpDr4i6Wq5Dho28+ZrcT1ZTMhQjc3bg2+BJ2Xx3aiOpu/HQ/virK2nPtGujTXA81KeeJXbBv
fEQl5vFVfb3sAwX67DGwyguYiwMchqWVbiMIL3OPVgW85NOyNe8demtUgIF3d+KdZnHDc0AS+Oyj
pM7sGy4qt2M/SoDH0GwY9Ap2T+yygdVH8YQ7ew+sJlA8a8ktUo8KExc7tGIO+QmFTD4vgA6t05qS
66CGVZdbrg9lDL3hjyaP11V06DYcSpy0dgyyX9z6NGN60uj7HdpPPm5b9bQp7n5vk+KcOxVeuaMW
CxzHoEswQGJZZbZyT64U1sDP3Mal4OV8EABZ5qCY4ulCfbDXhFJbpfdJ+5MpXpFdZ/d0ko4+YXtv
kfICHwHbiMjPNT9Uw9widP7Qh+YJMwLWcx++RTdlBsDi6SiP8ScKyJy0cexlzUTrs73wExkgid6R
LbtpNH4/kjjO+wQFq2GBnrK6ZAoVHrULqca40u3bfayBTt+pyG5TjIUuvkjphnaPpxgAroRBgAIr
YBI92OxVugLZ/dxGfdE5cnGHZiS+8RhMaWL4kH4OIhCw035TpTdFMmbRqWy3nMS44n1g1APdusVn
Zf+6nOryba1odlWTSkKm0eNeveqdtZS+lULWrl+UMB+i7MT0ywOs4cwJQizwzAlScwfZ/PxnrzRK
ZqPY6fZWoOSjA+ekpSSK3DjVlBeBSe7ANVOpKDAUYhof7V+BoJZBoj9yw6rkL1s9ksfqYcRrkqpH
eGGIIV4GsmMYr+TmclnwuagKsWB9bS+0QjLCTeVsplmgzSaX1M5WSasOhPqJ442lf/kKLl5GkJhO
MEhTVBYz80HqJDmJP7vNDF33zG++tX0lNVjlvwRHNmf9QVzkLFRR/YfCosMhtR6Thw2fJchok0jY
jezgVsJBvmV0QBsfaCBvNMLJc2wMAh5spCC9kJ0eQ01bUYZlbXX+Yy/fSCUy2LXUCybTm2fsqer+
yvqN+O2W0TmQmYT0/1rX2uYze+TQqKbgOtwXYPaHhOm8OGUJndtdiKs2lu3NyPi3Vgdu1KW65Plj
HsqpcOjon9OrR+qrRQvRhsmgm15JOValUjw0w8S3Cfv0Dy0KKj0EJ+eP556GAXpmWKI5FCtgRW1h
JvgbmmCOb87LXYgwQyUu8fx7nyV7cVQnUw897KMVDasvs8YlwEr4Sk8KsYTuIBh+Xa4Q5WCFgcGn
XiHq98WFHOwosA0kZFasjocV4SLsv3+FZNbUh2T1gP/uIfeMFcfn0aG1cUUm1R60wAJFfUtmwVj6
DxHNpyx9ne8jK0dRHTi2rhrQHeSJFE77MEe3B9Kf66HUqGhC6pYR2L36DwHMQNzppPPD+OIyCcaf
W7SFzEQSLW6uTXLiufcalM+W72Pg3+o5P48eDML1HObZsPVudn+7IIe4GqV5OlKwOxsXziYN22Wp
1vR44hUOiDb3qubqzUEIva6PsDOUrQ4i9evSzbehL8WUHaaPZTSW+KpaKhWiJbmQGfThHpyzrI46
+23UOZCAG56maeuK4tChzKQhObq8Rk7NlvMQt7Ht5eOehhyqvGfXXan9p6MVAihbXf5iV9dq7xWA
YnwXEpD9JV/lzU0LQR+tIpBujrnZvgLJCH70swIqJH/aVSfYG0iAbRnf/uToOSDX2FCs0Bbh0Dxw
lvwZa39uPvNx/BI94SrgeDGhdm3qpT7ih5wXqW+5CUULsaXbOWvcynZh6/FcG3x2EAYpweAvC2Vq
ZWYIt4kShw79XAb/Lb2emJjg7N4I4365BA6VmRB/m5NegAUmZ8Gs5sDYaJZ0+WcGlGp3eoZh4Nkg
3DxB/qIgYwpfnHryTxqOrdSj9UXEzKKV1THkCVSt60d3uxGav3FZRRzUSLS3HdtYoM8qqVer32wD
SzL/ueAI9XJmyI6Mg3qUKm22PKkZejJe/vXp/NPbh+kws0LqV4quB0TpR1NRUTI7FUONM8eXNBaf
hE9dSEzsrYRHRlMV5NWWyBglyMhIZXP2AFOAr4Xf1HDJJutdBaM0HamV1GcEKhULjxEJ0M1TtL2x
xnJuw1P7s2+DAKH2Iy2dWyVHKvOg//MqdiiJazMIVu7jBKTnSGRhY0SzjDbnm10r2flukgsi6TwG
v9nxcipFnUTPD4i+WmDLaLgPpzN5K60WJK1DusUua46yWhzApvk/XCf51tjTu9HzWKo0BLDMn5bR
rp2sNZmYvoXoid6bceIJsCVv+4DPH0dsV3BDUXXUIexEPz699FS/98AN2vo7hbP9b39PCM8V+Jwf
x1XQxahiwYAOYbabIXXxJX1n681AsKNnlxpx4zHPPyb43vhfWkAmWMidQxpxCJrvF5fReLNfOrwL
ih7FO43RI9euQjfHOzbTttBoJtvPo4eZk2T92dAKOqJErlNudCOc7fNy3dlCjRfLsmj/RrZcTBsy
keCK2+30PBVJQTf1bSK159X+NsxLtuj3tUggHDiC9ERaoB64SgP5Cx4gT3xmQ94LvVLMaiYcJteV
T0z4WQHN1Pj6meA+bMiP3nbVyOH/Q0bnil4VZVlcEk4ORw43VVjQqAqgwSSiTMG8H6wGm7DmxuwL
FgD1SIje/KO7ryHtIm8khMOnXfbbIg59yvYmQ1Otw6VaSQIvi95BOs/X9Ipr/aXne/FLoFq/rE2+
ne/r0IGQRaGyuq5ey4M7hGocMT26pe+5yhWiFuZ/Gwg9XIvm1JSHOUtZx8PJ9FYJN3bMAS1inR8Y
Z9j89MD+WT/V1AQ+nu5GitxVwW0V+armtSDY5Mra3kc7/aeXwKoFj+Aui0yVMR4N9iJVGH+nr42s
R1ZPtVuiczorrz7lMUdaHAH1AxbPmQzalvK8W9HsigfVFRIFm2/7ThN5wGvQbO6m6k8HpO84+aJ/
vq15ontlPlmCv3FjAIaWN1I3p/lw4Uu4NWGMN4psT/tcd9JFow7/KfdpA4qOrjEllBVEXv5K+w9E
rF/UE4iDKXA1TlRWku69pEf7u4HsFRR5ie1KvhSWlcT66rQs/LL5kgkAp6FSXCItKyCottovkm7l
aY/1oWPEIfmOXIe/qRjD2Rua4StHWpmq9YZpnPd3NcWJ8oo0lMwt2oDFR8jccWqv1yamnRfZ0Sek
0u/Vs5WJ8mCKKrD5RxwEzQoJ1nitHMUSpdVxkTH9+DuDry9t4kT2Uv71EbQ7heWYpjYNdk98fqxz
HPRQqSVJ2DPoQVgO7uhnZH8diII899Fevi09OHl6RkwRcjBMKk+fwVuR52YoKSGy2uqrsipr34R4
dDMX7AWu9zQn+gsaXuAUyWAafKX6W+y8XGFWiSO6zPmx9M1QtFDe4q5vuL0hWBQVQrQNF4dwHJVv
M3ndVzRsnZh8qYAyM4KjaYyTU8Yxrmfm8t/ilYgFc6/ycg/vOt9jFrKVSaCrpIjV2WQg9Rbl4d8Y
pXO5kH/RYwttZlBU5238tB/RLwsk+kCFCQVQK8Nu4pW1EYm67JaXTzmaPV9S/dNnEvTmAQR/R5JE
a0vkdmCmJKjgbQGnVn0wvv8wgbzmQG12lEo2F3m8uW6IP2zt6vwFQhKXeQeW4fYAFhzSxrsI90WV
uoaOdrjbvbE5Cat7txoMTRWmVdScnlshNfgHFC1QqR1aqRzEO4y2KLwgA5EaiHWWGP+hQkJwPf08
wScST3KhFhPs2wtz4+gc3xmzW/qPIKuhHEQ2LwMithDdH5Qi+E6cdX16stTZCP8jh7YWnP7w7ao/
zdJt5Af42z0QfTed/OAyrsFGb3trVjmkjkJREBPJKJkP/EEdxnEz19wXohvOZo3+KbBsqs69Ieyq
3prJL8rA15ia/Ti9p5fH17sPOYOG+Fh5+YFNmFTXfCOtyFWf+6YEaCDcnW9rFBlt05VNSRpDBNvC
TLwo2VAagWokRVEttfo6Msqaie5rpxirU62EPXZFcsu7Pf1smQfhK3H30wCusuMZ7A+7OJcj7jZw
SO6NR0CEVg2+tHe6je0TW0NUUko2o60GvzrEoj/qgI5ZRzyOuhnLa67JvM2b2VwdyRyzzNtB6XCy
nzLf9EtsiPP+PZ1xx2AxdIhZnS5OqTA3NBIYrqtknKmN7dQLOG6Enbm+zkvEWiI3nT0VwYTyxhbu
MnOPACE4AQJCViHCd99kH29vTOtwhs1QlXLK9IlknhxnEN+Xu92HgbLxP91nSqy/fc61iV9OGAOw
J8eKUu7uh2olQLe0J047eELomi3GlhFbpMS02/2tEK8e5pUsFyRtTQkn+kpwDZNsrcywBjdF8KZt
0WgF+Kh97mUkjWUdaqyJB/9i9jeyS3I+Z0WnRY1n9Z8tKtpmdQIbbO18IXzc/rNxdqrwdcdPUhJs
FQavW6Ge27C63mXZ10RIo24VXIJ9ESrgiqzqZGkw5hwOLSBhOOANDPU4hJBMkpPit1IT980D64lD
JQu9qf0YrghpTTz4wKnVYv3BoPr20Zljk+SZsHpkfbydNWohRa/JexO/75VBQjn/C7ZmamjAg4at
5vSkBwj3NW3oSyTymopwh37FBZinItS1KRC2QRzy2Vw76GfPH1yL2K4KM+M2hsY0BvXVsWPVoTe7
ZpmlBvQW5o4WdHfz7OSjz22phlo29hphCKnFNNaiyUWnG3xBgA41GXMiuqZeo0PlGMGbrDGi1nXi
a72mIdNJSh9vu5geE2JhTLlXO6tZXL8pVmRUoq+Ce4L9LplbbcPPkpQQZnJkb7OwU+yWx0L8QlNg
e/GToKSrtLghhnKuCEmRJUHpw77Vu2wjXInlY3ZP3wSUn5/PsjQXpojpG8DANy8C47cbcfOfP0Fs
CZApJm9750R01PUJucRkadZfjc5fNN2E9Kdo9AZWBaL3f3zTtDTRKti9vy4j7EKvIrkh7A0jotvU
p5x8lDToUm2jrbgM8wV+Y0MDG58y7Vvw/MygpSBAWZ4xmXmILPyCbJM2DAatNrnRQJxRO2Zl04Ei
H4vOtNI8JaFzw6Fndc2fNqqZqL3ZSMQeG1lmTY11i4HAwu43xg8dGIePX0FHyiGDSfY/XTnYCxQV
MYlZyvWPOWE/YHKry9v8jW/X698fQJg2MhymlgRotoERziT3ENx1nxGahRPFMtmkWHLHfQaHUlqe
RZYCTxvUcmgI4kbQYTYW5W6CWFSpjMSurf15m/4Ve6ov5iNs3/8qPKv5nJ1xp+o5IhMKQ43f5v8f
OHQxY98UIoksugXI5nQdpCDo687Lr37FFhWoz2KGn6qzSXJQC6XGEBDTep+DVZFgLyph0ecGfehK
8JR13k446j/Dfwzf6BLwGDPd4yR3HxvyicwPOrJQMuvU6SWNCHRCCNZxecJP16ciN0TUun3yDxkW
cDDeI/sHaamCU0PhwtUCY4CC2Ut9Tll92rCyYSsXI0FaWndg6xB2kjiiwiqYGc72nWNWgvWnXSM+
5kBJJMw53ECtmrZ4sWuBtiuuHA3DgePX3fVgGRcaVKuwoKra+UFpppb4xNNfMImZwoBO5s5nBT8R
vtVp6S/0SJFME/zufRjGS2QRcuQUsmdtAIxO0qw1N7q/RU8jflQ1LjKRH1lrmJ0orHRqOFTvBvLS
wHh4H4xoB2nk6LHGncfKClfaweDdsjAM/MzHgTbxxZ0f8IMpvXQn2YLVgY+r5J8mEqQYpllrOiC4
WxMsFSQ6aeghKuRKJe83xSQqfAOnqVuFWy7vzAXHV7FCbM766usWdf/0g3U0zQhqdEPblCCDaWI5
t9MzLbRmw3/CEyT5rE3MRlVPEOA7oddGBD/bxGSXKXnU5uOrVcYkhHrOOuMEAfOT7VQjrKZ8Jd/9
kWNzi01M8+xwg7fMK49I/39nzwr2Uvz5s0+nVCZkeQ0cHmfCL7/an5tGfC+k3vkN8g4lxZjATtnS
+hE9r6BJQ/ScfeqH8JuVCOERp6QHapfrhsvoNxbzTeagbfqcnUyaW6elEn28UuRWzMu5UqkljcpC
r1p4G877eNExFqH6tNaxBvCneVjjyA19OMrIlCX6w32K7dtT5/NposqnJmf03c6x/mGEvpM38xT6
mS26PSEeabPIBPP/kwgrKfMJLlBlnW50JLW+M36eGTpdve2xIkno6uIZZaCWJ9JbS4T5eYYO1bi1
WrFtJEc1hRi4SxHiG6hHT+aDrw+hrYMCdUb9XMqnF3yEGHU0rECV0i2tHc30wu4FmG3Lg1ki2j6f
d4qrKEHBw3dQOK1sP5lmEjyEIUzQSTqjwEJeMi3UTO7u1bpHskykemYmhkmmN219b1lEVsyOkVOV
huj/S3Tax+VaWL8lsYQk+FQupgWFl80KxNEnyqxORu+zkopUlILWiWcnlQkAJEO5DB61kgOJo4oa
o3oFpovVEOQxd5zr/CJeKgtQv7BhPj1c++5yQozZkOX9j9/Lcg9hj10/6Zftw8V8dgwpaPTw+iuA
XCLefXy4bt7YHLKUbzBdX3vV7271i3wYRbwRWzqXS4lSmIAgB1TuAo7y6FgYZkfaoJfZSUhotoc5
Gh4RPlemru58B+6RRPlILRmRjPfs/18lurb6GfyR8iL1inE8Ynm0TCNrmkfVEwVNk0teXDsdtzrK
RUQaQUb0JWvt3ycg45m1YSk07cMAyYs+xUxtvYR33SFpdWemN96V36wC1GsBzSrwAOLlTlXFnsqL
Ue11f8K2gtghA23c7WqBrHIO/dLpai7/Ie2KP60hsKJh2tNtzHdkticgYuA0X/usJlXbMawZRdMO
Vx63+aAwalQ0DntaZveLwpwHaePQXw5wRz6J2u0NjjBApVC8W0miDj7enJwot7ZqNSWVEnhcZCp4
ZOqFr3c7MXcQ9SfC845ZpDx4Fh6YafJzlMk/6K4CuB9UoqnJYI2WhZ7INqrDwfLc/Ip72sS3iwgG
l5kEwG4bztBcA/nfguTSOHwPUcKtq/qH1t5lbvAm3WS4eFTn0a3q18cZpJwSdksdpPCPjieajjyJ
i/MR6JWYD7fXgQQvd1Bft+hwe617sh2QRJ94CMZM16dvbmTklAh/X8O9OtPikEVQdGSHZPMgtVs9
SgD2fD7JrjQaBI+5xZfuc274JBbowFi3lVs1GfoUDSPhXuIk9ZUQh6tl9lEk5UMxJgkKFNgmCAWM
pA1qDhtN4bUR1QIeZZE1YkRsFrjxvbJYt9BdA00yLCSKmR7Y/1ow7VtUU/RJFkD1kjtLnC8V7hXe
dswBIB4ggQdiStn8wZKQ8QrEL/IhnUGnGT9wGa5pnKOIooCCpasvba9WF8ztbQkERIGRdnm9nGiX
wrIe4+2958bEuMNZHJInYnf7ILRuor5F1PEAGxPoyNsNs+xRi+hoyuVhgxKBfmhgpOJwxxEH/bQE
KYdfpS+Ehk+TOUF/8UMmqtnR4qs+OA77r1SxoeyRYgwq3FSmTnkubtCiigYWsTE2Azce9+ErT+zy
5FcffiTwy4Oj4QUO13LAM9vGlqM/TXTxwpfVkL/JxsTP2TXQns6DKxbokR8fldFrQEXSngU/dOpX
hgDJxE5rrYRH+RRQjDpE8XAzmC98ah4VtJPWe73EC8um5PPShaOzvMfNKRSjFCpOYvcOtEsCFXT4
6zWa1O8tPyQ4OGccjEVFeAj+gquBiXT3OjX8rl0vHd1Ks4nRbrXqQfhOHfZktQYGRM3QnhFHbnT1
gejDg136MeO1L3mUKprolIKomQPyoXsEeGATpmrFigDH5lY03Caff4JoJGoJPpfPM5tHS3AoGJ4L
p7GjY2kOMfK3kr7cxE9BO/rwcXCsWEk8g2zpcwb8XUvgXSEHqry4JuULMMvkEa5lwQ5b2uiFZ3rM
HyVeJtmei0BClKB9UPt0KevUNxAFswl6/eOMLDT44520nKtVDA+rdHuc08XzfRdvosSBBqMRpkGy
gY/9+5g/CRJ6OBHtkC6CPGB+7RTleNNlsohFNdTNIrmQ89O9IGT7v1Hun7Q0YyNnUSfuXSdImqth
mxMlwZI445GActLK79jq80u4T/CvJsHismibnrtmna9YlNK2KSLS2HMKLljtrIZickBQbiaJ2nf7
rDw6pLG88P4rWs7lOzkYmPl4GoCP1H63wrJaUywS5O6dm4DKWbOfd97jbjXHzSPcK/K/FX3e9iRG
ZGlYNo8fDjwXg8BvppNEDsBsf3levG+hd4PIP1hqxK1PY7Gh+BZd2otYplkQ5Gt06vwMnNzBVzig
2PT4oq37nyh5zkXieMnRGdIP4ppSSBh8KyYV28HdaQF1NlH6KYVMDg3AV1k4LvI19/A61xbQSgo7
8h48S8CE6vdTICzn/o49uC82/DpvXOdYtzW7vBYk5Q4qwtmIVuTUPFqU7LHov3o0XgReADua4NEO
N8M1sYR1kU2cISigkjFfmRKLarJBJx+wtnhnzcON0+I9QV1VfMWdzEP4EFlq6EAgZaG/WuKChKho
DqL7zYGjZMqhLWyIZuSPAx14UvBqp5ciOe3fa4qMOq4OSXqzhlWtLUHKsYJO0PsNR1T75rGJ+3Wa
qzcDqn6HK/yYVQfzRA7rpomW7iF42GVIAV2rG+QFs0yXt+wS2GGFjG9PIMdD3aJ0Rw47wFlXszCO
aea1eJGLojKMJZG5ah5RxJny3Fhehg94OS5seXaIYw8TBfG37w2VJOXa65Vc/2zfqHhebiCKd4oZ
+qY1WvSZny/WejMPHj4hgdf5MjCq/UyMvz2z1/tbqK0Rt3qk9U8J00s/3T0yaptHlzh+0+FRPA0g
cXJKEXJLGnuKUHmQjpcoIyILNcM5+RUM5I6WqDkczvvGdgQicwxFyIPZBsBsN9wcTYAVvzwvfAef
F2PBWuK0RlWegKGkI0qCHr9zypisjIjeifux9wZgXKTDeX67FbxqBWG+xZOFtSXj1ytOhkqRQMz/
niyXWYTiZqR/FLs4ClEQ9+dajkGjbWctrInYygq+9pBlsHNTHl9fFqfS53fBrRKpGM8yi/5pSiDU
2nThOZntqfBLwXMV3IrapK+f/USdMn/6v7G3sTrsNaWLnFnHGM6s2ZLYTxOrpo6A8X++7EvZD5EC
pDMR1c4QQtH2pAul5z2RMzBKAKRm4Jv1UwG5i8Ctir2Elfvz3M3u2b1hVT8lPa7wTk2r47NQf9fH
ybCp7XS0FDflWXHfmoAGY0sIY5xZX/rVTY/sD4cOhW0WTpCMspIWUjb/sZ8CE/smqgFsjI19SGst
FwjHwb8kVzXTx+4V5ODMUkKwd906WxSSQBlG5tgTdKNjuPLm43evt/pSncEvpvi3MQ7MEWq39TbU
QZV44+IeuF38lxkRZrs5xhFOCJRyLUqpXlHd208pq6NWrvZERDnXwP2Z79iLHrp+ItjmaiO7HuPT
Is0MvqqKfFpyRGjWaVyTOiBMSytmdyu6uxW5OLqEli2kDWp0kFQkCxOsufcxs9zyXZRimW19w8yJ
A9n8TxRSWcoQaxS6gVnqBoDADegseKNYCHRd1qfO1U0AVVjziQ5UB0hPGHxFVMNZijjItNT0ml3w
0CKGKoaOzFYttlDRvKi+w9iTlDubjE/Ib1mTzhbAfkMLOSPnzB9TvHEzquAdR72/AYbaQe4czdIc
LD9OcpdnZS61x85sRWS6lJ9l+OX0lbRTIqJ2weK3eWIwqHpb9RCdPzb4tO5rVZm29uOn1V3U0MZc
v8EuNolnfJWnGWF9fjQ8dJZKrKdOGCYinSs6/IvHsHzuz9BNugivwp1FRnGGBDK5HJgItxwACXhz
lKtPjdCwgUgNuKrbJJaHffpARodeWkW191h2XkAF8JiHtGacUNJnesgpXey2zke3B1YdzVDvKyya
BALa6gOAh4UOFcpIkqbzWVFC8mzZaULVw2ywmiT9EzQtIVsbTcPy+03sqNUdTUYyG7iFEVq/AMO2
MqQk1xiiucA5o08ImbKdBLJ1MMe1cQ3zkxrI/mTBpU0ZxeZyWXGOo+61KgQfJL6XnhqL6EUHE/Ii
fC5Wmm5SK8RhGluvPGqXmH6mmxvmLaY8xCFUEp69DEMKQapdP1gntKu7K50za910pKtGn7eiuyap
5IU+Bb4h/xipxIF++0iz6ekG62dwwMhsLLvoMY2w8r/0UjStjgb93kfVnjI4S55jdR3VShGA8zNW
eb8GJnEJB0Z+JwFMV3+vivVx61vL6O2lrW94FZ95XFvk8eR1aChaGkvw4mx79fI8zf+QEQTzb3E4
yZCZxfqmguCop39OuzxQ2vo2I0FR6JQk0s+M5Xb9Zgksi6yc6A9TMxZ50nUJu9GJh85FfFaYMuID
e8vS9GLKNnkKbE+54vKEatxciU3lXydFnFsSae5Iz2sjS/zb5GrV72gziBgJcQSDfI/b+3rPf5an
/zpy9H6JYkg+Zr4PhIH62/LLfCCc2mTqiw97m/qH9kqgNM2pug1cnbiy2sQ/ka9lqGM/nMXzM9/L
IEoKoWCR2ff984BiNE4FqSS1/Mfx99b3Mey2KS94EIE8RT0R12W/G9FFwXzlfNth13FuFRV8rHlq
UqSIcS9TM9vt9MwTv293j9EreS7K/dQYj0Iu+zbdyHCGnyP9x+V8oBa+F6WQeT3TMNJFls4CAE79
lws3yGu2rVRL7YJeD7y+PiKLPSpv/X2A1ESoKd6FsELNRXTLrZbtG4JpJHTsPgAzsQoLX9liZwf/
jOCF16H5cqu7kF88y2EKRBxSt6HeWTMBvuB/jt5Nd9ZQKyCwvnhX5TShXA2ETv/wHZk5EViCNfyj
93oGmoqNQ7LhttHZjNKgf3KuDBpPT7hQW+J3WFSFzucqI5h3xI78AqrnD7jYSEWJlBY0DGCxGc62
KA9FqmMowQWVXhNAPPsedOjRQoEejTQ+MtKRpHRwMD/KweE0/xMOEAuvgi1lugHWK6kSWifhWHof
VIcgBF4Wf+YdX09s+Eu3GZnrew4aAEIJJEWCuq+1E/xufUgAM6VeMxTcdtp6Pj5Gi+3GsXJ5e3Pf
GazcLWZG4itsy+yP8NiiP5uPhwrXT1rjxke5/Q0KAyeThL1hWbG22xUwPGijyktBZmhRCJH0z6M5
AL7TrX9C8LV78UEqbc0Puo0DLl+3XveC1wRnbZBx2KxNxD7xpXVWsiRWU5pXQgLauic3Kpdccmxm
uGFVqngRFunzjFbLFvplZ2VWS9arpA8MwwcRRNUgu2cXj33YEvE4fGesBdXvu/QrOL8fnklTc3ZO
XQPblajuzXPkLGp2wDIlTo/KPU5tyDZP+JsX17mvq6C+lh7MII+u9tQg9h7cWe9LpEFq3l2EjDjm
ZM1w3i9hZ+qcJ9iVq9UYxnkp9fMts24g9ccY+xyTEWFiNqR5lXAki/wVqAL66tCETFCVbpec3KMz
ROc9H0EEasfpSwRwHuiCMdTznpd0hyUmeDSp43g8qY/RGfemWSqmJP0JfKQOtTX8rj14E6PzY8Q/
XKIRrHxXcRFB0ywmoev/bSYuVslIbTI/DIe6HzwOwCEpWsN1TBDvdvKjjsfg+G7R03Du9YQDCPJt
vP/eS8j5H0V07Ex5bwIN1Xb1qndhFxjl9KCkbAuqp4ToCfB4FPSKFGYTCYppFqKhmONmtyeboA+e
QdrXBmS6O7LxnIgdANZPnLca/vvGkc3eEcqvSzhD+SsFCvjU56vyZ+MiPXreC+aDHQykLS4sXECc
I4lxaK80fm6Q8tGUqZLH4tazHekw8ns61Un6InFGogvxr3LgUxbzmD42trlH/blJubFdVAirosW0
tFU2QU0eslns95n9CjNdAScvKu1EqmViIkrqeMaNN9aDV5XnvK4aEcIraxrRbklcRGUCQ406L2OQ
vxq0wWZbd0Nbw+HvHGbvnieZhq7kKow71P5nKu66zW129898r17uZ34LDlyhANNBwJshD1SWgg/C
7pHxODHYg4DDnmP4spka7hTmG2QN6o3PdZyRdXGHx/Sl/zxoKMxn6iQ+T3a5CuYAvNG+Na/ua0Bg
ozbz0WzJHTvty1/T/p3asHxMLaPKo9zgkUNr1HARJSOOSJrKGBdSlMDQD32NulOi9bKANA1bzi5p
/sDGnEg+kelSTpmQwC84OboHH38myXAqVcH/OX3LUx0KiM3SkWvnwb9WiyR7LxoahLGy6oKJfOQw
5yAfkL+tKzipiAhrH3FAq8bcNzNfj0q+j01F9hWLKxMy3k+FT2PEMpZSdo6pJAoe+JJ5mOyv3tFi
lJLZOeXDuH6r+ot3eeZNrbISL0es1DCUi/5E8Jm8cyoAHextWz3vurnhr6WWXmaWEU24OPmJ8tfu
di+sTGkxZw2LhkTewIoY1x7vtmxrXWC/2JIa6TsUGMy3aq7+AYywSV/L+1Xf6OK8J6nP8WKee1bH
EoILv3E7SyP/e7vXC0NoQPz4nMKrlZq3M3z9FYRhVzqTDd8GzJbuRk/WQK+WgnIa3FtupPSvkMho
a46UcgIdxx/M6rfMHQqSL/8FvGorrYn55vfG1YQMrUU4nPEDEucX/zVLO1DUEncrGkEMGJrd699c
4WQcyz38VNxmOCF9CA+4Ozq3AlJkU4VZBCeKlP+bFSoFv535ZYgC6RoUEBSOwjnjeYPUDXjF497b
4lhs1FNvi5xwM8TtHh4ykdE740raCtD7EZ+urTHyVC6qWbwO7e/zqxVlSDGbFuylYTi/fVk+Uq6F
yoJKu/2CWAhFT8F7B7Z6dQOSJQ7NHWMNEPAQm/lD1RvB582NNFCYTJf5CB5DpPKI58MOrVmxTQaZ
kEXdE8DPohgirq1Fcc/vN6eVLV2VupsUQW3oknpvYexWiOli4kDRiuNqyS1crvPXPpcLzfP7+eBy
fdVE3uT21tbR05ZgP+A/dpiKX/fOVKrmTnDaZ1t5NR2xEnV5FNXOTPUJzCwMvhVM8Mx7LWVbncdU
/db4FSVyz7GlsudvyyjCyqbQ44fqZsUILzV+ZRoNCCXC9pItYn2TCfaeoRuQJZxmSUUeD4Jn0Sw9
5nNvKoje29Lt4Okr81BK2H3X5GF+gTpJFzTx9QeM+yyAUY+FitKyrPYeQYjanoLsO+IQkKLnQjmD
ZZEl8T1VV4WJ2MKFU1rsSCsh8E+bpP/j5m+GlBOS4IcAGSHiySBaGYD5OXD1IuVeZ0tSMrL6B17j
cqdFjWSHsGC7qGcgdEJ778kItm/RJ5PGslfUQGzJVPP/X7V60rGAWmM8uEUpWqXVnfAkK+ZvfKWt
0XZlO+Y92uKqhNPZJnVCXlu9i3V9CFsZFZb9Rkm3JaPXToUazJmj7u+zeEGqni5gLobseWp9BIZ1
buW1hDrN1YUNzTWHR1B6i/MltaNujZ21iW3HcE3RJzRUQC10HmVfcsEWLwPxSDnnS1mi0mRqVuFM
1O7Xq30w1E12rvSYt5f/TysV3I5vQZEwU3i7uLJL255FY9FxfYEI3+s0ZcIDVrHOfkEPnwhOmCq4
a+ngdx0tbuh7m8BZyRViFCYlHsMGftQJ/NchWbmpA8j6J05c7ODeqNxZFv+O15w1yiVAlSZmSlj2
w9+HXZcBGmPPMk8Z2ftwVfrv+3ERb7g9VW3r8syhTQWGTZDdGUFP5IrPrmhfZS1pazI4N2/ytuLs
nKOUdIjHR9HMe6ZvywbN9iAGMlJ3JOnzhkH9psiT6U5T1Nxvk1/dvRQfgxcrdzLdce5XUJnsDZ2t
IgXDi1PkP4yGSKP6FRGSHfHcMcYyOpDT4uKciHQVTe/gRhwwMWJOhO/mNas2mhaiqd7OvXVdmxaD
vyiF0QJrcL/ThKXeAgL390pMemow/OumMccTUUQDYgy4lcdgKLeCZFGhL+OHEJkkE4sXhBvP7Y5A
ocKj80/omZSSINn1torQczoiRyBg1v5ntw2kbt9FClvdYdAI9k+rvp6bwflRqwZowJ1KsKYiXqQw
0Tr+UG5JXDwgc3VpY9KuoCbneTXqp21NprOH31OJRWCiPiWGVVybf8O29xQ/mNM8sYWJ3HN+Y6ZC
pZyvLZDw5g/LmWJFJoi+EOX4lJAGqk4jEppDaknEBruEjX56EIY/5hRsHqOCXUo0ArtmfGT9cBii
WAdlmwjTm6JiUZZzV1nMYT+iGaOPOHqPyICtql5AifhFZ2/Q0gJWcBcbr3x8po5MRG0K1qi6shUj
dsdi6h2kqbr1306OXdn+6UgNosOzA3uVqUrGPCLePz7jecv6OYZCHzoHw74vgzRceIf59Hhon9As
FdNFpqaKdglriNNoJ/JvTAG3Q1H8nWVJGg5BIEbknHJHM+TzOl5wTNwRftLpy8xNgN3c8f6hynH2
+f5pbIQ84UptsFd492y9EZV2ZwLk+lhr3ExSoRuUb8yGK0VBmednsAEt1t4okre6ye4PmI+36Rfg
GFYuxcfnRk7p67azb68ixpHKzveL8O5QhyRygHL/fwhFNCuobHnPLCjFTUsGIzajTHLhowKVOAWQ
NYQKifV2Ds7ru/VZoLBQa4uo5O0wk6Y0MM8AY3mgQKTysmXQQe7km5niAMA40VfuFp+PiHJts5Ki
LWxW
`pragma protect end_protected

2
gowin/bttn/impl/gwsynthesis/bttn.vgZone.Identifier
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[ZoneTransfer]
ZoneId=3

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gowin/bttn/impl/gwsynthesis/bttn_syn.rpt.html
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>synthesis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper{ width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table td.label { min-width: 100px; width: 8%;}
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.9.03 Education (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Jan 21 15:29:04 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>bttn</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.694s, Peak memory usage = 153.727MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 153.727MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 153.727MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 153.727MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 153.793MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 153.871MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 153.926MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 153.941MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 153.969MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 153.973MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 153.977MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 3s, Peak memory usage = 185.441MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 185.441MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.304s, Peak memory usage = 185.441MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 2s, Elapsed time = 0h 0m 4s, Peak memory usage = 185.441MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>28</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>28</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>14</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>14</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>141</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>16</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>36</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>89</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>141(141 LUT, 0 ALU) / 20736</td>
<td><1%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>0 / 46</td>
<td>0%</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Hierarchy Module Resource</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
div#main_wrapper{ width: 100%; }
h1 {text-align: center; }
h1 {margin-top: 36px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { align = "center"; padding: 5px 2px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="content">
<h1>Hierarchy Module Resource</h1>
<table>
<tr>
<th class="label">MODULE NAME</th>
<th class="label">REG NUMBER</th>
<th class="label">ALU NUMBER</th>
<th class="label">LUT NUMBER</th>
<th class="label">DSP NUMBER</th>
<th class="label">BSRAM NUMBER</th>
<th class="label">SSRAM NUMBER</th>
<th class="label">ROM16 NUMBER</th>
</tr>
<tr>
<td class="label">bttn (//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">13</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp|--s1
(//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">128</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<Module name="bttn" Lut="13" T_Lut="141(13)">
<SubModule name="s1" Lut="128" T_Lut="128(128)"/>
</Module>

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gowin/bttn/impl/pnr/bttn.log
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Reading netlist file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg"
Parsing netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg" completed
Processing netlist completed
Reading constraint file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst"
Physical Constraint parsed completed
Running placement......
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
[30%] Placement Phase 2 completed
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.power.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.pin.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.rpt.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.rpt.txt" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.tr.html" completed
Tue Jan 21 15:29:17 2025

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gowin/bttn/impl/pnr/bttn.power.html
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//ENhttp://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Power Analysis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper { width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td {white-space:pre; border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.thermal_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.Configure_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table th.label { min-width: 8%; width: 8%; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#Message" style=" font-size: 16px;">Power Messages</a>
<ul>
<li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li>
</ul>
</li>
<li><a href="#Summary" style=" font-size: 16px;">Power Summary</a>
<ul>
<li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li>
<li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li>
<li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li>
</ul>
</li>
<li><a href="#Detail" style=" font-size: 16px;">Power Details</a>
<ul>
<li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li>
<li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li>
<li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="Message">Power Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Power Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.9.03 Education (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Jan 21 15:29:12 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h2><a name="Configure_Info">Configure Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Grade</td>
<td>Commercial</td>
</tr>
<tr>
<td class="label">Process</td>
<td>Typical</td>
</tr>
<tr>
<td class="label">Ambient Temperature</td>
<td>25.000
</tr>
<tr>
<td class="label">Use Custom Theta JA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Heat Sink</td>
<td>None</td>
</tr>
<tr>
<td class="label">Air Flow</td>
<td>LFM_0</td>
</tr>
<tr>
<td class="label">Use Custom Theta SA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Board Thermal Model</td>
<td>None</td>
</tr>
<tr>
<td class="label">Use Custom Theta JB</td>
<td>false</td>
</tr>
<tr>
<td class="label">Related Vcd File</td>
<td></td>
</tr>
<tr>
<td class="label">Related Saif File</td>
<td></td>
</tr>
<tr>
<td class="label">Filter Glitches</td>
<td>false</td>
</tr>
<tr>
<td class="label">Default IO Toggle Rate</td>
<td>0.125</td>
</tr>
<tr>
<td class="label">Default Remain Toggle Rate</td>
<td>0.125</td>
</tr>
</table>
<h1><a name="Summary">Power Summary</a></h1>
<h2><a name="Power_Info">Power Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Total Power (mW)</td>
<td>124.522</td>
</tr>
<tr>
<td class="label">Quiescent Power (mW)</td>
<td>121.169</td>
</tr>
<tr>
<td class="label">Dynamic Power (mW)</td>
<td>3.353</td>
</tr>
</table>
<h2><a name="Thermal_Info">Thermal Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Junction Temperature</td>
<td>28.987</td>
</tr>
<tr>
<td class="label">Theta JA</td>
<td>32.020</td>
</tr>
<tr>
<td class="label">Max Allowed Ambient Temperature</td>
<td>81.013</td>
</tr>
</table>
<h2><a name="Supply_Summary">Supply Information:</a></h2>
<table class="summary_table">
<tr>
<th class="label">Voltage Source</th>
<th class="label">Voltage</th>
<th class="label">Dynamic Current(mA)</th>
<th class="label">Quiescent Current(mA)</th>
<th class="label">Power(mW)</th>
</tr>
<tr>
<td>VCC</td>
<td>1.000</td>
<td>0.552</td>
<td>69.981</td>
<td>70.533</td>
</tr>
<tr>
<td>VCCX</td>
<td>3.300</td>
<td>0.552</td>
<td>15.000</td>
<td>51.322</td>
</tr>
<tr>
<td>VCCIO18</td>
<td>1.800</td>
<td>0.544</td>
<td>0.938</td>
<td>2.668</td>
</tr>
</table>
<h1><a name="Detail">Power Details</a></h1>
<h2><a name="By_Block_Type">Power By Block Type:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Block Type</th>
<th class="label">Total Power(mW)</th>
<th class="label">Static Power(mW)</th>
<th class="label">Average Toggle Rate(millions of transitions/sec)</th>
</tr>
<tr>
<td>IO</td>
<td>8.544
<td>5.191
<td>6.250
</tr>
</table>
<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Hierarchy Entity</th>
<th class="label">Total Power(mW)</th>
<th class="label">Block Dynamic Power(mW)</th>
</tr>
<tr>
<td>bttn</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>bttn/s1/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
</table>
<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Domain</th>
<th class="label">Clock Frequency(Mhz)</th>
<th class="label">Total Dynamic Power(mW)</th>
</tr>
<tr>
<td>NO CLOCK DOMAIN</td>
<td>0.000</td>
<td>0.000</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
1. PnR Messages
<Report Title>: PnR Report
<Design File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg
<Physical Constraints File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst
<Timing Constraints File>: ---
<Tool Version>: V1.9.9.03 Education (64-bit)
<Part Number>: GW2A-LV18PG256C8/I7
<Device>: GW2A-18
<Device Version>: C
<Created Time>:Tue Jan 21 15:29:16 2025
2. PnR Details
Running placement:
Placement Phase 0: CPU time = 0h 0m 0.131s, Elapsed time = 0h 0m 0.131s
Placement Phase 1: CPU time = 0h 0m 0.403s, Elapsed time = 0h 0m 0.402s
Placement Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s
Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Running routing:
Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.001s
Routing Phase 1: CPU time = 0h 0m 0.21s, Elapsed time = 0h 0m 0.21s
Routing Phase 2: CPU time = 0h 0m 0.263s, Elapsed time = 0h 0m 0.264s
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Total Routing: CPU time = 0h 0m 0.475s, Elapsed time = 0h 0m 0.475s
Generate output files:
CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s
Total Time and Memory Usage: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 413MB
3. Resource Usage Summary
----------------------------------------------------------
Resources | Usage
----------------------------------------------------------
Logic | 141/20736 <1%
--LUT,ALU,ROM16 | 141(141 LUT, 0 ALU, 0 ROM16)
--SSRAM(RAM16) | 0
Register | 0/16173 0%
--Logic Register as Latch | 0/15552 0%
--Logic Register as FF | 0/15552 0%
--I/O Register as Latch | 0/621 0%
--I/O Register as FF | 0/621 0%
CLS | 75/10368 <1%
I/O Port | 28
I/O Buf | 28
--Input Buf | 14
--Output Buf | 14
--Inout Buf | 0
IOLOGIC | 0%
BSRAM | 0%
DSP | 0%
PLL | 0/4 0%
DCS | 0/8 0%
DQCE | 0/24 0%
OSC | 0/1 0%
CLKDIV | 0/8 0%
DLLDLY | 0/8 0%
DQS | 0/9 0%
DHCEN | 0/16 0%
==========================================================
4. I/O Bank Usage Summary
-----------------------
I/O Bank | Usage
-----------------------
bank 0 | 1/29(3%)
bank 1 | 5/20(25%)
bank 2 | 2/20(10%)
bank 3 | 8/32(25%)
bank 4 | 2/36(5%)
bank 5 | 0/36(0%)
bank 6 | 2/18(11%)
bank 7 | 8/16(50%)
=======================
5. Global Clock Usage Summary
-------------------------------
Global Clock | Usage
-------------------------------
PRIMARY | 0/8(0%)
LW | 0/8(0%)
GCLK_PIN | 1/8(13%)
PLL | 0/4(0%)
CLKDIV | 0/8(0%)
DLLDLY | 0/8(0%)
===============================
6. Global Clock Signals
-------------------------------------------
Signal | Global Clock | Location
-------------------------------------------
===========================================
7. Pinout by Port Name
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | BankVccio
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
A[0] | | A11/7 | Y | in | IOL15[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
A[1] | | N6/3 | Y | in | IOR51[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
A[2] | | E15/1 | Y | in | IOT44[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | NA | NA | 1.8
A[3] | | L9/3 | Y | in | IOR40[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
B[0] | | B11/7 | Y | in | IOL13[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
B[1] | | D11/7 | Y | in | IOL22[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
B[2] | | N7/3 | Y | in | IOR47[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
B[3] | | N8/3 | Y | in | IOR40[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
opCodeA[0] | | T5/4 | Y | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
opCodeA[1] | | T4/4 | Y | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
opCodeA[2] | | E8/6 | Y | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
select[0] | | A15/7 | Y | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
select[1] | | A14/7 | Y | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
Cin | | E9/6 | Y | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
leds[0] | | L16/1 | Y | out | IOT34[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
leds[1] | | L14/1 | Y | out | IOT34[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
Y[0] | | P6/3 | Y | out | IOR53[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[1] | | T7/3 | Y | out | IOR29[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[2] | | P8/3 | Y | out | IOR42[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[3] | | P9/3 | Y | out | IOR38[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[4] | | T11/2 | Y | out | IOR24[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[5] | | T12/2 | Y | out | IOR17[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[6] | | M14/1 | Y | out | IOT40[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
Y[7] | | J14/0 | Y | out | IOT22[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
Y[8] | | D14/1 | Y | out | IOT44[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
Y[9] | | B14/7 | Y | out | IOL2[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[10] | | B13/7 | Y | out | IOL8[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[11] | | B12/7 | Y | out | IOL7[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
===================================================================================================================================================================================================================
8. All Package Pins
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | Bank Vccio
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
L15/0 | - | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D16/0 | - | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E14/0 | - | in | IOT4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C16/0 | - | in | IOT5[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D15/0 | - | in | IOT5[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E16/0 | - | in | IOT6[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F15/0 | - | in | IOT6[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F13/0 | - | in | IOT8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G12/0 | - | in | IOT8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F14/0 | - | in | IOT9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F16/0 | - | in | IOT9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F12/0 | - | in | IOT12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G13/0 | - | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G15/0 | - | in | IOT13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G14/0 | - | in | IOT13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G11/0 | - | in | IOT14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H12/0 | - | in | IOT14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G16/0 | - | in | IOT16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H15/0 | - | in | IOT16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H13/0 | - | in | IOT18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J12/0 | - | in | IOT18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H14/0 | - | in | IOT20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H16/0 | - | in | IOT20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J16/0 | - | in | IOT22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J14/0 | Y[7] | out | IOT22[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
J15/0 | - | in | IOT24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K16/0 | - | in | IOT24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H11/0 | - | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J13/0 | - | in | IOT27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K14/1 | - | in | IOT30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K15/1 | - | in | IOT30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J11/1 | - | in | IOT32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L12/1 | - | in | IOT32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L16/1 | leds[0] | out | IOT34[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
L14/1 | leds[1] | out | IOT34[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
K13/1 | - | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K12/1 | - | in | IOT36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K11/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L13/1 | - | in | IOT38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M14/1 | Y[6] | out | IOT40[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
M15/1 | - | in | IOT40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D14/1 | Y[8] | out | IOT44[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
E15/1 | A[2] | in | IOT44[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | NA | NA | 1.8
N15/1 | - | in | IOT48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P16/1 | - | in | IOT48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N16/1 | - | in | IOT52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N14/1 | - | in | IOT52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P15/1 | - | in | IOT54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R16/1 | - | in | IOT54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
A4/5 | - | in | IOB2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C5/5 | - | in | IOB2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D6/5 | - | in | IOB3[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E7/5 | - | in | IOB3[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A3/5 | - | in | IOB4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B4/5 | - | in | IOB4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A5/5 | - | in | IOB7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B6/5 | - | in | IOB7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B1/5 | - | in | IOB8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C2/5 | - | in | IOB8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D3/5 | - | in | IOB9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D1/5 | - | in | IOB9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E2/5 | - | in | IOB12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E3/5 | - | in | IOB12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B3/5 | - | in | IOB13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A2/5 | - | in | IOB13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C1/5 | - | in | IOB14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D2/5 | - | in | IOB14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E1/5 | - | in | IOB16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F2/5 | - | in | IOB16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F4/5 | - | in | IOB18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G6/5 | - | in | IOB18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F3/5 | - | in | IOB19[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F1/5 | - | in | IOB19[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G5/5 | - | in | IOB20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G4/5 | - | in | IOB20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G2/5 | - | in | IOB21[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G3/5 | - | in | IOB21[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F5/5 | - | in | IOB22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H6/5 | - | in | IOB22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G1/5 | - | in | IOB24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H2/5 | - | in | IOB24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H4/5 | - | in | IOB26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J6/5 | - | in | IOB26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J1/5 | - | in | IOB27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J3/5 | - | in | IOB27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L2/4 | - | in | IOB30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M1/4 | - | in | IOB30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H3/4 | - | in | IOB32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H1/4 | - | in | IOB32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J2/4 | - | in | IOB34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K1/4 | - | in | IOB34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H5/4 | - | in | IOB35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J4/4 | - | in | IOB35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K3/4 | - | in | IOB36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K2/4 | - | in | IOB36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J5/4 | - | in | IOB37[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K6/4 | - | in | IOB37[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L1/4 | - | in | IOB38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L3/4 | - | in | IOB38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K4/4 | - | in | IOB39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L5/4 | - | in | IOB39[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K5/4 | - | in | IOB40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L4/4 | - | in | IOB40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N2/4 | - | in | IOB41[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P1/4 | - | in | IOB41[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M3/4 | - | in | IOB42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N1/4 | - | in | IOB42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M2/4 | - | in | IOB43[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N3/4 | - | in | IOB43[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R1/4 | - | in | IOB44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P2/4 | - | in | IOB44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P4/4 | - | in | IOB45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T4/4 | opCodeA[1] | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R3/4 | - | in | IOB48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T2/4 | - | in | IOB48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P5/4 | - | in | IOB50[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R5/4 | - | in | IOB50[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R4/4 | - | in | IOB52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T3/4 | - | in | IOB52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R6/4 | - | in | IOB54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T5/4 | opCodeA[0] | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
B14/7 | Y[9] | out | IOL2[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
A15/7 | select[0] | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
C12/7 | - | in | IOL7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B12/7 | Y[11] | out | IOL7[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
B13/7 | Y[10] | out | IOL8[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
A14/7 | select[1] | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
F10/7 | - | in | IOL11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B11/7 | B[0] | in | IOL13[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
A12/7 | - | in | IOL13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A11/7 | A[0] | in | IOL15[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
C11/7 | - | in | IOL15[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D10/7 | - | in | IOL17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E10/7 | - | in | IOL17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D11/7 | B[1] | in | IOL22[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
A9/7 | - | in | IOL27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C9/7 | - | in | IOL27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C8/6 | - | in | IOL29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A8/6 | - | in | IOL29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F9/6 | - | in | IOL31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E11/6 | - | in | IOL31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B9/6 | - | in | IOL33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A10/6 | - | in | IOL33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F8/6 | - | in | IOL35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D9/6 | - | in | IOL35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D8/6 | - | in | IOL38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E9/6 | Cin | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
B7/6 | - | in | IOL40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C7/6 | - | in | IOL40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F7/6 | - | in | IOL45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E8/6 | opCodeA[2] | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
C4/6 | - | in | IOL47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B5/6 | - | in | IOL47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E6/6 | - | in | IOL53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D7/6 | - | in | IOL53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
T15/2 | - | in | IOR7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R14/2 | - | in | IOR7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P12/2 | - | in | IOR8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T13/2 | - | in | IOR8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R12/2 | - | in | IOR11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P13/2 | - | in | IOR11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R11/2 | - | in | IOR17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T12/2 | Y[5] | out | IOR17[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
R13/2 | - | in | IOR20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T14/2 | - | in | IOR20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M10/2 | - | in | IOR22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N11/2 | - | in | IOR22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T11/2 | Y[4] | out | IOR24[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
P11/2 | - | in | IOR24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C6/2 | - | out | IOR25[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
B8/2 | - | in | IOR25[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A7/2 | - | in | IOR26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A6/2 | - | in | IOR26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N10/2 | - | in | IOR27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M11/2 | - | in | IOR27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T7/3 | Y[1] | out | IOR29[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
R8/3 | - | in | IOR29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M16/3 | - | in | IOR30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B16/3 | - | in | IOR30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C15/3 | - | in | IOR31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B10/3 | - | in | IOR31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A13/3 | - | in | IOR32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C13/3 | - | in | IOR32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P10/3 | - | in | IOR33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R10/3 | - | in | IOR33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M9/3 | - | in | IOR34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L10/3 | - | in | IOR34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R9/3 | - | in | IOR35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T10/3 | - | in | IOR35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M8/3 | - | in | IOR36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N9/3 | - | in | IOR36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T9/3 | - | in | IOR38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P9/3 | Y[3] | out | IOR38[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
C10/3 | - | in | IOR39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N8/3 | B[3] | in | IOR40[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
L9/3 | A[3] | in | IOR40[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
P8/3 | Y[2] | out | IOR42[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
T8/3 | - | in | IOR42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M6/3 | - | in | IOR44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L8/3 | - | in | IOR44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M7/3 | - | in | IOR47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N7/3 | B[2] | in | IOR47[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
R7/3 | - | in | IOR49[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P7/3 | - | in | IOR49[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N6/3 | A[1] | in | IOR51[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
P6/3 | Y[0] | out | IOR53[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
T6/3 | - | in | IOR53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
========================================================================================================================================================================================

2
gowin/bttn/impl/pnr/bttn.rpt.txtZone.Identifier
View File

@ -1,2 +0,0 @@
[ZoneTransfer]
ZoneId=3

0
gowin/bttn/impl/pnr/bttn.timing_paths
View File

2
gowin/bttn/impl/pnr/bttn.timing_pathsZone.Identifier
View File

@ -1,2 +0,0 @@
[ZoneTransfer]
ZoneId=3

10
gowin/bttn/impl/pnr/bttn.tr.html
View File

@ -1,10 +0,0 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Timing Analysis Report</title>
</head>
<frameset cols="20%, 80%">
<frame src="bttn_tr_cata.html" name="cataFrame" />
<frame src="bttn_tr_content.html" name="mainFrame"/>
</frameset>
</html>

2
gowin/bttn/impl/pnr/bttn.tr.htmlZone.Identifier
View File

@ -1,2 +0,0 @@
[ZoneTransfer]
ZoneId=3

132
gowin/bttn/impl/pnr/bttn_tr_cata.html
View File

@ -1,132 +0,0 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Timing Report Navigation</title>
<style type="text/css">
@import url(../temp/style.css);
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#catalog_wrapper { width: 100%; }
div#catalog ul { list-style: none; margin-left: -15px; }
div#catalog ul li { margin: 3px 0 3px 0; text-align: left; color: #0084ff; white-space: nowrap; word-break: keep-all; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 4px; margin: 0 0 0 0; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
div.triangle_fake, div.triangle { display: inline-block; cursor: pointer; width: 8px; height: 0; border-top: 5px solid transparent; border-bottom: 5px solid transparent; }
div.triangle_fake { border-left: 5px solid transparent; }
div.triangle { border-left: 5px solid #0084ff; }
div.triangle:hover { border-left-color: #000; }
</style>
<script>
function onClick(obj){var childs=obj.parentNode.childNodes;for(var i=0;i<childs.length;i++){if(childs[i].tagName=="UL"){if(childs[i].style.display=="none"){childs[i].style.display="block"}else{childs[i].style.display="none"}}}};
</script>
</head>
<body>
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<!-- messages begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Message" target="mainFrame" style=" font-size: 16px;">Timing Messages</a></li>
<!-- messages end-->
<!-- summaries begin-->
<li><div class="triangle" onclick="onClick(this)"></div><a href="bttn_tr_content.html#Summary" style=" font-size: 16px;" target="mainFrame">Timing Summaries</a>
<ul>
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#STA_Tool_Run_Summary" style=" font-size: 14px;" target="mainFrame">STA Tool Run Summary</a></li>
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Clock_Report" style=" font-size: 14px;" target="mainFrame">Clock Summary</a></li>
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Max_Frequency_Report" style=" font-size: 14px;" target="mainFrame">Max Frequency Summary</a></li>
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Total_Negative_Slack_Report" style=" font-size: 14px;" target="mainFrame">Total Negative Slack Summary</a></li>
</ul>
</li>
<!-- summaries end-->
<!-- details begin-->
<li><div class="triangle" onclick="onClick(this)"></div><a href="bttn_tr_content.html#Detail" style=" font-size: 16px;" target="mainFrame">Timing Details</a>
<ul>
<!--All_Path_Slack_Table begin-->
<li><div class="triangle" onclick="onClick(this)"></div><a href="bttn_tr_content.html#All_Path_Slack_Table" style=" font-size: 14px;" target="mainFrame">Path Slacks Table</a>
<ul>
<!--Setup_Slack_Table begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Setup_Slack_Table" style=" font-size: 13px;" target="mainFrame">Setup Paths Table</a>
</li>
<!--Setup_Slack_Table end-->
<!--Hold_Slack_Table begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Hold_Slack_Table" style=" font-size: 13px;" target="mainFrame">Hold Paths Table</a>
</li>
<!--Hold_Slack_Table end-->
<!--Recovery_Slack_Table begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Recovery_Slack_Table" style=" font-size: 13px;" target="mainFrame">Recovery Paths Table</a>
</li>
<!--Recovery_Slack_Table end-->
<!--Removal_Slack_Table begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Removal_Slack_Table" style=" font-size: 13px;" target="mainFrame">Removal Paths Table</a>
</li>
<!--Removal_Slack_Table end-->
</ul>
</li><!--All_Path_Slack_Table end-->
<!--MIN_PULSE_WIDTH_TABLE begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#MIN_PULSE_WIDTH_TABLE" style=" font-size: 14px;" target="mainFrame">Minimum Pulse Width Table</a>
</li>
<!--MIN_PULSE_WIDTH_TABLE end-->
<!--Timing_Report_by_Analysis_Type begin-->
<li><div class="triangle" onclick="onClick(this)"></div><a href="bttn_tr_content.html#Timing_Report_by_Analysis_Type" style=" font-size: 14px;" target="mainFrame">Timing Report By Analysis Type</a>
<ul>
<!--Setup_Analysis begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Setup_Analysis" style=" font-size: 13px;" target="mainFrame">Setup Analysis Report</a>
</li>
<!--Setup_Analysis end-->
<!--Hold_Analysis begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Hold_Analysis" style=" font-size: 13px;" target="mainFrame">Hold Analysis Report</a>
</li>
<!--Hold_Analysis end-->
<!--Recovery_Analysis begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Recovery_Analysis" style=" font-size: 13px;" target="mainFrame">Recovery Analysis Report</a>
</li>
<!--Recovery_Analysis end-->
<!--Removal_Analysis begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Removal_Analysis" style=" font-size: 13px;" target="mainFrame">Removal Analysis Report</a>
</li>
<!--Removal_Analysis end-->
</ul>
</li>
<!--Timing_Report_by_Analysis_Type end-->
<!--Minimum_Pulse_Width_Report begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Minimum_Pulse_Width_Report" style=" font-size: 14px;" target="mainFrame">Minimum Pulse Width Report</a>
</li>
<!--Minimum_Pulse_Width_Report end-->
<!--High_Fanout_Nets_Report begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#High_Fanout_Nets_Report" style=" font-size: 14px;" target="mainFrame">High Fanout Nets Report</a></li>
<!--High_Fanout_Nets_Report end-->
<!--Route_Congestions_Report begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Route_Congestions_Report" style=" font-size: 14px;" target="mainFrame">Route Congestions Report</a></li>
<!--Route_Congestions_Report end-->
<!--Timing_Exceptions_Report begin-->
<li><div class="triangle" onclick="onClick(this)"></div><a href="bttn_tr_content.html#Timing_Exceptions_Report" style=" font-size: 14px;" target="mainFrame">Timing Exceptions Report</a>
<ul>
<!--Setup_Analysis_Exceptions begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Setup_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Setup Analysis Report</a>
</li>
<!--Setup_Analysis_Exceptions end-->
<!--Hold_Analysis_Exceptions begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Hold_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Hold Analysis Report</a>
</li>
<!--Hold_Analysis_Exceptions end-->
<!--Recovery_Analysis_Exceptions begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Recovery_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Recovery Analysis Report</a>
</li>
<!--Recovery_Analysis_Exceptions end-->
<!--Removal_Analysis_Exceptions begin-->
<li><div class="triangle_fake" onclick="onClick(this)"></div><a href="bttn_tr_content.html#Removal_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Removal Analysis Report</a>
</li>
<!--Removal_Analysis_Exceptions end-->
</ul>
</li>
<!--Timing_Exceptions_Report end-->
<!--SDC_Report begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#SDC_Report" style=" font-size: 14px;" target="mainFrame">Timing Constraints Report</a></li>
<!--SDC_Report end-->
</ul>
</li>
<!-- details end-->
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
</body>
</html>

2
gowin/bttn/impl/pnr/bttn_tr_cata.htmlZone.Identifier
View File

@ -1,2 +0,0 @@
[ZoneTransfer]
ZoneId=3

257
gowin/bttn/impl/pnr/bttn_tr_content.html
View File

@ -1,257 +0,0 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Timing Analysis Report</title>
<style type="text/css">
@import url(../temp/style.css);
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#content { width: 100%; margin: }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td {white-space:pre; border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table th.label { min-width: 8%; width: 8%; }
</style>
</head>
<body>
<div id="content">
<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.9.03 Education (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Jan 21 15:29:17 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.95V 85C C8/I7</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.05V 0C C8/I7</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>158</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>14</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
</table>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h4>Nothing to report!</h4>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h4>No setup paths to report!</h4>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h4>No hold paths to report!</h4>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>No recovery paths to report!</h4>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>No removal paths to report!</h4>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h4>Nothing to report!</h4>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R27C30</td>
<td>43.06%</td>
</tr>
<tr>
<td>R29C29</td>
<td>43.06%</td>
</tr>
<tr>
<td>R27C29</td>
<td>40.28%</td>
</tr>
<tr>
<td>R26C29</td>
<td>33.33%</td>
</tr>
<tr>
<td>R26C30</td>
<td>31.94%</td>
</tr>
<tr>
<td>R29C28</td>
<td>30.56%</td>
</tr>
<tr>
<td>R29C30</td>
<td>29.17%</td>
</tr>
<tr>
<td>R27C28</td>
<td>26.39%</td>
</tr>
<tr>
<td>R27C31</td>
<td>25.00%</td>
</tr>
<tr>
<td>R26C28</td>
<td>25.00%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
</div><!-- content -->
</body>
</html>

2
gowin/bttn/impl/pnr/bttn_tr_content.htmlZone.Identifier
View File

@ -1,2 +0,0 @@
[ZoneTransfer]
ZoneId=3

13
gowin/bttn/impl/pnr/cmd.do
View File

@ -1,13 +0,0 @@
-d \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg
-p GW2A-18C-PBGA256-8
-pn GW2A-LV18PG256C8/I7
-cst \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst
-cfg \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\device.cfg
-bit
-tr
-ph
-timing
-cst_error
-correct_hold 1
-route_maxfan 23
-global_freq 100.000

2
gowin/bttn/impl/pnr/cmd.doZone.Identifier
View File

@ -1,2 +0,0 @@
[ZoneTransfer]
ZoneId=3

21
gowin/bttn/impl/pnr/device.cfg
View File

@ -1,21 +0,0 @@
set JTAG regular_io = false
set SSPI regular_io = false
set MSPI regular_io = false
set READY regular_io = false
set DONE regular_io = false
set I2C regular_io = false
set RECONFIG_N regular_io = false
set unused_pin = default
set CRC_check = true
set compress = false
set encryption = false
set security_bit_enable = true
set bsram_init_fuse_print = true
set background_programming = off
set secure_mode = false
set program_done_bypass = false
set wake_up = 0
set format = binary
set power_on_reset_monitor = true
set multiboot_spi_flash_address = 0x00000000
set vccx = 3.3

2
gowin/bttn/impl/pnr/device.cfgZone.Identifier
View File

@ -1,2 +0,0 @@
[ZoneTransfer]
ZoneId=3

702
gowin/bttn/impl/temp/rtl_parser.result
View File

@ -1,702 +0,0 @@
[
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
"InstLine" : 1,
"InstName" : "bttn",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
"ModuleLine" : 1,
"ModuleName" : "bttn",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
"InstLine" : 13,
"InstName" : "a1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
"ModuleLine" : 1,
"ModuleName" : "ALU",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
"InstLine" : 18,
"InstName" : "opCd",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/opCode.v",
"ModuleLine" : 1,
"ModuleName" : "opCode"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
"InstLine" : 20,
"InstName" : "aU",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
"ModuleLine" : 1,
"ModuleName" : "arithmeticUnit",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
"InstLine" : 13,
"InstName" : "a1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"ModuleLine" : 1,
"ModuleName" : "addition",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 11,
"InstName" : "f0",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 12,
"InstName" : "f1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 13,
"InstName" : "f2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 14,
"InstName" : "f3",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
"InstLine" : 14,
"InstName" : "s1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
"ModuleLine" : 1,
"ModuleName" : "subtraction",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
"InstLine" : 11,
"InstName" : "f0",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "fullsubtraction",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 8,
"InstName" : "hf1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 9,
"InstName" : "hf2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
"InstLine" : 12,
"InstName" : "f1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "fullsubtraction",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 8,
"InstName" : "hf1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 9,
"InstName" : "hf2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
"InstLine" : 13,
"InstName" : "f2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "fullsubtraction",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 8,
"InstName" : "hf1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 9,
"InstName" : "hf2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
"InstLine" : 14,
"InstName" : "f3",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "fullsubtraction",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 8,
"InstName" : "hf1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 9,
"InstName" : "hf2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
}
]
}
]
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
"InstLine" : 21,
"InstName" : "lU",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/logicUnit.v",
"ModuleLine" : 1,
"ModuleName" : "logicUnit"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
"InstLine" : 22,
"InstName" : "mU",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v",
"ModuleLine" : 1,
"ModuleName" : "multiplier",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v",
"InstLine" : 26,
"InstName" : "add0",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"ModuleLine" : 1,
"ModuleName" : "addition",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 11,
"InstName" : "f0",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 12,
"InstName" : "f1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 13,
"InstName" : "f2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 14,
"InstName" : "f3",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v",
"InstLine" : 42,
"InstName" : "add1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"ModuleLine" : 1,
"ModuleName" : "addition",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 11,
"InstName" : "f0",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 12,
"InstName" : "f1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 13,
"InstName" : "f2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 14,
"InstName" : "f3",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v",
"InstLine" : 58,
"InstName" : "add2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"ModuleLine" : 1,
"ModuleName" : "addition",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 11,
"InstName" : "f0",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 12,
"InstName" : "f1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 13,
"InstName" : "f2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 14,
"InstName" : "f3",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
}
]
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
"InstLine" : 76,
"InstName" : "btod1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"ModuleLine" : 1,
"ModuleName" : "BinaryToBCD",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 14,
"InstName" : "d1t",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 23,
"InstName" : "d2u",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 32,
"InstName" : "d3v",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 41,
"InstName" : "d4w",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 50,
"InstName" : "d5x",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 59,
"InstName" : "d6y",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 68,
"InstName" : "d7z",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
}
]
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
"InstLine" : 14,
"InstName" : "s1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/selector.v",
"ModuleLine" : 1,
"ModuleName" : "selector"
}
]
}
]

2
gowin/bttn/impl/temp/rtl_parser.resultZone.Identifier
View File

@ -1,2 +0,0 @@
[ZoneTransfer]
ZoneId=3

73
gowin/bttn/impl/temp/rtl_parser_arg.json
View File

@ -1,73 +0,0 @@
{
"Device" : "GW2A-18C",
"Files" : [
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/logicUnit.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/opCode.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/selector.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
"Type" : "verilog"
}
],
"IncludePath" : [
],
"LoopLimit" : 2000,
"ResultFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/impl/temp/rtl_parser.result",
"Top" : "",
"VerilogStd" : "verilog_2001",
"VhdlStd" : "vhdl_93"
}

2
gowin/bttn/impl/temp/rtl_parser_arg.jsonZone.Identifier
View File

@ -1,2 +0,0 @@
[ZoneTransfer]
ZoneId=3

0
gowin/bttn/impl/temp/style.css
View File

2
gowin/bttn/impl/temp/style.cssZone.Identifier
View File

@ -1,2 +0,0 @@
[ZoneTransfer]
ZoneId=3

2191
gowin/bttn/src/bttn
View File

File diff suppressed because it is too large Load Diff

1103
gowin/bttn/src/bttn.vcd
View File

File diff suppressed because it is too large Load Diff

0
gowin/bttn/src/bttn.cst → gowin/bttn/src/top.cst
View File

10
gowin/bttn/src/bttn.v → gowin/bttn/src/top.v
View File

@ -1,4 +1,4 @@
module bttn (
module top (
input [3:0] A, B,
input [2:0] opCodeA,
input [1:0] select,
@ -10,10 +10,10 @@ module bttn (
wire wire1, wire2;
wire [11:0] selectY;
ALU a1(.A(A), .B(B), .opCodeA(opCodeA), .CarryIN(Cin), .bcd(selectY), .CarryOUT(wire2), .overflow(wire1));
selector s1(.A(A), .B(B), .opCodeA(opCodeA), .select(select), .ALUY(selectY), .Y(Y));
ALU a1(.A(A), .B(B), .opCodeA(opCodeA), .CarryIN(Cin), .bcd(selectY), .CarryOUT(wire2), .overflow(wire1)); //ALU module
selector s1(.A(A), .B(B), .opCodeA(opCodeA), .select(select), .ALUY(selectY), .Y(Y)); // selector for 7 segment
assign leds[0] = ~wire1;
assign leds[1] = ~wire2;
assign leds[0] = ~wire1; //overflow led
assign leds[1] = ~wire2; //CarryOut/BorrowOut led
endmodule

6
gowin/bttn/src/bttnTB.v → gowin/bttn/src/topTB.v
View File

@ -1,11 +1,11 @@
module bttnTB();
module topTB();
reg [3:0] A,B;
reg [2:0] opCodeA;
reg [1:0] select;
wire [11:0] Y;
bttn uut (
top uut (
.A(A),
.B(B),
.opCodeA(opCodeA),
@ -14,7 +14,7 @@ bttn uut (
);
initial begin
$dumpfile("bttn.vcd");
$dumpfile("top.vcd");
$dumpvars;
A = 4'b0001; B = 4'b0110; opCodeA = 3'b000; select = 2'b01; #5;
$finish;

0
project0.2/selector.v → project0.2/!NOTUSE!selector.v
View File

32
project0.2/PU.v
View File

@ -1,32 +0,0 @@
module PU (
input A, // Dividend bit
input B, // Divisor bit
input Cin, // Carry input
input S, // Select input for the mux
output Y, // Output of the PU
output COut // Carry output from the full adder
);
wire Sum, notB;
// Invert B for subtraction
not n1 (notB, B);
// Full adder performs A - B + Cin
fulladder f1 (
.A(A),
.B(notB),
.Carry(Cin),
.Sum(Sum),
.CarryO(COut)
);
// 2:1 multiplexer to select between A and Sum
mux2 m1 (
.A0(A), // Input 0 of mux
.A1(Sum), // Input 1 of mux
.S(S), // Select line
.Y(Y) // Output of the mux
);
endmodule

9
project0.2/aluboard.v
View File

@ -1,9 +0,0 @@
module aluboard (
input [3:0] select,
input [7:0] Y,
input [3:0] A, B,
input [2:0] opCodeA,
output [7:0] sO
);
ALU alu0 ()

391
project0.2/divider4
View File

@ -1,391 +0,0 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55ec337fbbf0 .scope module, "divider4TB" "divider4TB" 2 1;
.timescale 0 0;
v0x55ec33821ff0_0 .var "Dividend", 3 0;
v0x55ec338220d0_0 .var "Divisor", 1 0;
v0x55ec33822170_0 .net "Quotient", 3 0, L_0x55ec338251a0; 1 drivers
v0x55ec33822240_0 .net "Remainder", 2 0, L_0x55ec33825510; 1 drivers
S_0x55ec337fa3a0 .scope module, "uut" "divider4" 2 12, 3 1 0, S_0x55ec337fbbf0;
.timescale 0 0;
.port_info 0 /INPUT 4 "Dividend";
.port_info 1 /INPUT 2 "Divisor";
.port_info 2 /OUTPUT 4 "Quotient";
.port_info 3 /OUTPUT 3 "Remainder";
L_0x55ec338251a0 .functor BUFZ 4, L_0x55ec338252b0, C4<0000>, C4<0000>, C4<0000>;
v0x55ec338218a0_0 .net "Carry", 3 0, L_0x55ec338253d0; 1 drivers
v0x55ec338219a0_0 .net "Dividend", 3 0, v0x55ec33821ff0_0; 1 drivers
v0x55ec33821a80_0 .net "Divisor", 1 0, v0x55ec338220d0_0; 1 drivers
v0x55ec33821b40_0 .net "Quotient", 3 0, L_0x55ec338251a0; alias, 1 drivers
v0x55ec33821c20_0 .net "Remainder", 2 0, L_0x55ec33825510; alias, 1 drivers
v0x55ec33821d50_0 .net "S0", 0 0, L_0x55ec33822310; 1 drivers
v0x55ec33821df0_0 .net "S1", 0 0, L_0x55ec338223e0; 1 drivers
v0x55ec33821e90_0 .net "Y", 3 0, L_0x55ec338252b0; 1 drivers
L_0x55ec33822310 .part L_0x55ec338253d0, 3, 1;
L_0x55ec338223e0 .part L_0x55ec338253d0, 2, 1;
L_0x55ec33822d50 .part v0x55ec33821ff0_0, 3, 1;
L_0x55ec33822e40 .part v0x55ec338220d0_0, 1, 1;
L_0x55ec338238c0 .part v0x55ec33821ff0_0, 2, 1;
L_0x55ec33823960 .part v0x55ec338220d0_0, 1, 1;
L_0x55ec33823a90 .part L_0x55ec338253d0, 3, 1;
L_0x55ec338243b0 .part v0x55ec33821ff0_0, 1, 1;
L_0x55ec33824530 .part v0x55ec338220d0_0, 0, 1;
L_0x55ec33824660 .part L_0x55ec338253d0, 2, 1;
L_0x55ec33825060 .part v0x55ec33821ff0_0, 0, 1;
L_0x55ec33825100 .part v0x55ec338220d0_0, 0, 1;
L_0x55ec33825210 .part L_0x55ec338253d0, 1, 1;
L_0x55ec338252b0 .concat8 [ 1 1 1 1], L_0x55ec33824ff0, L_0x55ec338242f0, L_0x55ec33823800, L_0x55ec33822c60;
L_0x55ec338253d0 .concat8 [ 1 1 1 1], L_0x55ec33824db0, L_0x55ec338240b0, L_0x55ec338235c0, L_0x55ec33822a20;
L_0x55ec33825510 .part L_0x55ec338253d0, 0, 3;
S_0x55ec337f9f60 .scope module, "PU1" "PU" 3 17, 4 1 0, S_0x55ec337fa3a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Cin";
.port_info 3 /INPUT 1 "S";
.port_info 4 /OUTPUT 1 "Y";
.port_info 5 /OUTPUT 1 "COut";
L_0x55ec33822480 .functor NOT 1, L_0x55ec33822e40, C4<0>, C4<0>, C4<0>;
v0x55ec33819cb0_0 .net "A", 0 0, L_0x55ec33822d50; 1 drivers
v0x55ec33819d70_0 .net "B", 0 0, L_0x55ec33822e40; 1 drivers
v0x55ec33819e30_0 .net "COut", 0 0, L_0x55ec33822a20; 1 drivers
L_0x7f82dfd33018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x55ec33819ed0_0 .net "Cin", 0 0, L_0x7f82dfd33018; 1 drivers
v0x55ec33819fc0_0 .net "S", 0 0, L_0x55ec33822310; alias, 1 drivers
v0x55ec3381a0b0_0 .net "Sum", 0 0, L_0x55ec33822870; 1 drivers
v0x55ec3381a150_0 .net "Y", 0 0, L_0x55ec33822c60; 1 drivers
v0x55ec3381a1f0_0 .net "notB", 0 0, L_0x55ec33822480; 1 drivers
S_0x55ec337f9a30 .scope module, "f1" "fulladder" 4 16, 5 1 0, S_0x55ec337f9f60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x55ec33822a20 .functor OR 1, L_0x55ec338224f0, L_0x55ec33822730, C4<0>, C4<0>;
v0x55ec33818dd0_0 .net "A", 0 0, L_0x55ec33822d50; alias, 1 drivers
v0x55ec33818e90_0 .net "B", 0 0, L_0x55ec33822480; alias, 1 drivers
v0x55ec33818f60_0 .net "Carry", 0 0, L_0x7f82dfd33018; alias, 1 drivers
v0x55ec33819060_0 .net "CarryO", 0 0, L_0x55ec33822a20; alias, 1 drivers
v0x55ec33819100_0 .net "Sum", 0 0, L_0x55ec33822870; alias, 1 drivers
v0x55ec338191f0_0 .net "and1", 0 0, L_0x55ec338224f0; 1 drivers
v0x55ec338192c0_0 .net "and2", 0 0, L_0x55ec33822730; 1 drivers
v0x55ec33819390_0 .net "xor1", 0 0, L_0x55ec338226a0; 1 drivers
S_0x55ec337f7800 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55ec337f9a30;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x55ec338224f0 .functor AND 1, L_0x55ec33822d50, L_0x55ec33822480, C4<1>, C4<1>;
L_0x55ec338226a0 .functor XOR 1, L_0x55ec33822d50, L_0x55ec33822480, C4<0>, C4<0>;
v0x55ec337f5bd0_0 .net "A", 0 0, L_0x55ec33822d50; alias, 1 drivers
v0x55ec337f7e00_0 .net "B", 0 0, L_0x55ec33822480; alias, 1 drivers
v0x55ec337f36f0_0 .net "Carry", 0 0, L_0x55ec338224f0; alias, 1 drivers
v0x55ec337f5980_0 .net "Sum", 0 0, L_0x55ec338226a0; alias, 1 drivers
S_0x55ec33818960 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55ec337f9a30;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x55ec33822730 .functor AND 1, L_0x55ec338226a0, L_0x7f82dfd33018, C4<1>, C4<1>;
L_0x55ec33822870 .functor XOR 1, L_0x55ec338226a0, L_0x7f82dfd33018, C4<0>, C4<0>;
v0x55ec337f7bb0_0 .net "A", 0 0, L_0x55ec338226a0; alias, 1 drivers
v0x55ec337f9de0_0 .net "B", 0 0, L_0x7f82dfd33018; alias, 1 drivers
v0x55ec33818b90_0 .net "Carry", 0 0, L_0x55ec33822730; alias, 1 drivers
v0x55ec33818c60_0 .net "Sum", 0 0, L_0x55ec33822870; alias, 1 drivers
S_0x55ec33819480 .scope module, "m1" "mux2" 4 25, 7 1 0, S_0x55ec337f9f60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A0";
.port_info 1 /INPUT 1 "A1";
.port_info 2 /INPUT 1 "S";
.port_info 3 /OUTPUT 1 "Y";
L_0x55ec33822ad0 .functor NOT 1, L_0x55ec33822310, C4<0>, C4<0>, C4<0>;
L_0x55ec33822b60 .functor AND 1, L_0x55ec33822870, L_0x55ec33822310, C4<1>, C4<1>;
L_0x55ec33822bf0 .functor AND 1, L_0x55ec33822ad0, L_0x55ec33822d50, C4<1>, C4<1>;
L_0x55ec33822c60 .functor OR 1, L_0x55ec33822b60, L_0x55ec33822bf0, C4<0>, C4<0>;
v0x55ec33819660_0 .net "A0", 0 0, L_0x55ec33822d50; alias, 1 drivers
v0x55ec33819750_0 .net "A1", 0 0, L_0x55ec33822870; alias, 1 drivers
v0x55ec33819860_0 .net "S", 0 0, L_0x55ec33822310; alias, 1 drivers
v0x55ec33819900_0 .net "Y", 0 0, L_0x55ec33822c60; alias, 1 drivers
v0x55ec338199a0_0 .net "and1", 0 0, L_0x55ec33822b60; 1 drivers
v0x55ec33819ab0_0 .net "and2", 0 0, L_0x55ec33822bf0; 1 drivers
v0x55ec33819b70_0 .net "notS", 0 0, L_0x55ec33822ad0; 1 drivers
S_0x55ec3381a320 .scope module, "PU2" "PU" 3 26, 4 1 0, S_0x55ec337fa3a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Cin";
.port_info 3 /INPUT 1 "S";
.port_info 4 /OUTPUT 1 "Y";
.port_info 5 /OUTPUT 1 "COut";
L_0x55ec33822fb0 .functor NOT 1, L_0x55ec33823960, C4<0>, C4<0>, C4<0>;
v0x55ec3381c350_0 .net "A", 0 0, L_0x55ec338238c0; 1 drivers
v0x55ec3381c410_0 .net "B", 0 0, L_0x55ec33823960; 1 drivers
v0x55ec3381c4d0_0 .net "COut", 0 0, L_0x55ec338235c0; 1 drivers
v0x55ec3381c570_0 .net "Cin", 0 0, L_0x55ec33823a90; 1 drivers
v0x55ec3381c660_0 .net "S", 0 0, L_0x55ec33822310; alias, 1 drivers
v0x55ec3381c750_0 .net "Sum", 0 0, L_0x55ec33823410; 1 drivers
v0x55ec3381c7f0_0 .net "Y", 0 0, L_0x55ec33823800; 1 drivers
v0x55ec3381c890_0 .net "notB", 0 0, L_0x55ec33822fb0; 1 drivers
S_0x55ec3381a5c0 .scope module, "f1" "fulladder" 4 16, 5 1 0, S_0x55ec3381a320;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x55ec338235c0 .functor OR 1, L_0x55ec33823020, L_0x55ec338232d0, C4<0>, C4<0>;
v0x55ec3381b3d0_0 .net "A", 0 0, L_0x55ec338238c0; alias, 1 drivers
v0x55ec3381b490_0 .net "B", 0 0, L_0x55ec33822fb0; alias, 1 drivers
v0x55ec3381b560_0 .net "Carry", 0 0, L_0x55ec33823a90; alias, 1 drivers
v0x55ec3381b660_0 .net "CarryO", 0 0, L_0x55ec338235c0; alias, 1 drivers
v0x55ec3381b700_0 .net "Sum", 0 0, L_0x55ec33823410; alias, 1 drivers
v0x55ec3381b7f0_0 .net "and1", 0 0, L_0x55ec33823020; 1 drivers
v0x55ec3381b8c0_0 .net "and2", 0 0, L_0x55ec338232d0; 1 drivers
v0x55ec3381b990_0 .net "xor1", 0 0, L_0x55ec33823240; 1 drivers
S_0x55ec3381a7a0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55ec3381a5c0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x55ec33823020 .functor AND 1, L_0x55ec338238c0, L_0x55ec33822fb0, C4<1>, C4<1>;
L_0x55ec33823240 .functor XOR 1, L_0x55ec338238c0, L_0x55ec33822fb0, C4<0>, C4<0>;
v0x55ec3381a9d0_0 .net "A", 0 0, L_0x55ec338238c0; alias, 1 drivers
v0x55ec3381aab0_0 .net "B", 0 0, L_0x55ec33822fb0; alias, 1 drivers
v0x55ec3381ab70_0 .net "Carry", 0 0, L_0x55ec33823020; alias, 1 drivers
v0x55ec3381ac40_0 .net "Sum", 0 0, L_0x55ec33823240; alias, 1 drivers
S_0x55ec3381adb0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55ec3381a5c0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x55ec338232d0 .functor AND 1, L_0x55ec33823240, L_0x55ec33823a90, C4<1>, C4<1>;
L_0x55ec33823410 .functor XOR 1, L_0x55ec33823240, L_0x55ec33823a90, C4<0>, C4<0>;
v0x55ec3381b020_0 .net "A", 0 0, L_0x55ec33823240; alias, 1 drivers
v0x55ec3381b0f0_0 .net "B", 0 0, L_0x55ec33823a90; alias, 1 drivers
v0x55ec3381b190_0 .net "Carry", 0 0, L_0x55ec338232d0; alias, 1 drivers
v0x55ec3381b260_0 .net "Sum", 0 0, L_0x55ec33823410; alias, 1 drivers
S_0x55ec3381ba80 .scope module, "m1" "mux2" 4 25, 7 1 0, S_0x55ec3381a320;
.timescale 0 0;
.port_info 0 /INPUT 1 "A0";
.port_info 1 /INPUT 1 "A1";
.port_info 2 /INPUT 1 "S";
.port_info 3 /OUTPUT 1 "Y";
L_0x55ec33823670 .functor NOT 1, L_0x55ec33822310, C4<0>, C4<0>, C4<0>;
L_0x55ec33823700 .functor AND 1, L_0x55ec33823410, L_0x55ec33822310, C4<1>, C4<1>;
L_0x55ec33823790 .functor AND 1, L_0x55ec33823670, L_0x55ec338238c0, C4<1>, C4<1>;
L_0x55ec33823800 .functor OR 1, L_0x55ec33823700, L_0x55ec33823790, C4<0>, C4<0>;
v0x55ec3381bcd0_0 .net "A0", 0 0, L_0x55ec338238c0; alias, 1 drivers
v0x55ec3381bdc0_0 .net "A1", 0 0, L_0x55ec33823410; alias, 1 drivers
v0x55ec3381bed0_0 .net "S", 0 0, L_0x55ec33822310; alias, 1 drivers
v0x55ec3381bfc0_0 .net "Y", 0 0, L_0x55ec33823800; alias, 1 drivers
v0x55ec3381c060_0 .net "and1", 0 0, L_0x55ec33823700; 1 drivers
v0x55ec3381c150_0 .net "and2", 0 0, L_0x55ec33823790; 1 drivers
v0x55ec3381c210_0 .net "notS", 0 0, L_0x55ec33823670; 1 drivers
S_0x55ec3381c9e0 .scope module, "PU3" "PU" 3 36, 4 1 0, S_0x55ec337fa3a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Cin";
.port_info 3 /INPUT 1 "S";
.port_info 4 /OUTPUT 1 "Y";
.port_info 5 /OUTPUT 1 "COut";
L_0x55ec33823b30 .functor NOT 1, L_0x55ec33824530, C4<0>, C4<0>, C4<0>;
v0x55ec3381ea80_0 .net "A", 0 0, L_0x55ec338243b0; 1 drivers
v0x55ec3381eb40_0 .net "B", 0 0, L_0x55ec33824530; 1 drivers
v0x55ec3381ec00_0 .net "COut", 0 0, L_0x55ec338240b0; 1 drivers
v0x55ec3381eca0_0 .net "Cin", 0 0, L_0x55ec33824660; 1 drivers
v0x55ec3381ed90_0 .net "S", 0 0, L_0x55ec338223e0; alias, 1 drivers
v0x55ec3381ee80_0 .net "Sum", 0 0, L_0x55ec33823f00; 1 drivers
v0x55ec3381ef20_0 .net "Y", 0 0, L_0x55ec338242f0; 1 drivers
v0x55ec3381efc0_0 .net "notB", 0 0, L_0x55ec33823b30; 1 drivers
S_0x55ec3381cc60 .scope module, "f1" "fulladder" 4 16, 5 1 0, S_0x55ec3381c9e0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x55ec338240b0 .functor OR 1, L_0x55ec33823ba0, L_0x55ec33823dc0, C4<0>, C4<0>;
v0x55ec3381db30_0 .net "A", 0 0, L_0x55ec338243b0; alias, 1 drivers
v0x55ec3381dbf0_0 .net "B", 0 0, L_0x55ec33823b30; alias, 1 drivers
v0x55ec3381dcc0_0 .net "Carry", 0 0, L_0x55ec33824660; alias, 1 drivers
v0x55ec3381ddc0_0 .net "CarryO", 0 0, L_0x55ec338240b0; alias, 1 drivers
v0x55ec3381de60_0 .net "Sum", 0 0, L_0x55ec33823f00; alias, 1 drivers
v0x55ec3381df50_0 .net "and1", 0 0, L_0x55ec33823ba0; 1 drivers
v0x55ec3381e020_0 .net "and2", 0 0, L_0x55ec33823dc0; 1 drivers
v0x55ec3381e0f0_0 .net "xor1", 0 0, L_0x55ec33823d30; 1 drivers
S_0x55ec3381cec0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55ec3381cc60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x55ec33823ba0 .functor AND 1, L_0x55ec338243b0, L_0x55ec33823b30, C4<1>, C4<1>;
L_0x55ec33823d30 .functor XOR 1, L_0x55ec338243b0, L_0x55ec33823b30, C4<0>, C4<0>;
v0x55ec3381d130_0 .net "A", 0 0, L_0x55ec338243b0; alias, 1 drivers
v0x55ec3381d210_0 .net "B", 0 0, L_0x55ec33823b30; alias, 1 drivers
v0x55ec3381d2d0_0 .net "Carry", 0 0, L_0x55ec33823ba0; alias, 1 drivers
v0x55ec3381d3a0_0 .net "Sum", 0 0, L_0x55ec33823d30; alias, 1 drivers
S_0x55ec3381d510 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55ec3381cc60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x55ec33823dc0 .functor AND 1, L_0x55ec33823d30, L_0x55ec33824660, C4<1>, C4<1>;
L_0x55ec33823f00 .functor XOR 1, L_0x55ec33823d30, L_0x55ec33824660, C4<0>, C4<0>;
v0x55ec3381d780_0 .net "A", 0 0, L_0x55ec33823d30; alias, 1 drivers
v0x55ec3381d850_0 .net "B", 0 0, L_0x55ec33824660; alias, 1 drivers
v0x55ec3381d8f0_0 .net "Carry", 0 0, L_0x55ec33823dc0; alias, 1 drivers
v0x55ec3381d9c0_0 .net "Sum", 0 0, L_0x55ec33823f00; alias, 1 drivers
S_0x55ec3381e1e0 .scope module, "m1" "mux2" 4 25, 7 1 0, S_0x55ec3381c9e0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A0";
.port_info 1 /INPUT 1 "A1";
.port_info 2 /INPUT 1 "S";
.port_info 3 /OUTPUT 1 "Y";
L_0x55ec33824160 .functor NOT 1, L_0x55ec338223e0, C4<0>, C4<0>, C4<0>;
L_0x55ec338241f0 .functor AND 1, L_0x55ec33823f00, L_0x55ec338223e0, C4<1>, C4<1>;
L_0x55ec33824280 .functor AND 1, L_0x55ec33824160, L_0x55ec338243b0, C4<1>, C4<1>;
L_0x55ec338242f0 .functor OR 1, L_0x55ec338241f0, L_0x55ec33824280, C4<0>, C4<0>;
v0x55ec3381e430_0 .net "A0", 0 0, L_0x55ec338243b0; alias, 1 drivers
v0x55ec3381e520_0 .net "A1", 0 0, L_0x55ec33823f00; alias, 1 drivers
v0x55ec3381e630_0 .net "S", 0 0, L_0x55ec338223e0; alias, 1 drivers
v0x55ec3381e6d0_0 .net "Y", 0 0, L_0x55ec338242f0; alias, 1 drivers
v0x55ec3381e770_0 .net "and1", 0 0, L_0x55ec338241f0; 1 drivers
v0x55ec3381e880_0 .net "and2", 0 0, L_0x55ec33824280; 1 drivers
v0x55ec3381e940_0 .net "notS", 0 0, L_0x55ec33824160; 1 drivers
S_0x55ec3381f0f0 .scope module, "PU4" "PU" 3 45, 4 1 0, S_0x55ec337fa3a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Cin";
.port_info 3 /INPUT 1 "S";
.port_info 4 /OUTPUT 1 "Y";
.port_info 5 /OUTPUT 1 "COut";
L_0x55ec338247f0 .functor NOT 1, L_0x55ec33825100, C4<0>, C4<0>, C4<0>;
v0x55ec33821210_0 .net "A", 0 0, L_0x55ec33825060; 1 drivers
v0x55ec338212d0_0 .net "B", 0 0, L_0x55ec33825100; 1 drivers
v0x55ec33821390_0 .net "COut", 0 0, L_0x55ec33824db0; 1 drivers
v0x55ec33821430_0 .net "Cin", 0 0, L_0x55ec33825210; 1 drivers
v0x55ec33821520_0 .net "S", 0 0, L_0x55ec338223e0; alias, 1 drivers
v0x55ec33821610_0 .net "Sum", 0 0, L_0x55ec33824c00; 1 drivers
v0x55ec338216b0_0 .net "Y", 0 0, L_0x55ec33824ff0; 1 drivers
v0x55ec33821750_0 .net "notB", 0 0, L_0x55ec338247f0; 1 drivers
S_0x55ec3381f370 .scope module, "f1" "fulladder" 4 16, 5 1 0, S_0x55ec3381f0f0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x55ec33824db0 .functor OR 1, L_0x55ec33824860, L_0x55ec33824ac0, C4<0>, C4<0>;
v0x55ec33820290_0 .net "A", 0 0, L_0x55ec33825060; alias, 1 drivers
v0x55ec33820350_0 .net "B", 0 0, L_0x55ec338247f0; alias, 1 drivers
v0x55ec33820420_0 .net "Carry", 0 0, L_0x55ec33825210; alias, 1 drivers
v0x55ec33820520_0 .net "CarryO", 0 0, L_0x55ec33824db0; alias, 1 drivers
v0x55ec338205c0_0 .net "Sum", 0 0, L_0x55ec33824c00; alias, 1 drivers
v0x55ec338206b0_0 .net "and1", 0 0, L_0x55ec33824860; 1 drivers
v0x55ec33820780_0 .net "and2", 0 0, L_0x55ec33824ac0; 1 drivers
v0x55ec33820850_0 .net "xor1", 0 0, L_0x55ec33824a30; 1 drivers
S_0x55ec3381f5f0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55ec3381f370;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x55ec33824860 .functor AND 1, L_0x55ec33825060, L_0x55ec338247f0, C4<1>, C4<1>;
L_0x55ec33824a30 .functor XOR 1, L_0x55ec33825060, L_0x55ec338247f0, C4<0>, C4<0>;
v0x55ec3381f890_0 .net "A", 0 0, L_0x55ec33825060; alias, 1 drivers
v0x55ec3381f970_0 .net "B", 0 0, L_0x55ec338247f0; alias, 1 drivers
v0x55ec3381fa30_0 .net "Carry", 0 0, L_0x55ec33824860; alias, 1 drivers
v0x55ec3381fb00_0 .net "Sum", 0 0, L_0x55ec33824a30; alias, 1 drivers
S_0x55ec3381fc70 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55ec3381f370;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x55ec33824ac0 .functor AND 1, L_0x55ec33824a30, L_0x55ec33825210, C4<1>, C4<1>;
L_0x55ec33824c00 .functor XOR 1, L_0x55ec33824a30, L_0x55ec33825210, C4<0>, C4<0>;
v0x55ec3381fee0_0 .net "A", 0 0, L_0x55ec33824a30; alias, 1 drivers
v0x55ec3381ffb0_0 .net "B", 0 0, L_0x55ec33825210; alias, 1 drivers
v0x55ec33820050_0 .net "Carry", 0 0, L_0x55ec33824ac0; alias, 1 drivers
v0x55ec33820120_0 .net "Sum", 0 0, L_0x55ec33824c00; alias, 1 drivers
S_0x55ec33820940 .scope module, "m1" "mux2" 4 25, 7 1 0, S_0x55ec3381f0f0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A0";
.port_info 1 /INPUT 1 "A1";
.port_info 2 /INPUT 1 "S";
.port_info 3 /OUTPUT 1 "Y";
L_0x55ec33824e60 .functor NOT 1, L_0x55ec338223e0, C4<0>, C4<0>, C4<0>;
L_0x55ec33824ef0 .functor AND 1, L_0x55ec33824c00, L_0x55ec338223e0, C4<1>, C4<1>;
L_0x55ec33824f80 .functor AND 1, L_0x55ec33824e60, L_0x55ec33825060, C4<1>, C4<1>;
L_0x55ec33824ff0 .functor OR 1, L_0x55ec33824ef0, L_0x55ec33824f80, C4<0>, C4<0>;
v0x55ec33820b90_0 .net "A0", 0 0, L_0x55ec33825060; alias, 1 drivers
v0x55ec33820c80_0 .net "A1", 0 0, L_0x55ec33824c00; alias, 1 drivers
v0x55ec33820d90_0 .net "S", 0 0, L_0x55ec338223e0; alias, 1 drivers
v0x55ec33820e80_0 .net "Y", 0 0, L_0x55ec33824ff0; alias, 1 drivers
v0x55ec33820f20_0 .net "and1", 0 0, L_0x55ec33824ef0; 1 drivers
v0x55ec33821010_0 .net "and2", 0 0, L_0x55ec33824f80; 1 drivers
v0x55ec338210d0_0 .net "notS", 0 0, L_0x55ec33824e60; 1 drivers
.scope S_0x55ec337fbbf0;
T_0 ;
%vpi_call 2 21 "$monitor", "Time=%0t | Dividend=%b | Divisor=%b | Quotient=%b | Remainder=%b", $time, v0x55ec33821ff0_0, v0x55ec338220d0_0, v0x55ec33822170_0, v0x55ec33822240_0 {0 0 0};
%vpi_call 2 23 "$dumpfile", "divider4.vcd" {0 0 0};
%vpi_call 2 24 "$dumpvars" {0 0 0};
%pushi/vec4 8, 0, 4;
%store/vec4 v0x55ec33821ff0_0, 0, 4;
%pushi/vec4 2, 0, 2;
%store/vec4 v0x55ec338220d0_0, 0, 2;
%delay 10, 0;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x55ec33821ff0_0, 0, 4;
%pushi/vec4 3, 0, 2;
%store/vec4 v0x55ec338220d0_0, 0, 2;
%delay 10, 0;
%pushi/vec4 7, 0, 4;
%store/vec4 v0x55ec33821ff0_0, 0, 4;
%pushi/vec4 2, 0, 2;
%store/vec4 v0x55ec338220d0_0, 0, 2;
%delay 10, 0;
%pushi/vec4 9, 0, 4;
%store/vec4 v0x55ec33821ff0_0, 0, 4;
%pushi/vec4 3, 0, 2;
%store/vec4 v0x55ec338220d0_0, 0, 2;
%delay 10, 0;
%pushi/vec4 6, 0, 4;
%store/vec4 v0x55ec33821ff0_0, 0, 4;
%pushi/vec4 1, 0, 2;
%store/vec4 v0x55ec338220d0_0, 0, 2;
%delay 10, 0;
%pushi/vec4 10, 0, 4;
%store/vec4 v0x55ec33821ff0_0, 0, 4;
%pushi/vec4 0, 0, 2;
%store/vec4 v0x55ec338220d0_0, 0, 2;
%delay 10, 0;
%vpi_call 2 57 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 8;
"N/A";
"<interactive>";
"divider4TB.v";
"divider4.v";
"PU.v";
"fulladder.v";
"halfadder.v";
"mux2.v";

58
project0.2/divider4.v
View File

@ -1,58 +0,0 @@
module divider4 (
input [3:0] Dividend, // 4-bit dividend
input [1:0] Divisor, // 2-bit divisor
output [3:0] Quotient, // 4-bit quotient
output [2:0] Remainder // 3-bit remainder
);
wire [3:0] Carry; // Carry wires between PUs
wire [3:0] Y; // Intermediate PU outputs
wire S0, S1; // Select signals based on division logic
// Calculate select signals based on carry outputs
assign S0 = Carry[3]; // First select signal
assign S1 = Carry[2]; // Second select signal
// Row 1
PU PU1 (
.A(Dividend[3]),
.B(Divisor[1]),
.Cin(1'b0), // Initial carry input is 0
.S(S0),
.Y(Y[3]),
.COut(Carry[3])
);
PU PU2 (
.A(Dividend[2]),
.B(Divisor[1]),
.Cin(Carry[3]),
.S(S0),
.Y(Y[2]),
.COut(Carry[2])
);
// Row 2
PU PU3 (
.A(Dividend[1]),
.B(Divisor[0]),
.Cin(Carry[2]),
.S(S1),
.Y(Y[1]),
.COut(Carry[1])
);
PU PU4 (
.A(Dividend[0]),
.B(Divisor[0]),
.Cin(Carry[1]),
.S(S1),
.Y(Y[0]),
.COut(Carry[0])
);
// Assign outputs
assign Quotient = Y; // Output of the PUs is the quotient
assign Remainder = Carry; // Final carry values are the remainder
endmodule

457
project0.2/divider4.vcd
View File

@ -1,457 +0,0 @@
$date
Fri Dec 27 21:47:45 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module divider4TB $end
$var wire 3 ! Remainder [2:0] $end
$var wire 4 " Quotient [3:0] $end
$var reg 4 # Dividend [3:0] $end
$var reg 2 $ Divisor [1:0] $end
$scope module uut $end
$var wire 4 % Dividend [3:0] $end
$var wire 2 & Divisor [1:0] $end
$var wire 4 ' Quotient [3:0] $end
$var wire 4 ( Y [3:0] $end
$var wire 1 ) S1 $end
$var wire 1 * S0 $end
$var wire 3 + Remainder [2:0] $end
$var wire 4 , Carry [3:0] $end
$scope module PU1 $end
$var wire 1 - A $end
$var wire 1 . B $end
$var wire 1 / Cin $end
$var wire 1 * S $end
$var wire 1 0 notB $end
$var wire 1 1 Y $end
$var wire 1 2 Sum $end
$var wire 1 3 COut $end
$scope module f1 $end
$var wire 1 - A $end
$var wire 1 0 B $end
$var wire 1 / Carry $end
$var wire 1 3 CarryO $end
$var wire 1 4 xor1 $end
$var wire 1 5 and2 $end
$var wire 1 6 and1 $end
$var wire 1 2 Sum $end
$scope module h1 $end
$var wire 1 - A $end
$var wire 1 0 B $end
$var wire 1 6 Carry $end
$var wire 1 4 Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 4 A $end
$var wire 1 / B $end
$var wire 1 5 Carry $end
$var wire 1 2 Sum $end
$upscope $end
$upscope $end
$scope module m1 $end
$var wire 1 - A0 $end
$var wire 1 2 A1 $end
$var wire 1 * S $end
$var wire 1 1 Y $end
$var wire 1 7 and1 $end
$var wire 1 8 and2 $end
$var wire 1 9 notS $end
$upscope $end
$upscope $end
$scope module PU2 $end
$var wire 1 : A $end
$var wire 1 ; B $end
$var wire 1 < Cin $end
$var wire 1 * S $end
$var wire 1 = notB $end
$var wire 1 > Y $end
$var wire 1 ? Sum $end
$var wire 1 @ COut $end
$scope module f1 $end
$var wire 1 : A $end
$var wire 1 = B $end
$var wire 1 < Carry $end
$var wire 1 @ CarryO $end
$var wire 1 A xor1 $end
$var wire 1 B and2 $end
$var wire 1 C and1 $end
$var wire 1 ? Sum $end
$scope module h1 $end
$var wire 1 : A $end
$var wire 1 = B $end
$var wire 1 C Carry $end
$var wire 1 A Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 A A $end
$var wire 1 < B $end
$var wire 1 B Carry $end
$var wire 1 ? Sum $end
$upscope $end
$upscope $end
$scope module m1 $end
$var wire 1 : A0 $end
$var wire 1 ? A1 $end
$var wire 1 * S $end
$var wire 1 > Y $end
$var wire 1 D and1 $end
$var wire 1 E and2 $end
$var wire 1 F notS $end
$upscope $end
$upscope $end
$scope module PU3 $end
$var wire 1 G A $end
$var wire 1 H B $end
$var wire 1 I Cin $end
$var wire 1 ) S $end
$var wire 1 J notB $end
$var wire 1 K Y $end
$var wire 1 L Sum $end
$var wire 1 M COut $end
$scope module f1 $end
$var wire 1 G A $end
$var wire 1 J B $end
$var wire 1 I Carry $end
$var wire 1 M CarryO $end
$var wire 1 N xor1 $end
$var wire 1 O and2 $end
$var wire 1 P and1 $end
$var wire 1 L Sum $end
$scope module h1 $end
$var wire 1 G A $end
$var wire 1 J B $end
$var wire 1 P Carry $end
$var wire 1 N Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 N A $end
$var wire 1 I B $end
$var wire 1 O Carry $end
$var wire 1 L Sum $end
$upscope $end
$upscope $end
$scope module m1 $end
$var wire 1 G A0 $end
$var wire 1 L A1 $end
$var wire 1 ) S $end
$var wire 1 K Y $end
$var wire 1 Q and1 $end
$var wire 1 R and2 $end
$var wire 1 S notS $end
$upscope $end
$upscope $end
$scope module PU4 $end
$var wire 1 T A $end
$var wire 1 U B $end
$var wire 1 V Cin $end
$var wire 1 ) S $end
$var wire 1 W notB $end
$var wire 1 X Y $end
$var wire 1 Y Sum $end
$var wire 1 Z COut $end
$scope module f1 $end
$var wire 1 T A $end
$var wire 1 W B $end
$var wire 1 V Carry $end
$var wire 1 Z CarryO $end
$var wire 1 [ xor1 $end
$var wire 1 \ and2 $end
$var wire 1 ] and1 $end
$var wire 1 Y Sum $end
$scope module h1 $end
$var wire 1 T A $end
$var wire 1 W B $end
$var wire 1 ] Carry $end
$var wire 1 [ Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 [ A $end
$var wire 1 V B $end
$var wire 1 \ Carry $end
$var wire 1 Y Sum $end
$upscope $end
$upscope $end
$scope module m1 $end
$var wire 1 T A0 $end
$var wire 1 Y A1 $end
$var wire 1 ) S $end
$var wire 1 X Y $end
$var wire 1 ^ and1 $end
$var wire 1 _ and2 $end
$var wire 1 ` notS $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1`
0_
0^
0]
0\
1[
0Z
1Y
0X
1W
0V
0U
0T
1S
0R
0Q
0P
0O
1N
0M
1L
0K
1J
0I
0H
0G
1F
0E
0D
0C
0B
0A
0@
0?
0>
0=
0<
1;
0:
19
18
07
06
05
14
03
12
11
00
0/
1.
1-
b0 ,
b0 +
0*
0)
b1000 (
b1000 '
b10 &
b1000 %
b10 $
b1000 #
b1000 "
b0 !
$end
#10
0\
0V
b0 !
b0 +
1?
1>
0M
1L
1K
b0 ,
0Z
1Y
b1111 "
b1111 '
b1111 (
1X
0J
0W
1A
1E
0P
1N
1R
0]
1[
1_
1H
1U
1:
1G
1T
b11 $
b11 &
b1111 #
b1111 %
#20
1V
b11 !
b11 +
1M
0L
b11 ,
1Z
1Y
1P
0N
1]
0[
02
b111 "
b111 '
b111 (
01
1J
1W
04
08
0H
0U
0-
b10 $
b10 &
b111 #
b111 %
#30
0Z
b0 !
b0 +
0V
0]
1[
12
11
0?
0>
b0 ,
0M
0L
b1001 "
b1001 '
b1001 (
0K
0J
0W
14
18
0A
0E
0P
0N
0R
1H
1U
1-
0:
0G
b11 $
b11 &
b1001 #
b1001 %
#40
1^
1V
1M
1O
0S
0Q
0`
b110 !
b110 +
1I
1)
b110 ,
1@
1C
12
01
0?
1>
0L
0K
1Y
b101 "
b101 '
b101 (
1X
10
1=
14
08
0A
1E
1N
0R
0[
0_
0.
0;
0-
1:
1G
0T
b1 $
b1 &
b110 #
b110 %
#50
1Q
1L
1K
0R
0X
1Z
1B
09
0F
0D
0S
0`
0^
0O
1\
0Y
1<
1*
b111 !
b111 +
1I
1)
1P
0N
1[
13
02
01
b1111 ,
1@
0?
b10 "
b10 '
b10 (
0>
1J
1W
16
04
08
0C
1A
0E
0H
0U
1-
0:
b0 $
b0 &
b1010 #
b1010 %
#60

60
project0.2/divider4TB.v
View File

@ -1,60 +0,0 @@
module divider4TB;
// Inputs
reg [3:0] Dividend;
reg [1:0] Divisor;
// Outputs
wire [3:0] Quotient;
wire [2:0] Remainder;
// Instantiate the Unit Under Test (UUT)
divider4 uut (
.Dividend(Dividend),
.Divisor(Divisor),
.Quotient(Quotient),
.Remainder(Remainder)
);
initial begin
// Monitor output changes
$monitor("Time=%0t | Dividend=%b | Divisor=%b | Quotient=%b | Remainder=%b",
$time, Dividend, Divisor, Quotient, Remainder);
$dumpfile("divider4.vcd");
$dumpvars;
// Test Case 1: 8 / 2
Dividend = 4'b1000; // 8 in binary
Divisor = 2'b10; // 2 in binary
#10;
// Test Case 2: 15 / 3
Dividend = 4'b1111; // 15 in binary
Divisor = 2'b11; // 3 in binary
#10;
// Test Case 3: 7 / 2
Dividend = 4'b0111; // 7 in binary
Divisor = 2'b10; // 2 in binary
#10;
// Test Case 4: 9 / 3
Dividend = 4'b1001; // 9 in binary
Divisor = 2'b11; // 3 in binary
#10;
// Test Case 5: 6 / 1
Dividend = 4'b0110; // 6 in binary
Divisor = 2'b01; // 1 in binary
#10;
// Test Case 6: Division by 0 (should be undefined behavior)
Dividend = 4'b1010; // 10 in binary
Divisor = 2'b00; // Division by zero
#10;
// End simulation
$finish;
end
endmodule

16
project0.2/mux2.v
View File

@ -1,16 +0,0 @@
module mux2 (
input A0, A1,
input S,
output Y
);
wire notS, and1, and2;
not n1 (notS, S);
and an1 (and1, A1, S);
and an2 (and2, notS, A0);
or o1 (Y, and1, and2);
endmodule

300
project0.2/selector
View File

@ -1,300 +0,0 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55b89815f210 .scope module, "selectorTB" "selectorTB" 2 1;
.timescale 0 0;
v0x55b898185a70_0 .var "A", 3 0;
v0x55b898185b50_0 .var "B", 3 0;
v0x55b898185c20_0 .var "Y", 7 0;
v0x55b898185cf0_0 .var "opCodeA", 2 0;
v0x55b898185de0_0 .net "s0", 7 0, L_0x55b89818e810; 1 drivers
v0x55b898185e80_0 .var "select", 3 0;
S_0x55b898152b60 .scope module, "uut" "selector" 2 8, 3 1 0, S_0x55b89815f210;
.timescale 0 0;
.port_info 0 /INPUT 4 "select";
.port_info 1 /INPUT 8 "Y";
.port_info 2 /INPUT 4 "A";
.port_info 3 /INPUT 4 "B";
.port_info 4 /INPUT 3 "opCodeA";
.port_info 5 /OUTPUT 8 "s0";
L_0x55b898185f50 .functor AND 1, L_0x55b898186050, L_0x55b898186190, C4<1>, C4<1>;
L_0x55b8981862d0 .functor AND 1, L_0x55b898186340, L_0x55b898186430, C4<1>, C4<1>;
L_0x55b898186550 .functor AND 1, L_0x55b8981865c0, L_0x55b8981866b0, C4<1>, C4<1>;
L_0x55b8981868d0 .functor AND 1, L_0x55b8981869c0, L_0x55b898186b00, C4<1>, C4<1>;
L_0x55b898186bf0 .functor AND 1, L_0x55b898186c60, L_0x55b898186db0, C4<1>, C4<1>;
L_0x55b898186ea0 .functor AND 1, L_0x55b898186f50, L_0x55b8981870b0, C4<1>, C4<1>;
L_0x55b8981871a0 .functor AND 1, L_0x55b898187210, L_0x55b898187380, C4<1>, C4<1>;
L_0x55b898187040 .functor AND 1, L_0x55b8981876e0, L_0x55b8981877d0, C4<1>, C4<1>;
L_0x55b898187960 .functor AND 1, L_0x55b8981879d0, L_0x55b898187ac0, C4<1>, C4<1>;
L_0x55b898187c60 .functor AND 1, L_0x55b8981878c0, L_0x55b898187d60, C4<1>, C4<1>;
L_0x55b898187f60 .functor AND 1, L_0x55b898187fd0, L_0x55b8981880c0, C4<1>, C4<1>;
L_0x55b898188280 .functor AND 1, L_0x55b898188390, L_0x55b898188480, C4<1>, C4<1>;
L_0x55b898188650 .functor AND 1, L_0x55b8981886f0, L_0x55b898188790, C4<1>, C4<1>;
L_0x55b898188970 .functor AND 1, L_0x55b898188a90, L_0x55b898188b80, C4<1>, C4<1>;
L_0x55b898188320 .functor AND 1, L_0x55b898188da0, L_0x55b898188e90, C4<1>, C4<1>;
L_0x55b8981893b0 .functor AND 1, L_0x55b898189500, L_0x55b898189710, C4<1>, C4<1>;
L_0x55b898189800 .functor AND 1, L_0x55b898189870, L_0x55b898189a90, C4<1>, C4<1>;
L_0x55b898189bd0 .functor AND 1, L_0x55b898189ce0, L_0x55b898189f10, C4<1>, C4<1>;
L_0x55b89818a290 .functor AND 1, L_0x55b89818a350, L_0x55b89818a440, C4<1>, C4<1>;
L_0x55b89818a690 .functor OR 1, L_0x55b898189c40, L_0x55b89818a800, C4<0>, C4<0>;
L_0x55b89818aab0 .functor OR 1, L_0x55b89818ab20, L_0x55b89818ac10, C4<0>, C4<0>;
L_0x55b89818ae80 .functor OR 1, L_0x55b89818afb0, L_0x55b89818b0a0, C4<0>, C4<0>;
L_0x55b89818b4a0 .functor OR 1, L_0x55b89818b560, L_0x55b89818b7f0, C4<0>, C4<0>;
L_0x55b89818b8e0 .functor OR 1, L_0x55b89818ba20, L_0x55b89818bd10, C4<0>, C4<0>;
L_0x55b89818be50 .functor OR 1, L_0x55b89818bec0, L_0x55b89818c170, C4<0>, C4<0>;
L_0x55b89818c260 .functor OR 1, L_0x55b89818c3b0, L_0x55b89818c700, C4<0>, C4<0>;
L_0x7f2e051b7018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x55b89818cb50 .functor OR 1, L_0x55b89818cc10, L_0x7f2e051b7018, C4<0>, C4<0>;
L_0x55b89818cd50 .functor OR 1, L_0x55b89818ceb0, L_0x55b89818d1e0, C4<0>, C4<0>;
L_0x55b89818d320 .functor OR 1, L_0x55b89818d390, L_0x55b89818d680, C4<0>, C4<0>;
L_0x55b89818d770 .functor OR 1, L_0x55b89818d8e0, L_0x55b89818dc70, C4<0>, C4<0>;
L_0x55b89818dda0 .functor OR 1, L_0x55b89818de10, L_0x55b89818e0d0, C4<0>, C4<0>;
v0x55b89815cd40_0 .net "A", 3 0, v0x55b898185a70_0; 1 drivers
v0x55b89815c0d0_0 .net "B", 3 0, v0x55b898185b50_0; 1 drivers
o0x7f2e0544e078 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
v0x55b89815b460_0 .net "Y", 7 0, o0x7f2e0544e078; 0 drivers
v0x55b898142380_0 .net *"_ivl_0", 0 0, L_0x55b898185f50; 1 drivers
v0x55b89817f760_0 .net *"_ivl_102", 0 0, L_0x55b898189870; 1 drivers
v0x55b89817f890_0 .net *"_ivl_104", 0 0, L_0x55b898189a90; 1 drivers
v0x55b89817f970_0 .net *"_ivl_105", 0 0, L_0x55b898189bd0; 1 drivers
v0x55b89817fa50_0 .net *"_ivl_108", 0 0, L_0x55b898189ce0; 1 drivers
v0x55b89817fb30_0 .net *"_ivl_11", 0 0, L_0x55b898186430; 1 drivers
v0x55b89817fc10_0 .net *"_ivl_110", 0 0, L_0x55b898189f10; 1 drivers
v0x55b89817fcf0_0 .net *"_ivl_111", 0 0, L_0x55b89818a290; 1 drivers
v0x55b89817fdd0_0 .net *"_ivl_115", 0 0, L_0x55b89818a350; 1 drivers
v0x55b89817feb0_0 .net *"_ivl_117", 0 0, L_0x55b89818a440; 1 drivers
v0x55b89817ff90_0 .net *"_ivl_118", 0 0, L_0x55b89818a690; 1 drivers
v0x55b898180070_0 .net *"_ivl_12", 0 0, L_0x55b898186550; 1 drivers
v0x55b898180150_0 .net *"_ivl_121", 0 0, L_0x55b898189c40; 1 drivers
v0x55b898180230_0 .net *"_ivl_123", 0 0, L_0x55b89818a800; 1 drivers
v0x55b898180310_0 .net *"_ivl_124", 0 0, L_0x55b89818aab0; 1 drivers
v0x55b8981803f0_0 .net *"_ivl_127", 0 0, L_0x55b89818ab20; 1 drivers
v0x55b8981804d0_0 .net *"_ivl_129", 0 0, L_0x55b89818ac10; 1 drivers
v0x55b8981805b0_0 .net *"_ivl_130", 0 0, L_0x55b89818ae80; 1 drivers
v0x55b898180690_0 .net *"_ivl_133", 0 0, L_0x55b89818afb0; 1 drivers
v0x55b898180770_0 .net *"_ivl_135", 0 0, L_0x55b89818b0a0; 1 drivers
v0x55b898180850_0 .net *"_ivl_136", 0 0, L_0x55b89818b4a0; 1 drivers
v0x55b898180930_0 .net *"_ivl_140", 0 0, L_0x55b89818b560; 1 drivers
v0x55b898180a10_0 .net *"_ivl_142", 0 0, L_0x55b89818b7f0; 1 drivers
v0x55b898180af0_0 .net *"_ivl_143", 0 0, L_0x55b89818b8e0; 1 drivers
v0x55b898180bd0_0 .net *"_ivl_146", 0 0, L_0x55b89818ba20; 1 drivers
v0x55b898180cb0_0 .net *"_ivl_148", 0 0, L_0x55b89818bd10; 1 drivers
v0x55b898180d90_0 .net *"_ivl_149", 0 0, L_0x55b89818be50; 1 drivers
v0x55b898180e70_0 .net *"_ivl_15", 0 0, L_0x55b8981865c0; 1 drivers
v0x55b898180f50_0 .net *"_ivl_152", 0 0, L_0x55b89818bec0; 1 drivers
v0x55b898181030_0 .net *"_ivl_154", 0 0, L_0x55b89818c170; 1 drivers
v0x55b898181320_0 .net *"_ivl_155", 0 0, L_0x55b89818c260; 1 drivers
v0x55b898181400_0 .net *"_ivl_158", 0 0, L_0x55b89818c3b0; 1 drivers
v0x55b8981814e0_0 .net *"_ivl_160", 0 0, L_0x55b89818c700; 1 drivers
v0x55b8981815c0_0 .net *"_ivl_161", 0 0, L_0x55b89818cb50; 1 drivers
v0x55b8981816a0_0 .net *"_ivl_165", 0 0, L_0x55b89818cc10; 1 drivers
v0x55b898181780_0 .net/2u *"_ivl_166", 0 0, L_0x7f2e051b7018; 1 drivers
v0x55b898181860_0 .net *"_ivl_168", 0 0, L_0x55b89818cd50; 1 drivers
v0x55b898181940_0 .net *"_ivl_17", 0 0, L_0x55b8981866b0; 1 drivers
v0x55b898181a20_0 .net *"_ivl_171", 0 0, L_0x55b89818ceb0; 1 drivers
v0x55b898181b00_0 .net *"_ivl_173", 0 0, L_0x55b89818d1e0; 1 drivers
v0x55b898181be0_0 .net *"_ivl_174", 0 0, L_0x55b89818d320; 1 drivers
v0x55b898181cc0_0 .net *"_ivl_177", 0 0, L_0x55b89818d390; 1 drivers
v0x55b898181da0_0 .net *"_ivl_179", 0 0, L_0x55b89818d680; 1 drivers
v0x55b898181e80_0 .net *"_ivl_18", 0 0, L_0x55b8981868d0; 1 drivers
v0x55b898181f60_0 .net *"_ivl_180", 0 0, L_0x55b89818d770; 1 drivers
v0x55b898182040_0 .net *"_ivl_183", 0 0, L_0x55b89818d8e0; 1 drivers
v0x55b898182120_0 .net *"_ivl_185", 0 0, L_0x55b89818dc70; 1 drivers
v0x55b898182200_0 .net *"_ivl_186", 0 0, L_0x55b89818dda0; 1 drivers
v0x55b8981822e0_0 .net *"_ivl_189", 0 0, L_0x55b89818de10; 1 drivers
v0x55b8981823c0_0 .net *"_ivl_191", 0 0, L_0x55b89818e0d0; 1 drivers
v0x55b8981824a0_0 .net *"_ivl_195", 0 0, L_0x55b89818e1c0; 1 drivers
v0x55b898182580_0 .net *"_ivl_199", 0 0, L_0x55b89818e490; 1 drivers
v0x55b898182660_0 .net *"_ivl_203", 0 0, L_0x55b89818e530; 1 drivers
v0x55b898182740_0 .net *"_ivl_208", 0 0, L_0x55b89818eb80; 1 drivers
v0x55b898182820_0 .net *"_ivl_22", 0 0, L_0x55b8981869c0; 1 drivers
v0x55b898182900_0 .net *"_ivl_24", 0 0, L_0x55b898186b00; 1 drivers
v0x55b8981829e0_0 .net *"_ivl_25", 0 0, L_0x55b898186bf0; 1 drivers
v0x55b898182ac0_0 .net *"_ivl_28", 0 0, L_0x55b898186c60; 1 drivers
v0x55b898182ba0_0 .net *"_ivl_3", 0 0, L_0x55b898186050; 1 drivers
v0x55b898182c80_0 .net *"_ivl_30", 0 0, L_0x55b898186db0; 1 drivers
v0x55b898182d60_0 .net *"_ivl_31", 0 0, L_0x55b898186ea0; 1 drivers
v0x55b898182e40_0 .net *"_ivl_34", 0 0, L_0x55b898186f50; 1 drivers
v0x55b898183330_0 .net *"_ivl_36", 0 0, L_0x55b8981870b0; 1 drivers
v0x55b898183410_0 .net *"_ivl_37", 0 0, L_0x55b8981871a0; 1 drivers
v0x55b8981834f0_0 .net *"_ivl_40", 0 0, L_0x55b898187210; 1 drivers
v0x55b8981835d0_0 .net *"_ivl_42", 0 0, L_0x55b898187380; 1 drivers
v0x55b8981836b0_0 .net *"_ivl_43", 0 0, L_0x55b898187040; 1 drivers
v0x55b898183790_0 .net *"_ivl_47", 0 0, L_0x55b8981876e0; 1 drivers
v0x55b898183870_0 .net *"_ivl_49", 0 0, L_0x55b8981877d0; 1 drivers
v0x55b898183950_0 .net *"_ivl_5", 0 0, L_0x55b898186190; 1 drivers
v0x55b898183a30_0 .net *"_ivl_50", 0 0, L_0x55b898187960; 1 drivers
v0x55b898183b10_0 .net *"_ivl_53", 0 0, L_0x55b8981879d0; 1 drivers
v0x55b898183bf0_0 .net *"_ivl_55", 0 0, L_0x55b898187ac0; 1 drivers
v0x55b898183cd0_0 .net *"_ivl_56", 0 0, L_0x55b898187c60; 1 drivers
v0x55b898183db0_0 .net *"_ivl_59", 0 0, L_0x55b8981878c0; 1 drivers
v0x55b898183e90_0 .net *"_ivl_6", 0 0, L_0x55b8981862d0; 1 drivers
v0x55b898183f70_0 .net *"_ivl_61", 0 0, L_0x55b898187d60; 1 drivers
v0x55b898184050_0 .net *"_ivl_62", 0 0, L_0x55b898187f60; 1 drivers
v0x55b898184130_0 .net *"_ivl_65", 0 0, L_0x55b898187fd0; 1 drivers
v0x55b898184210_0 .net *"_ivl_67", 0 0, L_0x55b8981880c0; 1 drivers
v0x55b8981842f0_0 .net *"_ivl_68", 0 0, L_0x55b898188280; 1 drivers
v0x55b8981843d0_0 .net *"_ivl_71", 0 0, L_0x55b898188390; 1 drivers
v0x55b8981844b0_0 .net *"_ivl_73", 0 0, L_0x55b898188480; 1 drivers
v0x55b898184590_0 .net *"_ivl_74", 0 0, L_0x55b898188650; 1 drivers
v0x55b898184670_0 .net *"_ivl_77", 0 0, L_0x55b8981886f0; 1 drivers
v0x55b898184750_0 .net *"_ivl_79", 0 0, L_0x55b898188790; 1 drivers
v0x55b898184830_0 .net *"_ivl_80", 0 0, L_0x55b898188970; 1 drivers
v0x55b898184910_0 .net *"_ivl_83", 0 0, L_0x55b898188a90; 1 drivers
v0x55b8981849f0_0 .net *"_ivl_85", 0 0, L_0x55b898188b80; 1 drivers
v0x55b898184ad0_0 .net *"_ivl_86", 0 0, L_0x55b898188320; 1 drivers
v0x55b898184bb0_0 .net *"_ivl_89", 0 0, L_0x55b898188da0; 1 drivers
v0x55b898184c90_0 .net *"_ivl_9", 0 0, L_0x55b898186340; 1 drivers
v0x55b898184d70_0 .net *"_ivl_91", 0 0, L_0x55b898188e90; 1 drivers
v0x55b898184e50_0 .net *"_ivl_92", 0 0, L_0x55b8981893b0; 1 drivers
v0x55b898184f30_0 .net *"_ivl_96", 0 0, L_0x55b898189500; 1 drivers
v0x55b898185010_0 .net *"_ivl_98", 0 0, L_0x55b898189710; 1 drivers
v0x55b8981850f0_0 .net *"_ivl_99", 0 0, L_0x55b898189800; 1 drivers
v0x55b8981851d0_0 .net "a0", 3 0, L_0x55b898186790; 1 drivers
v0x55b8981852b0_0 .net "b0", 3 0, L_0x55b898187470; 1 drivers
v0x55b898185390_0 .net "op0", 2 0, L_0x55b89818a000; 1 drivers
v0x55b898185470_0 .net "opCodeA", 2 0, v0x55b898185cf0_0; 1 drivers
v0x55b898185550_0 .net "s0", 7 0, L_0x55b89818e810; alias, 1 drivers
v0x55b898185630_0 .net "select", 3 0, v0x55b898185e80_0; 1 drivers
v0x55b898185710_0 .net "tempAB", 3 0, L_0x55b89818b360; 1 drivers
v0x55b8981857f0_0 .net "tempYO", 3 0, L_0x55b89818c830; 1 drivers
v0x55b8981858d0_0 .net "y0", 7 0, L_0x55b898189090; 1 drivers
L_0x55b898186050 .part v0x55b898185e80_0, 0, 1;
L_0x55b898186190 .part v0x55b898185a70_0, 0, 1;
L_0x55b898186340 .part v0x55b898185e80_0, 0, 1;
L_0x55b898186430 .part v0x55b898185a70_0, 1, 1;
L_0x55b8981865c0 .part v0x55b898185e80_0, 0, 1;
L_0x55b8981866b0 .part v0x55b898185a70_0, 2, 1;
L_0x55b898186790 .concat8 [ 1 1 1 1], L_0x55b898185f50, L_0x55b8981862d0, L_0x55b898186550, L_0x55b8981868d0;
L_0x55b8981869c0 .part v0x55b898185e80_0, 0, 1;
L_0x55b898186b00 .part v0x55b898185a70_0, 3, 1;
L_0x55b898186c60 .part v0x55b898185e80_0, 1, 1;
L_0x55b898186db0 .part v0x55b898185b50_0, 0, 1;
L_0x55b898186f50 .part v0x55b898185e80_0, 1, 1;
L_0x55b8981870b0 .part v0x55b898185b50_0, 1, 1;
L_0x55b898187210 .part v0x55b898185e80_0, 1, 1;
L_0x55b898187380 .part v0x55b898185b50_0, 2, 1;
L_0x55b898187470 .concat8 [ 1 1 1 1], L_0x55b898186bf0, L_0x55b898186ea0, L_0x55b8981871a0, L_0x55b898187040;
L_0x55b8981876e0 .part v0x55b898185e80_0, 1, 1;
L_0x55b8981877d0 .part v0x55b898185b50_0, 3, 1;
L_0x55b8981879d0 .part v0x55b898185e80_0, 2, 1;
L_0x55b898187ac0 .part o0x7f2e0544e078, 0, 1;
L_0x55b8981878c0 .part v0x55b898185e80_0, 2, 1;
L_0x55b898187d60 .part o0x7f2e0544e078, 1, 1;
L_0x55b898187fd0 .part v0x55b898185e80_0, 2, 1;
L_0x55b8981880c0 .part o0x7f2e0544e078, 2, 1;
L_0x55b898188390 .part v0x55b898185e80_0, 2, 1;
L_0x55b898188480 .part o0x7f2e0544e078, 3, 1;
L_0x55b8981886f0 .part v0x55b898185e80_0, 2, 1;
L_0x55b898188790 .part o0x7f2e0544e078, 4, 1;
L_0x55b898188a90 .part v0x55b898185e80_0, 2, 1;
L_0x55b898188b80 .part o0x7f2e0544e078, 5, 1;
L_0x55b898188da0 .part v0x55b898185e80_0, 2, 1;
L_0x55b898188e90 .part o0x7f2e0544e078, 6, 1;
LS_0x55b898189090_0_0 .concat8 [ 1 1 1 1], L_0x55b898187960, L_0x55b898187c60, L_0x55b898187f60, L_0x55b898188280;
LS_0x55b898189090_0_4 .concat8 [ 1 1 1 1], L_0x55b898188650, L_0x55b898188970, L_0x55b898188320, L_0x55b8981893b0;
L_0x55b898189090 .concat8 [ 4 4 0 0], LS_0x55b898189090_0_0, LS_0x55b898189090_0_4;
L_0x55b898189500 .part v0x55b898185e80_0, 2, 1;
L_0x55b898189710 .part o0x7f2e0544e078, 7, 1;
L_0x55b898189870 .part v0x55b898185e80_0, 3, 1;
L_0x55b898189a90 .part v0x55b898185cf0_0, 0, 1;
L_0x55b898189ce0 .part v0x55b898185e80_0, 3, 1;
L_0x55b898189f10 .part v0x55b898185cf0_0, 1, 1;
L_0x55b89818a000 .concat8 [ 1 1 1 0], L_0x55b898189800, L_0x55b898189bd0, L_0x55b89818a290;
L_0x55b89818a350 .part v0x55b898185e80_0, 3, 1;
L_0x55b89818a440 .part v0x55b898185cf0_0, 2, 1;
L_0x55b898189c40 .part L_0x55b898186790, 0, 1;
L_0x55b89818a800 .part L_0x55b898187470, 0, 1;
L_0x55b89818ab20 .part L_0x55b898186790, 1, 1;
L_0x55b89818ac10 .part L_0x55b898187470, 1, 1;
L_0x55b89818afb0 .part L_0x55b898186790, 2, 1;
L_0x55b89818b0a0 .part L_0x55b898187470, 2, 1;
L_0x55b89818b360 .concat8 [ 1 1 1 1], L_0x55b89818a690, L_0x55b89818aab0, L_0x55b89818ae80, L_0x55b89818b4a0;
L_0x55b89818b560 .part L_0x55b898186790, 3, 1;
L_0x55b89818b7f0 .part L_0x55b898187470, 3, 1;
L_0x55b89818ba20 .part L_0x55b898189090, 0, 1;
L_0x55b89818bd10 .part L_0x55b89818a000, 0, 1;
L_0x55b89818bec0 .part L_0x55b898189090, 1, 1;
L_0x55b89818c170 .part L_0x55b89818a000, 1, 1;
L_0x55b89818c3b0 .part L_0x55b898189090, 2, 1;
L_0x55b89818c700 .part L_0x55b89818a000, 2, 1;
L_0x55b89818c830 .concat8 [ 1 1 1 1], L_0x55b89818b8e0, L_0x55b89818be50, L_0x55b89818c260, L_0x55b89818cb50;
L_0x55b89818cc10 .part L_0x55b898189090, 3, 1;
L_0x55b89818ceb0 .part L_0x55b89818b360, 0, 1;
L_0x55b89818d1e0 .part L_0x55b89818c830, 0, 1;
L_0x55b89818d390 .part L_0x55b89818b360, 1, 1;
L_0x55b89818d680 .part L_0x55b89818c830, 1, 1;
L_0x55b89818d8e0 .part L_0x55b89818b360, 2, 1;
L_0x55b89818dc70 .part L_0x55b89818c830, 2, 1;
L_0x55b89818de10 .part L_0x55b89818b360, 3, 1;
L_0x55b89818e0d0 .part L_0x55b89818c830, 3, 1;
L_0x55b89818e1c0 .part L_0x55b898189090, 4, 1;
L_0x55b89818e490 .part L_0x55b898189090, 5, 1;
L_0x55b89818e530 .part L_0x55b898189090, 6, 1;
LS_0x55b89818e810_0_0 .concat8 [ 1 1 1 1], L_0x55b89818cd50, L_0x55b89818d320, L_0x55b89818d770, L_0x55b89818dda0;
LS_0x55b89818e810_0_4 .concat8 [ 1 1 1 1], L_0x55b89818e1c0, L_0x55b89818e490, L_0x55b89818e530, L_0x55b89818eb80;
L_0x55b89818e810 .concat8 [ 4 4 0 0], LS_0x55b89818e810_0_0, LS_0x55b89818e810_0_4;
L_0x55b89818eb80 .part L_0x55b898189090, 7, 1;
.scope S_0x55b89815f210;
T_0 ;
%vpi_call 2 17 "$dumpfile", "selector.vcd" {0 0 0};
%vpi_call 2 18 "$dumpvars" {0 0 0};
%pushi/vec4 1, 0, 4;
%store/vec4 v0x55b898185a70_0, 0, 4;
%pushi/vec4 2, 0, 4;
%store/vec4 v0x55b898185b50_0, 0, 4;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b898185cf0_0, 0, 3;
%pushi/vec4 240, 0, 8;
%store/vec4 v0x55b898185c20_0, 0, 8;
%pushi/vec4 2, 0, 4;
%store/vec4 v0x55b898185e80_0, 0, 4;
%delay 5, 0;
%pushi/vec4 1, 0, 4;
%store/vec4 v0x55b898185a70_0, 0, 4;
%pushi/vec4 2, 0, 4;
%store/vec4 v0x55b898185b50_0, 0, 4;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b898185cf0_0, 0, 3;
%pushi/vec4 240, 0, 8;
%store/vec4 v0x55b898185c20_0, 0, 8;
%pushi/vec4 1, 0, 4;
%store/vec4 v0x55b898185e80_0, 0, 4;
%delay 5, 0;
%pushi/vec4 1, 0, 4;
%store/vec4 v0x55b898185a70_0, 0, 4;
%pushi/vec4 2, 0, 4;
%store/vec4 v0x55b898185b50_0, 0, 4;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b898185cf0_0, 0, 3;
%pushi/vec4 112, 0, 8;
%store/vec4 v0x55b898185c20_0, 0, 8;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x55b898185e80_0, 0, 4;
%delay 5, 0;
%pushi/vec4 1, 0, 4;
%store/vec4 v0x55b898185a70_0, 0, 4;
%pushi/vec4 2, 0, 4;
%store/vec4 v0x55b898185b50_0, 0, 4;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b898185cf0_0, 0, 3;
%pushi/vec4 112, 0, 8;
%store/vec4 v0x55b898185c20_0, 0, 8;
%pushi/vec4 8, 0, 4;
%store/vec4 v0x55b898185e80_0, 0, 4;
%delay 5, 0;
%vpi_call 2 23 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"selectorTB.v";
"selector.v";

80
project0.2/selector.vcd
View File

@ -1,80 +0,0 @@
$date
Wed Jan 8 01:16:47 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module selectorTB $end
$var wire 8 ! s0 [7:0] $end
$var reg 4 " A [3:0] $end
$var reg 4 # B [3:0] $end
$var reg 8 $ Y [7:0] $end
$var reg 3 % opCodeA [2:0] $end
$var reg 4 & select [3:0] $end
$scope module uut $end
$var wire 4 ' A [3:0] $end
$var wire 4 ( B [3:0] $end
$var wire 8 ) Y [7:0] $end
$var wire 3 * opCodeA [2:0] $end
$var wire 4 + select [3:0] $end
$var wire 8 , y0 [7:0] $end
$var wire 4 - tempYO [3:0] $end
$var wire 4 . tempAB [3:0] $end
$var wire 8 / s0 [7:0] $end
$var wire 3 0 op0 [2:0] $end
$var wire 4 1 b0 [3:0] $end
$var wire 4 2 a0 [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 2
b10 1
b0 0
b10 /
b10 .
b0 -
b0 ,
b10 +
b111 *
bz )
b10 (
b1 '
b10 &
b111 %
b11110000 $
b10 #
b1 "
b10 !
$end
#5
b1 !
b1 /
b1 .
b1 2
b0 1
b1 &
b1 +
#10
b0 .
bx -
bx !
bx /
b0 2
bx ,
b100 &
b100 +
b1110000 $
#15
b111 -
b111 !
b111 /
b0 ,
b111 0
b1000 &
b1000 +
#20

2220
tangTest/bttn
View File

File diff suppressed because it is too large Load Diff

59
tangTest/bttn.cst
View File

@ -1,59 +0,0 @@
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Physical Constraints file
//Tool Version: V1.9.9.03 Education (64-bit)
//Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18
//Device Version: C
//Created Time: Sat 01 18 21:56:09 2025
IO_LOC "Y[11]" B12;
IO_PORT "Y[11]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[10]" B13;
IO_PORT "Y[10]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[9]" B14;
IO_PORT "Y[9]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[8]" D14;
IO_PORT "Y[8]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[7]" J14;
IO_PORT "Y[7]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[6]" M14;
IO_PORT "Y[6]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[5]" T12;
IO_PORT "Y[5]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[4]" T11;
IO_PORT "Y[4]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[3]" P9;
IO_PORT "Y[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[2]" P8;
IO_PORT "Y[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[1]" T7;
IO_PORT "Y[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[0]" P6;
IO_PORT "Y[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "select[1]" A14;
IO_PORT "select[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "select[0]" A15;
IO_PORT "select[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[2]" E8;
IO_PORT "opCodeA[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[1]" T4;
IO_PORT "opCodeA[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[0]" T5;
IO_PORT "opCodeA[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "B[3]" N8;
IO_PORT "B[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[2]" N7;
IO_PORT "B[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[1]" D11;
IO_PORT "B[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[0]" B11;
IO_PORT "B[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[3]" L9;
IO_PORT "A[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[2]" E15;
IO_PORT "A[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[1]" N6;
IO_PORT "A[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[0]" A11;
IO_PORT "A[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;

10
tangTest/compile.sh Normal file
View File

@ -0,0 +1,10 @@
#!/bin/bash
# Granting execute permissions to this script (one-time setup)
# chmod +x script_name.sh
# Using Icarus Verilog to compile Verilog files for simulation
iverilog -o top top.v topTB.v ALU.v selector.v BinaryToBCD.v arithmeticUnit.v logicUnit.v multiplier.v opCode.v addition.v dabble.v subtraction.v fulladder.v fullsubtraction.v halfadder.v halfsubtraction.v
# Running the simulation
vvp top

2220
tangTest/top Normal file
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File diff suppressed because it is too large Load Diff

2
tangTest/bttn.v → tangTest/top.v
View File

@ -1,4 +1,4 @@
module bttn (
module top (
input [3:0] A, B,
input [2:0] opCodeA,
input [1:0] select,

4
tangTest/bttn.vcd → tangTest/top.vcd
View File

@ -1,5 +1,5 @@
$date
Mon Jan 20 01:37:42 2025
Thu Jan 23 05:37:04 2025
$end
$version
Icarus Verilog
@ -7,7 +7,7 @@ $end
$timescale
1s
$end
$scope module bttnTB $end
$scope module topTB $end
$var wire 2 ! led [1:0] $end
$var wire 12 " Y [11:0] $end
$var reg 4 # A [3:0] $end

6
tangTest/bttnTB.v → tangTest/topTB.v
View File

@ -1,4 +1,4 @@
module bttnTB();
module topTB();
reg [3:0] A,B;
reg [2:0] opCodeA;
@ -6,7 +6,7 @@ reg [1:0] select;
wire [1:0] led;
wire [11:0] Y;
bttn uut (
top uut (
.A(A),
.B(B),
.opCodeA(opCodeA),
@ -16,7 +16,7 @@ bttn uut (
);
initial begin
$dumpfile("bttn.vcd");
$dumpfile("top.vcd");
$dumpvars;
A = 4'b1111; B = 4'b1111; opCodeA = 3'b000; select = 2'b01; #5;
A = 4'b0000; B = 4'b1111; opCodeA = 3'b001; select = 2'b01; #5;