kaltinsoy/verilog
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k0rrluna 8003e7f253 fpga
2025-01-23 05:25:40 +03:00
gowin
fpga
2025-01-23 05:25:40 +03:00
iverilog
subtraction & multiplier
2024-12-20 21:28:15 +03:00
project
opCode fixes
2024-12-15 04:25:43 +03:00
project0.2
selector&bcd
2025-01-15 22:21:50 +03:00
tangTest
bttnTB
2025-01-20 15:16:37 +03:00
Description
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2 MiB
Languages
Verilog 99.2%
Shell 0.5%
Coq 0.3%