selector&bcd
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project0.2/selector.v
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68
project0.2/selector.v
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@ -0,0 +1,68 @@
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module selector (
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input [3:0] select,
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input [7:0] Y,
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input [3:0] A, B,
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input [2:0] opCodeA,
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output [7:0] s0
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);
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wire [3:0] a0, b0, tempAB, tempYO;
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wire [7:0] y0;
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wire [2:0] op0;
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wire tempsO, temps;
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// Select signals for A
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and a00 (a0[0], select[0], A[0]);
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and a01 (a0[1], select[0], A[1]);
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and a02 (a0[2], select[0], A[2]);
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and a03 (a0[3], select[0], A[3]);
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// Select signals for B
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and b00 (b0[0], select[1], B[0]);
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and b01 (b0[1], select[1], B[1]);
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and b02 (b0[2], select[1], B[2]);
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and b03 (b0[3], select[1], B[3]);
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// Select signals for Y
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and y00 (y0[0], select[2], Y[0]);
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and y01 (y0[1], select[2], Y[1]);
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and y02 (y0[2], select[2], Y[2]);
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and y03 (y0[3], select[2], Y[3]);
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and y04 (y0[4], select[2], Y[4]);
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and y05 (y0[5], select[2], Y[5]);
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and y06 (y0[6], select[2], Y[6]);
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and y07 (y0[7], select[2], Y[7]);
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// Select signals for opCodeA
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and op00 (op0[0], select[3], opCodeA[0]);
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and op01 (op0[1], select[3], opCodeA[1]);
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and op02 (op0[2], select[3], opCodeA[2]);
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// Combine A and B
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or or1 (tempAB[0], a0[0], b0[0]);
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or or2 (tempAB[1], a0[1], b0[1]);
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or or3 (tempAB[2], a0[2], b0[2]);
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or or4 (tempAB[3], a0[3], b0[3]);
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// Combine Y and opCodeA
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or or5 (tempYO[0], y0[0], op0[0]);
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or or6 (tempYO[1], y0[1], op0[1]);
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or or7 (tempYO[2], y0[2], op0[2]);
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or or8 (tempYO[3], y0[3], 1'b0);
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// NOR for select logic
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nor s01 (tempsO, select[0], select[1]);
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nor s02 (temps, tempsO, select[3]);
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// Final s0 connections
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or or9 (s0[0], tempAB[0], tempYO[0]);
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or or10 (s0[1], tempAB[1], tempYO[1]);
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or or11 (s0[2], tempAB[2], tempYO[2]);
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or or12 (s0[3], tempAB[3], tempYO[3]);
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and and13 (s0[4], y0[4], temps);
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and and14 (s0[5], y0[5], temps);
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and and15 (s0[6], y0[6], temps);
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and and16 (s0[7], y0[7], temps);
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endmodule
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@ -2,7 +2,7 @@ module ALU (
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input [3:0] A, B,
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input CarryIN,
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input [2:0] opCodeA,
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output [7:0] Y,
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output [11:0] bcd,
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output CarryOUT, overflow
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);
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@ -73,7 +73,7 @@ or o36 (Y[5], 1'b0, wireM[5]);
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or o37 (Y[6], 1'b0, wireM[6]);
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or o38 (Y[7], 1'b0, wireM[7]);
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//BinaryToBCD btod1(.binary(Y), .bcd(bcd)); // WIRE Y BINARY!!!!
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BinaryToBCD btod1(.binary(Y), .bcd(bcd)); // WIRE Y BINARY!!!!
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endmodule
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@ -1,9 +0,0 @@
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module aluboard (
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input [3:0] select,
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input [7:0] Y,
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input [3:0] A, B,
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input [2:0] opCodeA,
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output [7:0] sO
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);
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ALU alu0 ()
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68
spartanTest/selector.v
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68
spartanTest/selector.v
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module selector (
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input [3:0] select,
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input [7:0] Y,
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input [3:0] A, B,
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input [2:0] opCodeA,
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output [7:0] s0
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);
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wire [3:0] a0, b0, tempAB, tempYO;
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wire [7:0] y0;
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wire [2:0] op0;
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wire tempsO, temps;
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// Select signals for A
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and a00 (a0[0], select[0], A[0]);
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and a01 (a0[1], select[0], A[1]);
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and a02 (a0[2], select[0], A[2]);
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and a03 (a0[3], select[0], A[3]);
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// Select signals for B
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and b00 (b0[0], select[1], B[0]);
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and b01 (b0[1], select[1], B[1]);
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and b02 (b0[2], select[1], B[2]);
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and b03 (b0[3], select[1], B[3]);
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// Select signals for Y
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and y00 (y0[0], select[2], Y[0]);
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and y01 (y0[1], select[2], Y[1]);
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and y02 (y0[2], select[2], Y[2]);
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and y03 (y0[3], select[2], Y[3]);
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and y04 (y0[4], select[2], Y[4]);
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and y05 (y0[5], select[2], Y[5]);
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and y06 (y0[6], select[2], Y[6]);
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and y07 (y0[7], select[2], Y[7]);
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// Select signals for opCodeA
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and op00 (op0[0], select[3], opCodeA[0]);
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and op01 (op0[1], select[3], opCodeA[1]);
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and op02 (op0[2], select[3], opCodeA[2]);
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// Combine A and B
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or or1 (tempAB[0], a0[0], b0[0]);
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or or2 (tempAB[1], a0[1], b0[1]);
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or or3 (tempAB[2], a0[2], b0[2]);
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or or4 (tempAB[3], a0[3], b0[3]);
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// Combine Y and opCodeA
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or or5 (tempYO[0], y0[0], op0[0]);
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or or6 (tempYO[1], y0[1], op0[1]);
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or or7 (tempYO[2], y0[2], op0[2]);
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or or8 (tempYO[3], y0[3], 1'b0);
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// NOR for select logic
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nor s01 (tempsO, select[0], select[1]);
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nor s02 (temps, tempsO, select[3]);
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// Final s0 connections
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or or9 (s0[0], tempAB[0], tempYO[0]);
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or or10 (s0[1], tempAB[1], tempYO[1]);
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or or11 (s0[2], tempAB[2], tempYO[2]);
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or or12 (s0[3], tempAB[3], tempYO[3]);
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and and13 (s0[4], y0[4], temps);
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and and14 (s0[5], y0[5], temps);
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and and15 (s0[6], y0[6], temps);
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and and16 (s0[7], y0[7], temps);
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endmodule
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