80 lines
2.5 KiB
Verilog
80 lines
2.5 KiB
Verilog
module ALU (
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input [3:0] A, B,
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input CarryIN,
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input [2:0] opCodeA,
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output [7:0] Y,
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output CarryOUT, overflow
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);
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// Supports: ADD[0], SUB[1], MULT[2], AND[4], OR[5], XOR[6]
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wire [7:0] opCode8;
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wire [3:0] add_Y, sub_Y;
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wire [3:0] resultA, resultO, resultX, lUOutput1;
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wire [3:0] aUtemp1, aUtemp2, lUOutput2;
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wire [3:0] wireY, wireLA;
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wire [7:0] opwireM, wireM, Y;
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opCode opCd (.A(opCodeA), .opCode(opCode8));
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arithmeticUnit aU(.opCode(opCode8[1:0]), .A(A), .B(B), .CarryIN(CarryIN), .add_Y(add_Y), .sub_Y(sub_Y), .CarryOUT(CarryOUT), .overflow(overflow));
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logicUnit lU (.opCode(opCode8[6:4]), .A(A), .B(B), .resultA(resultA), .resultO(resultO), .resultX(resultX));
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multiplier mU (.A(A), .B(B), .Y(opwireM));
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or o01 (lUOutput1[0], resultA[0], resultO[0]);
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or o02 (lUOutput1[1], resultA[1], resultO[1]);
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or o03 (lUOutput1[2], resultA[2], resultO[2]);
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or o04 (lUOutput1[3], resultA[3], resultO[3]);
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or o11 (lUOutput2[0], lUOutput1[0], resultX[0]);
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or o12 (lUOutput2[1], lUOutput1[1], resultX[1]);
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or o13 (lUOutput2[2], lUOutput1[2], resultX[2]);
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or o14 (lUOutput2[3], lUOutput1[3], resultX[3]);
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and a01 (aUtemp1[0], opCode8[0], add_Y[0]);
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and a02 (aUtemp1[1], opCode8[0], add_Y[1]);
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and a03 (aUtemp1[2], opCode8[0], add_Y[2]);
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and a04 (aUtemp1[3], opCode8[0], add_Y[3]);
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and a11 (aUtemp2[0], opCode8[1], sub_Y[0]);
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and a12 (aUtemp2[1], opCode8[1], sub_Y[1]);
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and a13 (aUtemp2[2], opCode8[1], sub_Y[2]);
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and a14 (aUtemp2[3], opCode8[1], sub_Y[3]);
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and a21 (wireM[0], opCode8[2], opwireM[0]);
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and a22 (wireM[1], opCode8[2], opwireM[1]);
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and a23 (wireM[2], opCode8[2], opwireM[2]);
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and a24 (wireM[3], opCode8[2], opwireM[3]);
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and a25 (wireM[4], opCode8[2], opwireM[4]);
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and a26 (wireM[5], opCode8[2], opwireM[5]);
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and a27 (wireM[6], opCode8[2], opwireM[6]);
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and a28 (wireM[7], opCode8[2], opwireM[7]);
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or o21 (wireY[0], aUtemp1[0], aUtemp2[0]);
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or o22 (wireY[1], aUtemp1[1], aUtemp2[1]);
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or o23 (wireY[2], aUtemp1[2], aUtemp2[2]);
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or o24 (wireY[3], aUtemp1[3], aUtemp2[3]);
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or o1 (wireLA[0], lUOutput2[0], wireY[0]);
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or o2 (wireLA[1], lUOutput2[1], wireY[1]);
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or o3 (wireLA[2], lUOutput2[2], wireY[2]);
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or o4 (wireLA[3], lUOutput2[3], wireY[3]);
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or o31 (Y[0], wireLA[0], wireM[0]);
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or o32 (Y[1], wireLA[1], wireM[1]);
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or o33 (Y[2], wireLA[2], wireM[2]);
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or o34 (Y[3], wireLA[3], wireM[3]);
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or o35 (Y[4], 1'b0, wireM[4]);
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or o36 (Y[5], 1'b0, wireM[5]);
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or o37 (Y[6], 1'b0, wireM[6]);
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or o38 (Y[7], 1'b0, wireM[7]);
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//BinaryToBCD btod1(.binary(Y), .bcd(bcd)); // WIRE Y BINARY!!!!
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endmodule
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