4-bit ALU
This commit is contained in:
parent
cd93206ad4
commit
cbf97501ea
13
project/addition.v
Normal file
13
project/addition.v
Normal file
@ -0,0 +1,13 @@
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module addition (
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input [3:0] A, B,
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output [4:0] Y
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);
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wire [3:0] Carry4;
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halfadder h1(.A(A[0]), .B(B[0]), .Sum(Y[0]), .Carry(Carry4[0]));
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fulladder f1(.A(A[1]), .B(B[1]), .Carry(Carry4[0]), .Sum(Y[1]), .CarryO(Carry4[1]));
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fulladder f2(.A(A[2]), .B(B[2]), .Carry(Carry4[1]), .Sum(Y[2]), .CarryO(Carry4[2]));
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fulladder f3(.A(A[3]), .B(B[3]), .Carry(Carry4[2]), .Sum(Y[3]), .CarryO(Y[4]));
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endmodule
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12
project/fulladder.v
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12
project/fulladder.v
Normal file
@ -0,0 +1,12 @@
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module fulladder (
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input A, B, Carry,
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output Sum, CarryO
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);
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wire xor1, and1, and2;
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halfadder h1(.A(A), .B(B), .Sum(xor1), .Carry(and1));
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halfadder h2 (.A(xor1), .B(Carry), .Sum(Sum), .Carry(and2));
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or o1 (CarryO, and1, and2);
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endmodule
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9
project/halfadder.v
Normal file
9
project/halfadder.v
Normal file
@ -0,0 +1,9 @@
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module halfadder (
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input A, B,
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output Sum, Carry
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);
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and a1 (Carry, A, B);
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xor xo1 (Sum, A, B);
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endmodule
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288
project/logicUnit
Normal file
288
project/logicUnit
Normal file
@ -0,0 +1,288 @@
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#! /usr/bin/vvp
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:ivl_version "11.0 (stable)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
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S_0x56004b80baa0 .scope module, "logicUnitTB" "logicUnitTB" 2 1;
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.timescale 0 0;
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v0x56004b83a150_0 .var "A", 3 0;
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v0x56004b83a230_0 .var "B", 3 0;
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v0x56004b83a300_0 .var "opCode", 2 0;
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v0x56004b83a400_0 .net "resultA", 3 0, L_0x56004b83d920; 1 drivers
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v0x56004b83a4d0_0 .net "resultO", 3 0, L_0x56004b83ec00; 1 drivers
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v0x56004b83a570_0 .net "resultX", 3 0, L_0x56004b83fe60; 1 drivers
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S_0x56004b80bc30 .scope module, "uut" "logicUnit" 2 7, 3 1 0, S_0x56004b80baa0;
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.timescale 0 0;
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.port_info 0 /INPUT 3 "opCode";
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.port_info 1 /INPUT 4 "A";
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.port_info 2 /INPUT 4 "B";
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.port_info 3 /OUTPUT 4 "resultA";
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.port_info 4 /OUTPUT 4 "resultO";
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.port_info 5 /OUTPUT 4 "resultX";
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L_0x56004b83a640 .functor AND 1, L_0x56004b83a740, L_0x56004b83a880, C4<1>, C4<1>;
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L_0x56004b83a9c0 .functor AND 1, L_0x56004b83aa30, L_0x56004b83ab20, C4<1>, C4<1>;
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L_0x56004b83ac40 .functor AND 1, L_0x56004b83acb0, L_0x56004b83ada0, C4<1>, C4<1>;
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L_0x56004b83afc0 .functor AND 1, L_0x56004b83b0b0, L_0x56004b83b1f0, C4<1>, C4<1>;
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L_0x56004b83b2e0 .functor OR 1, L_0x56004b83b350, L_0x56004b83b4a0, C4<0>, C4<0>;
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L_0x56004b83b540 .functor OR 1, L_0x56004b83b5f0, L_0x56004b83b750, C4<0>, C4<0>;
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L_0x56004b83b840 .functor OR 1, L_0x56004b83b8b0, L_0x56004b83ba20, C4<0>, C4<0>;
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L_0x56004b83b6e0 .functor OR 1, L_0x56004b83bdd0, L_0x56004b83bec0, C4<0>, C4<0>;
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L_0x56004b83c050 .functor XOR 1, L_0x56004b83c0c0, L_0x56004b83c1b0, C4<0>, C4<0>;
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L_0x56004b83c350 .functor XOR 1, L_0x56004b83bfb0, L_0x56004b83c450, C4<0>, C4<0>;
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L_0x56004b83c600 .functor XOR 1, L_0x56004b83c6a0, L_0x56004b83c790, C4<0>, C4<0>;
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L_0x56004b83cae0 .functor XOR 1, L_0x56004b83cc10, L_0x56004b83cde0, C4<0>, C4<0>;
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L_0x56004b83ced0 .functor AND 1, L_0x56004b83cf40, L_0x56004b83d170, C4<1>, C4<1>;
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L_0x56004b83d2b0 .functor AND 1, L_0x56004b83d3a0, L_0x56004b83d590, C4<1>, C4<1>;
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L_0x56004b83cba0 .functor AND 1, L_0x56004b83d680, L_0x56004b83d880, C4<1>, C4<1>;
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L_0x56004b83dbd0 .functor AND 1, L_0x56004b83dd20, L_0x56004b83de10, C4<1>, C4<1>;
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L_0x56004b83e030 .functor AND 1, L_0x56004b83e0a0, L_0x56004b83e190, C4<1>, C4<1>;
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L_0x56004b83e410 .functor AND 1, L_0x56004b83e520, L_0x56004b83e610, C4<1>, C4<1>;
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L_0x56004b83e850 .functor AND 1, L_0x56004b83e8c0, L_0x56004b83e9b0, C4<1>, C4<1>;
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L_0x56004b83ed90 .functor AND 1, L_0x56004b83e480, L_0x56004b83f0c0, C4<1>, C4<1>;
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L_0x56004b83f1b0 .functor AND 1, L_0x56004b83f220, L_0x56004b83f490, C4<1>, C4<1>;
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L_0x56004b83f5d0 .functor AND 1, L_0x56004b83f700, L_0x56004b83f980, C4<1>, C4<1>;
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L_0x56004b83fa70 .functor AND 1, L_0x56004b83fae0, L_0x56004b83fd70, C4<1>, C4<1>;
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L_0x56004b8401a0 .functor AND 1, L_0x56004b840330, L_0x56004b840420, C4<1>, C4<1>;
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v0x56004b7c9cf0_0 .net "A", 3 0, v0x56004b83a150_0; 1 drivers
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v0x56004b835650_0 .net "B", 3 0, v0x56004b83a230_0; 1 drivers
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v0x56004b835730_0 .net *"_ivl_0", 0 0, L_0x56004b83a640; 1 drivers
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v0x56004b8357f0_0 .net *"_ivl_100", 0 0, L_0x56004b83e030; 1 drivers
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v0x56004b8358d0_0 .net *"_ivl_103", 0 0, L_0x56004b83e0a0; 1 drivers
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v0x56004b835a00_0 .net *"_ivl_105", 0 0, L_0x56004b83e190; 1 drivers
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v0x56004b835ae0_0 .net *"_ivl_106", 0 0, L_0x56004b83e410; 1 drivers
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v0x56004b835bc0_0 .net *"_ivl_109", 0 0, L_0x56004b83e520; 1 drivers
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v0x56004b835ca0_0 .net *"_ivl_11", 0 0, L_0x56004b83ab20; 1 drivers
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v0x56004b835d80_0 .net *"_ivl_111", 0 0, L_0x56004b83e610; 1 drivers
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v0x56004b835e60_0 .net *"_ivl_112", 0 0, L_0x56004b83e850; 1 drivers
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v0x56004b835f40_0 .net *"_ivl_115", 0 0, L_0x56004b83e8c0; 1 drivers
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v0x56004b836020_0 .net *"_ivl_117", 0 0, L_0x56004b83e9b0; 1 drivers
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v0x56004b836100_0 .net *"_ivl_118", 0 0, L_0x56004b83ed90; 1 drivers
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v0x56004b8361e0_0 .net *"_ivl_12", 0 0, L_0x56004b83ac40; 1 drivers
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v0x56004b8362c0_0 .net *"_ivl_122", 0 0, L_0x56004b83e480; 1 drivers
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v0x56004b8363a0_0 .net *"_ivl_124", 0 0, L_0x56004b83f0c0; 1 drivers
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v0x56004b836480_0 .net *"_ivl_125", 0 0, L_0x56004b83f1b0; 1 drivers
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v0x56004b836560_0 .net *"_ivl_128", 0 0, L_0x56004b83f220; 1 drivers
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v0x56004b836640_0 .net *"_ivl_130", 0 0, L_0x56004b83f490; 1 drivers
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v0x56004b836720_0 .net *"_ivl_131", 0 0, L_0x56004b83f5d0; 1 drivers
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v0x56004b836800_0 .net *"_ivl_134", 0 0, L_0x56004b83f700; 1 drivers
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v0x56004b8368e0_0 .net *"_ivl_136", 0 0, L_0x56004b83f980; 1 drivers
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v0x56004b8369c0_0 .net *"_ivl_137", 0 0, L_0x56004b83fa70; 1 drivers
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v0x56004b836aa0_0 .net *"_ivl_140", 0 0, L_0x56004b83fae0; 1 drivers
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v0x56004b836b80_0 .net *"_ivl_142", 0 0, L_0x56004b83fd70; 1 drivers
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v0x56004b836c60_0 .net *"_ivl_143", 0 0, L_0x56004b8401a0; 1 drivers
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v0x56004b836d40_0 .net *"_ivl_147", 0 0, L_0x56004b840330; 1 drivers
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v0x56004b836e20_0 .net *"_ivl_149", 0 0, L_0x56004b840420; 1 drivers
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v0x56004b836f00_0 .net *"_ivl_15", 0 0, L_0x56004b83acb0; 1 drivers
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v0x56004b836fe0_0 .net *"_ivl_17", 0 0, L_0x56004b83ada0; 1 drivers
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v0x56004b8370c0_0 .net *"_ivl_18", 0 0, L_0x56004b83afc0; 1 drivers
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v0x56004b8371a0_0 .net *"_ivl_22", 0 0, L_0x56004b83b0b0; 1 drivers
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v0x56004b837280_0 .net *"_ivl_24", 0 0, L_0x56004b83b1f0; 1 drivers
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v0x56004b837360_0 .net *"_ivl_25", 0 0, L_0x56004b83b2e0; 1 drivers
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v0x56004b837440_0 .net *"_ivl_28", 0 0, L_0x56004b83b350; 1 drivers
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v0x56004b837520_0 .net *"_ivl_3", 0 0, L_0x56004b83a740; 1 drivers
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v0x56004b837600_0 .net *"_ivl_30", 0 0, L_0x56004b83b4a0; 1 drivers
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v0x56004b8376e0_0 .net *"_ivl_31", 0 0, L_0x56004b83b540; 1 drivers
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v0x56004b8377c0_0 .net *"_ivl_34", 0 0, L_0x56004b83b5f0; 1 drivers
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v0x56004b8378a0_0 .net *"_ivl_36", 0 0, L_0x56004b83b750; 1 drivers
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v0x56004b837980_0 .net *"_ivl_37", 0 0, L_0x56004b83b840; 1 drivers
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v0x56004b837a60_0 .net *"_ivl_40", 0 0, L_0x56004b83b8b0; 1 drivers
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v0x56004b837b40_0 .net *"_ivl_42", 0 0, L_0x56004b83ba20; 1 drivers
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v0x56004b837c20_0 .net *"_ivl_43", 0 0, L_0x56004b83b6e0; 1 drivers
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v0x56004b837d00_0 .net *"_ivl_47", 0 0, L_0x56004b83bdd0; 1 drivers
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v0x56004b837de0_0 .net *"_ivl_49", 0 0, L_0x56004b83bec0; 1 drivers
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v0x56004b837ec0_0 .net *"_ivl_5", 0 0, L_0x56004b83a880; 1 drivers
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v0x56004b837fa0_0 .net *"_ivl_50", 0 0, L_0x56004b83c050; 1 drivers
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v0x56004b838080_0 .net *"_ivl_53", 0 0, L_0x56004b83c0c0; 1 drivers
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v0x56004b838160_0 .net *"_ivl_55", 0 0, L_0x56004b83c1b0; 1 drivers
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v0x56004b838240_0 .net *"_ivl_56", 0 0, L_0x56004b83c350; 1 drivers
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v0x56004b838320_0 .net *"_ivl_59", 0 0, L_0x56004b83bfb0; 1 drivers
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v0x56004b838400_0 .net *"_ivl_6", 0 0, L_0x56004b83a9c0; 1 drivers
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v0x56004b8384e0_0 .net *"_ivl_61", 0 0, L_0x56004b83c450; 1 drivers
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v0x56004b8385c0_0 .net *"_ivl_62", 0 0, L_0x56004b83c600; 1 drivers
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v0x56004b8386a0_0 .net *"_ivl_65", 0 0, L_0x56004b83c6a0; 1 drivers
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v0x56004b838780_0 .net *"_ivl_67", 0 0, L_0x56004b83c790; 1 drivers
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v0x56004b838860_0 .net *"_ivl_68", 0 0, L_0x56004b83cae0; 1 drivers
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v0x56004b838940_0 .net *"_ivl_72", 0 0, L_0x56004b83cc10; 1 drivers
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v0x56004b838a20_0 .net *"_ivl_74", 0 0, L_0x56004b83cde0; 1 drivers
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v0x56004b838b00_0 .net *"_ivl_75", 0 0, L_0x56004b83ced0; 1 drivers
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v0x56004b838be0_0 .net *"_ivl_78", 0 0, L_0x56004b83cf40; 1 drivers
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v0x56004b838cc0_0 .net *"_ivl_80", 0 0, L_0x56004b83d170; 1 drivers
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v0x56004b838da0_0 .net *"_ivl_81", 0 0, L_0x56004b83d2b0; 1 drivers
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v0x56004b839290_0 .net *"_ivl_84", 0 0, L_0x56004b83d3a0; 1 drivers
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v0x56004b839370_0 .net *"_ivl_86", 0 0, L_0x56004b83d590; 1 drivers
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v0x56004b839450_0 .net *"_ivl_87", 0 0, L_0x56004b83cba0; 1 drivers
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v0x56004b839530_0 .net *"_ivl_9", 0 0, L_0x56004b83aa30; 1 drivers
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v0x56004b839610_0 .net *"_ivl_90", 0 0, L_0x56004b83d680; 1 drivers
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v0x56004b8396f0_0 .net *"_ivl_92", 0 0, L_0x56004b83d880; 1 drivers
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v0x56004b8397d0_0 .net *"_ivl_93", 0 0, L_0x56004b83dbd0; 1 drivers
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v0x56004b8398b0_0 .net *"_ivl_97", 0 0, L_0x56004b83dd20; 1 drivers
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v0x56004b839990_0 .net *"_ivl_99", 0 0, L_0x56004b83de10; 1 drivers
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v0x56004b839a70_0 .net "and1", 3 0, L_0x56004b83ae80; 1 drivers
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v0x56004b839b50_0 .net "opCode", 2 0, v0x56004b83a300_0; 1 drivers
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v0x56004b839c30_0 .net "or1", 3 0, L_0x56004b83bb10; 1 drivers
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v0x56004b839d10_0 .net "resultA", 3 0, L_0x56004b83d920; alias, 1 drivers
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v0x56004b839df0_0 .net "resultO", 3 0, L_0x56004b83ec00; alias, 1 drivers
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v0x56004b839ed0_0 .net "resultX", 3 0, L_0x56004b83fe60; alias, 1 drivers
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v0x56004b839fb0_0 .net "xor1", 3 0, L_0x56004b83c950; 1 drivers
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L_0x56004b83a740 .part v0x56004b83a150_0, 0, 1;
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L_0x56004b83a880 .part v0x56004b83a230_0, 0, 1;
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L_0x56004b83aa30 .part v0x56004b83a150_0, 1, 1;
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L_0x56004b83ab20 .part v0x56004b83a230_0, 1, 1;
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L_0x56004b83acb0 .part v0x56004b83a150_0, 2, 1;
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L_0x56004b83ada0 .part v0x56004b83a230_0, 2, 1;
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L_0x56004b83ae80 .concat8 [ 1 1 1 1], L_0x56004b83a640, L_0x56004b83a9c0, L_0x56004b83ac40, L_0x56004b83afc0;
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L_0x56004b83b0b0 .part v0x56004b83a150_0, 3, 1;
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L_0x56004b83b1f0 .part v0x56004b83a230_0, 3, 1;
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L_0x56004b83b350 .part v0x56004b83a150_0, 0, 1;
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L_0x56004b83b4a0 .part v0x56004b83a230_0, 0, 1;
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L_0x56004b83b5f0 .part v0x56004b83a150_0, 1, 1;
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L_0x56004b83b750 .part v0x56004b83a230_0, 1, 1;
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L_0x56004b83b8b0 .part v0x56004b83a150_0, 2, 1;
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L_0x56004b83ba20 .part v0x56004b83a230_0, 2, 1;
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L_0x56004b83bb10 .concat8 [ 1 1 1 1], L_0x56004b83b2e0, L_0x56004b83b540, L_0x56004b83b840, L_0x56004b83b6e0;
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L_0x56004b83bdd0 .part v0x56004b83a150_0, 3, 1;
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L_0x56004b83bec0 .part v0x56004b83a230_0, 3, 1;
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L_0x56004b83c0c0 .part v0x56004b83a150_0, 0, 1;
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L_0x56004b83c1b0 .part v0x56004b83a230_0, 0, 1;
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L_0x56004b83bfb0 .part v0x56004b83a150_0, 1, 1;
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L_0x56004b83c450 .part v0x56004b83a230_0, 1, 1;
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L_0x56004b83c6a0 .part v0x56004b83a150_0, 2, 1;
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L_0x56004b83c790 .part v0x56004b83a230_0, 2, 1;
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L_0x56004b83c950 .concat8 [ 1 1 1 1], L_0x56004b83c050, L_0x56004b83c350, L_0x56004b83c600, L_0x56004b83cae0;
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L_0x56004b83cc10 .part v0x56004b83a150_0, 3, 1;
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L_0x56004b83cde0 .part v0x56004b83a230_0, 3, 1;
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L_0x56004b83cf40 .part v0x56004b83a300_0, 0, 1;
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L_0x56004b83d170 .part L_0x56004b83ae80, 0, 1;
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L_0x56004b83d3a0 .part v0x56004b83a300_0, 0, 1;
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L_0x56004b83d590 .part L_0x56004b83ae80, 1, 1;
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L_0x56004b83d680 .part v0x56004b83a300_0, 0, 1;
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L_0x56004b83d880 .part L_0x56004b83ae80, 2, 1;
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L_0x56004b83d920 .concat8 [ 1 1 1 1], L_0x56004b83ced0, L_0x56004b83d2b0, L_0x56004b83cba0, L_0x56004b83dbd0;
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L_0x56004b83dd20 .part v0x56004b83a300_0, 0, 1;
|
||||
L_0x56004b83de10 .part L_0x56004b83ae80, 3, 1;
|
||||
L_0x56004b83e0a0 .part v0x56004b83a300_0, 1, 1;
|
||||
L_0x56004b83e190 .part L_0x56004b83bb10, 0, 1;
|
||||
L_0x56004b83e520 .part v0x56004b83a300_0, 1, 1;
|
||||
L_0x56004b83e610 .part L_0x56004b83bb10, 1, 1;
|
||||
L_0x56004b83e8c0 .part v0x56004b83a300_0, 1, 1;
|
||||
L_0x56004b83e9b0 .part L_0x56004b83bb10, 2, 1;
|
||||
L_0x56004b83ec00 .concat8 [ 1 1 1 1], L_0x56004b83e030, L_0x56004b83e410, L_0x56004b83e850, L_0x56004b83ed90;
|
||||
L_0x56004b83e480 .part v0x56004b83a300_0, 1, 1;
|
||||
L_0x56004b83f0c0 .part L_0x56004b83bb10, 3, 1;
|
||||
L_0x56004b83f220 .part v0x56004b83a300_0, 2, 1;
|
||||
L_0x56004b83f490 .part L_0x56004b83c950, 0, 1;
|
||||
L_0x56004b83f700 .part v0x56004b83a300_0, 2, 1;
|
||||
L_0x56004b83f980 .part L_0x56004b83c950, 1, 1;
|
||||
L_0x56004b83fae0 .part v0x56004b83a300_0, 2, 1;
|
||||
L_0x56004b83fd70 .part L_0x56004b83c950, 2, 1;
|
||||
L_0x56004b83fe60 .concat8 [ 1 1 1 1], L_0x56004b83f1b0, L_0x56004b83f5d0, L_0x56004b83fa70, L_0x56004b8401a0;
|
||||
L_0x56004b840330 .part v0x56004b83a300_0, 2, 1;
|
||||
L_0x56004b840420 .part L_0x56004b83c950, 3, 1;
|
||||
.scope S_0x56004b80baa0;
|
||||
T_0 ;
|
||||
%vpi_call 2 17 "$dumpfile", "logicUnit.vcd" {0 0 0};
|
||||
%vpi_call 2 18 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 1, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 1, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 3, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 1, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 9, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 9, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 15, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 15, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 1, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 5, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 9, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 5, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 1, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 15, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 5, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 5, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 5, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 15, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 15, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%vpi_call 2 34 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"logicUnitTB.v";
|
||||
"logicUnit.v";
|
||||
39
project/logicUnit.v
Normal file
39
project/logicUnit.v
Normal file
@ -0,0 +1,39 @@
|
||||
module logicUnit (
|
||||
input [2:0] opCode,
|
||||
input [3:0] A, B,
|
||||
output [3:0] resultA, resultO, resultX
|
||||
);
|
||||
|
||||
wire [3:0] and1, or1, xor1;
|
||||
|
||||
and a01 (and1[0], A[0], B[0]);
|
||||
and a02 (and1[1], A[1], B[1]);
|
||||
and a03 (and1[2], A[2], B[2]);
|
||||
and a04 (and1[3], A[3], B[3]);
|
||||
|
||||
or o01 (or1[0], A[0], B[0]);
|
||||
or o02 (or1[1], A[1], B[1]);
|
||||
or o03 (or1[2], A[2], B[2]);
|
||||
or o04 (or1[3], A[3], B[3]);
|
||||
|
||||
xor xor01 (xor1[0], A[0], B[0]);
|
||||
xor xor02 (xor1[1], A[1], B[1]);
|
||||
xor xor03 (xor1[2], A[2], B[2]);
|
||||
xor xor04 (xor1[3], A[3], B[3]);
|
||||
|
||||
and a_o1 (resultA[0], opCode[0], and1[0]);
|
||||
and a_o2 (resultA[1], opCode[0], and1[1]);
|
||||
and a_o3 (resultA[2], opCode[0], and1[2]);
|
||||
and a_o4 (resultA[3], opCode[0], and1[3]);
|
||||
|
||||
and o_o1 (resultO[0], opCode[1], or1[0]);
|
||||
and o_o2 (resultO[1], opCode[1], or1[1]);
|
||||
and o_o3 (resultO[2], opCode[1], or1[2]);
|
||||
and o_o4 (resultO[3], opCode[1], or1[3]);
|
||||
|
||||
and x_o1 (resultX[0], opCode[2], xor1[0]);
|
||||
and x_o2 (resultX[1], opCode[2], xor1[1]);
|
||||
and x_o3 (resultX[2], opCode[2], xor1[2]);
|
||||
and x_o4 (resultX[3], opCode[2], xor1[3]);
|
||||
|
||||
endmodule
|
||||
150
project/logicUnit.vcd
Normal file
150
project/logicUnit.vcd
Normal file
@ -0,0 +1,150 @@
|
||||
$date
|
||||
Sat Dec 14 03:32:40 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module logicUnitTB $end
|
||||
$var wire 4 ! resultX [3:0] $end
|
||||
$var wire 4 " resultO [3:0] $end
|
||||
$var wire 4 # resultA [3:0] $end
|
||||
$var reg 4 $ A [3:0] $end
|
||||
$var reg 4 % B [3:0] $end
|
||||
$var reg 3 & opCode [2:0] $end
|
||||
$scope module uut $end
|
||||
$var wire 4 ' A [3:0] $end
|
||||
$var wire 4 ( B [3:0] $end
|
||||
$var wire 3 ) opCode [2:0] $end
|
||||
$var wire 4 * xor1 [3:0] $end
|
||||
$var wire 4 + resultX [3:0] $end
|
||||
$var wire 4 , resultO [3:0] $end
|
||||
$var wire 4 - resultA [3:0] $end
|
||||
$var wire 4 . or1 [3:0] $end
|
||||
$var wire 4 / and1 [3:0] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
b1 /
|
||||
b1 .
|
||||
b1 -
|
||||
b0 ,
|
||||
b0 +
|
||||
b0 *
|
||||
b1 )
|
||||
b1 (
|
||||
b1 '
|
||||
b1 &
|
||||
b1 %
|
||||
b1 $
|
||||
b1 #
|
||||
b0 "
|
||||
b0 !
|
||||
$end
|
||||
#2
|
||||
b11 .
|
||||
b10 *
|
||||
b11 $
|
||||
b11 '
|
||||
#4
|
||||
b1001 #
|
||||
b1001 -
|
||||
b1001 /
|
||||
b1001 .
|
||||
b0 *
|
||||
b1001 %
|
||||
b1001 (
|
||||
b1001 $
|
||||
b1001 '
|
||||
#6
|
||||
b1111 #
|
||||
b1111 -
|
||||
b1111 /
|
||||
b1111 .
|
||||
b1111 %
|
||||
b1111 (
|
||||
b1111 $
|
||||
b1111 '
|
||||
#8
|
||||
b0 #
|
||||
b0 -
|
||||
b0 /
|
||||
b0 .
|
||||
b0 %
|
||||
b0 (
|
||||
b0 $
|
||||
b0 '
|
||||
#10
|
||||
b101 "
|
||||
b101 ,
|
||||
b100 *
|
||||
b1 /
|
||||
b101 .
|
||||
b101 %
|
||||
b101 (
|
||||
b1 $
|
||||
b1 '
|
||||
b10 &
|
||||
b10 )
|
||||
#12
|
||||
b1101 "
|
||||
b1101 ,
|
||||
b1101 .
|
||||
b1100 *
|
||||
b1001 $
|
||||
b1001 '
|
||||
#14
|
||||
b1111 "
|
||||
b1111 ,
|
||||
b1111 .
|
||||
b1110 *
|
||||
b1111 %
|
||||
b1111 (
|
||||
b1 $
|
||||
b1 '
|
||||
#16
|
||||
b101 "
|
||||
b101 ,
|
||||
b101 .
|
||||
b0 /
|
||||
b101 *
|
||||
b101 %
|
||||
b101 (
|
||||
b0 $
|
||||
b0 '
|
||||
#18
|
||||
b0 "
|
||||
b0 ,
|
||||
b101 !
|
||||
b101 +
|
||||
b100 &
|
||||
b100 )
|
||||
#20
|
||||
b0 !
|
||||
b0 +
|
||||
b0 .
|
||||
b0 *
|
||||
b0 %
|
||||
b0 (
|
||||
#22
|
||||
b101 !
|
||||
b101 +
|
||||
b101 .
|
||||
b101 *
|
||||
b101 %
|
||||
b101 (
|
||||
#24
|
||||
b0 !
|
||||
b0 +
|
||||
b1111 /
|
||||
b1111 .
|
||||
b0 *
|
||||
b1111 %
|
||||
b1111 (
|
||||
b1111 $
|
||||
b1111 '
|
||||
#26
|
||||
37
project/logicUnitTB.v
Normal file
37
project/logicUnitTB.v
Normal file
@ -0,0 +1,37 @@
|
||||
module logicUnitTB ();
|
||||
|
||||
reg [2:0] opCode;
|
||||
reg [3:0] A, B;
|
||||
wire [3:0] resultA, resultO, resultX;
|
||||
|
||||
logicUnit uut (
|
||||
.opCode(opCode),
|
||||
.A(A),
|
||||
.B(B),
|
||||
.resultA(resultA),
|
||||
.resultO(resultO),
|
||||
.resultX(resultX)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("logicUnit.vcd");
|
||||
$dumpvars;
|
||||
opCode = 3'b001; A = 4'b0001; B = 4'b0001; #2;
|
||||
opCode = 3'b001; A = 4'b0011; B = 4'b0001; #2;
|
||||
opCode = 3'b001; A = 4'b1001; B = 4'b1001; #2;
|
||||
opCode = 3'b001; A = 4'b1111; B = 4'b1111; #2;
|
||||
opCode = 3'b001; A = 4'b0000; B = 4'b0000; #2;
|
||||
|
||||
opCode = 3'b010; A = 4'b0001; B = 4'b0101; #2;
|
||||
opCode = 3'b010; A = 4'b1001; B = 4'b0101; #2;
|
||||
opCode = 3'b010; A = 4'b0001; B = 4'b1111; #2;
|
||||
opCode = 3'b010; A = 4'b0000; B = 4'b0101; #2;
|
||||
|
||||
opCode = 3'b100; A = 4'b0000; B = 4'b0101; #2;
|
||||
opCode = 3'b100; A = 4'b0000; B = 4'b0000; #2;
|
||||
opCode = 3'b100; A = 4'b0000; B = 4'b0101; #2;
|
||||
opCode = 3'b100; A = 4'b1111; B = 4'b1111; #2;
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
127
project/opCode
Normal file
127
project/opCode
Normal file
@ -0,0 +1,127 @@
|
||||
#! /usr/bin/vvp
|
||||
:ivl_version "11.0 (stable)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||
S_0x5595e35f5aa0 .scope module, "opCodeTB" "opCodeTB" 2 1;
|
||||
.timescale 0 0;
|
||||
v0x5595e360d6f0_0 .var "A", 0 0;
|
||||
v0x5595e360d7b0_0 .var "B", 0 0;
|
||||
v0x5595e360d880_0 .var "C", 0 0;
|
||||
v0x5595e360d980_0 .net "opCode", 7 0, L_0x5595e360e5f0; 1 drivers
|
||||
S_0x5595e35f5c30 .scope module, "uut" "opCode" 2 6, 3 1 0, S_0x5595e35f5aa0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "C";
|
||||
.port_info 3 /OUTPUT 8 "opCode";
|
||||
L_0x5595e360da50 .functor NOT 1, v0x5595e360d6f0_0, C4<0>, C4<0>, C4<0>;
|
||||
L_0x5595e360daf0 .functor NOT 1, v0x5595e360d7b0_0, C4<0>, C4<0>, C4<0>;
|
||||
L_0x5595e360dbb0 .functor NOT 1, v0x5595e360d880_0, C4<0>, C4<0>, C4<0>;
|
||||
L_0x5595e360dc70 .functor AND 1, v0x5595e360d6f0_0, v0x5595e360d7b0_0, C4<1>, C4<1>;
|
||||
L_0x5595e360dd10 .functor AND 1, L_0x5595e360da50, v0x5595e360d7b0_0, C4<1>, C4<1>;
|
||||
L_0x5595e360de00 .functor AND 1, v0x5595e360d6f0_0, L_0x5595e360daf0, C4<1>, C4<1>;
|
||||
L_0x5595e360deb0 .functor AND 1, L_0x5595e360da50, L_0x5595e360daf0, C4<1>, C4<1>;
|
||||
L_0x5595e360df20 .functor AND 1, L_0x5595e360deb0, L_0x5595e360dbb0, C4<1>, C4<1>;
|
||||
L_0x5595e360e030 .functor AND 1, L_0x5595e360deb0, v0x5595e360d880_0, C4<1>, C4<1>;
|
||||
L_0x5595e360e0a0 .functor AND 1, L_0x5595e360dd10, L_0x5595e360dbb0, C4<1>, C4<1>;
|
||||
L_0x5595e360e1c0 .functor AND 1, L_0x5595e360dd10, v0x5595e360d880_0, C4<1>, C4<1>;
|
||||
L_0x5595e360e2c0 .functor AND 1, L_0x5595e360de00, L_0x5595e360dbb0, C4<1>, C4<1>;
|
||||
L_0x5595e360e460 .functor AND 1, L_0x5595e360de00, v0x5595e360d880_0, C4<1>, C4<1>;
|
||||
L_0x5595e360e4d0 .functor AND 1, L_0x5595e360dc70, L_0x5595e360dbb0, C4<1>, C4<1>;
|
||||
L_0x5595e360e3f0 .functor AND 1, L_0x5595e360dc70, v0x5595e360d880_0, C4<1>, C4<1>;
|
||||
v0x5595e35e0f30_0 .net "A", 0 0, v0x5595e360d6f0_0; 1 drivers
|
||||
v0x5595e35e0ae0_0 .net "B", 0 0, v0x5595e360d7b0_0; 1 drivers
|
||||
v0x5595e35e0690_0 .net "C", 0 0, v0x5595e360d880_0; 1 drivers
|
||||
v0x5595e35e0240_0 .net *"_ivl_0", 0 0, L_0x5595e360df20; 1 drivers
|
||||
v0x5595e35dfdf0_0 .net *"_ivl_10", 0 0, L_0x5595e360e460; 1 drivers
|
||||
v0x5595e35df970_0 .net *"_ivl_12", 0 0, L_0x5595e360e4d0; 1 drivers
|
||||
v0x5595e360cbf0_0 .net *"_ivl_14", 0 0, L_0x5595e360e3f0; 1 drivers
|
||||
v0x5595e360ccd0_0 .net *"_ivl_2", 0 0, L_0x5595e360e030; 1 drivers
|
||||
v0x5595e360cdb0_0 .net *"_ivl_4", 0 0, L_0x5595e360e0a0; 1 drivers
|
||||
v0x5595e360ce90_0 .net *"_ivl_6", 0 0, L_0x5595e360e1c0; 1 drivers
|
||||
v0x5595e360cf70_0 .net *"_ivl_8", 0 0, L_0x5595e360e2c0; 1 drivers
|
||||
v0x5595e360d050_0 .net "and1", 0 0, L_0x5595e360dc70; 1 drivers
|
||||
v0x5595e360d110_0 .net "and2", 0 0, L_0x5595e360dd10; 1 drivers
|
||||
v0x5595e360d1d0_0 .net "and3", 0 0, L_0x5595e360de00; 1 drivers
|
||||
v0x5595e360d290_0 .net "and4", 0 0, L_0x5595e360deb0; 1 drivers
|
||||
v0x5595e360d350_0 .net "notA", 0 0, L_0x5595e360da50; 1 drivers
|
||||
v0x5595e360d410_0 .net "notB", 0 0, L_0x5595e360daf0; 1 drivers
|
||||
v0x5595e360d4d0_0 .net "notC", 0 0, L_0x5595e360dbb0; 1 drivers
|
||||
v0x5595e360d590_0 .net "opCode", 7 0, L_0x5595e360e5f0; alias, 1 drivers
|
||||
LS_0x5595e360e5f0_0_0 .concat8 [ 1 1 1 1], L_0x5595e360df20, L_0x5595e360e030, L_0x5595e360e0a0, L_0x5595e360e1c0;
|
||||
LS_0x5595e360e5f0_0_4 .concat8 [ 1 1 1 1], L_0x5595e360e2c0, L_0x5595e360e460, L_0x5595e360e4d0, L_0x5595e360e3f0;
|
||||
L_0x5595e360e5f0 .concat8 [ 4 4 0 0], LS_0x5595e360e5f0_0_0, LS_0x5595e360e5f0_0_4;
|
||||
.scope S_0x5595e35f5aa0;
|
||||
T_0 ;
|
||||
%vpi_call 2 14 "$dumpfile", "opCode.vcd" {0 0 0};
|
||||
%vpi_call 2 15 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d6f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d7b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d880_0, 0, 1;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d6f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d7b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d880_0, 0, 1;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d6f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d7b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d880_0, 0, 1;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d6f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d7b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d880_0, 0, 1;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d6f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d7b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d880_0, 0, 1;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d6f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d7b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d880_0, 0, 1;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d6f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d7b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d880_0, 0, 1;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d6f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d7b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d880_0, 0, 1;
|
||||
%delay 3, 0;
|
||||
%vpi_call 2 24 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"opCodeTB.v";
|
||||
"opCode.v";
|
||||
25
project/opCode.v
Normal file
25
project/opCode.v
Normal file
@ -0,0 +1,25 @@
|
||||
module opCode (
|
||||
input A, B, C,
|
||||
output [7:0] opCode
|
||||
);
|
||||
wire and1, and2, and3, and4, notA, notB, notC;
|
||||
|
||||
not n1(notA, A);
|
||||
not n2(notB, B);
|
||||
not n3(notC, C);
|
||||
|
||||
and a01(and1, A, B);
|
||||
and a02(and2, notA, B);
|
||||
and a03(and3, A, notB);
|
||||
and a04(and4, notA, notB);
|
||||
|
||||
and a1(opCode[0], and4, notC);
|
||||
and a2(opCode[1], and4, C);
|
||||
and a3(opCode[2], and2, notC);
|
||||
and a4(opCode[3], and2, C);
|
||||
and a5(opCode[4], and3, notC);
|
||||
and a6(opCode[5], and3, C);
|
||||
and a7(opCode[6], and1, notC);
|
||||
and a8(opCode[7], and1, C);
|
||||
|
||||
endmodule
|
||||
94
project/opCode.vcd
Normal file
94
project/opCode.vcd
Normal file
@ -0,0 +1,94 @@
|
||||
$date
|
||||
Fri Dec 13 20:24:01 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module opCodeTB $end
|
||||
$var wire 8 ! opCode [7:0] $end
|
||||
$var reg 1 " A $end
|
||||
$var reg 1 # B $end
|
||||
$var reg 1 $ C $end
|
||||
$scope module uut $end
|
||||
$var wire 1 " A $end
|
||||
$var wire 1 # B $end
|
||||
$var wire 1 $ C $end
|
||||
$var wire 1 % and1 $end
|
||||
$var wire 1 & and2 $end
|
||||
$var wire 1 ' and3 $end
|
||||
$var wire 1 ( and4 $end
|
||||
$var wire 1 ) notA $end
|
||||
$var wire 1 * notB $end
|
||||
$var wire 1 + notC $end
|
||||
$var wire 8 , opCode [7:0] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
b1 ,
|
||||
1+
|
||||
1*
|
||||
1)
|
||||
1(
|
||||
0'
|
||||
0&
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
0"
|
||||
b1 !
|
||||
$end
|
||||
#3
|
||||
0+
|
||||
b10 !
|
||||
b10 ,
|
||||
1$
|
||||
#6
|
||||
0(
|
||||
1+
|
||||
b100 !
|
||||
b100 ,
|
||||
0*
|
||||
1&
|
||||
0$
|
||||
1#
|
||||
#9
|
||||
0+
|
||||
b1000 !
|
||||
b1000 ,
|
||||
1$
|
||||
#12
|
||||
1'
|
||||
1+
|
||||
b10000 !
|
||||
b10000 ,
|
||||
1*
|
||||
0&
|
||||
0)
|
||||
0$
|
||||
0#
|
||||
1"
|
||||
#15
|
||||
0+
|
||||
b100000 !
|
||||
b100000 ,
|
||||
1$
|
||||
#18
|
||||
0'
|
||||
1+
|
||||
b1000000 !
|
||||
b1000000 ,
|
||||
0*
|
||||
1%
|
||||
0$
|
||||
1#
|
||||
#21
|
||||
0+
|
||||
b10000000 !
|
||||
b10000000 ,
|
||||
1$
|
||||
#24
|
||||
27
project/opCodeTB.v
Normal file
27
project/opCodeTB.v
Normal file
@ -0,0 +1,27 @@
|
||||
module opCodeTB();
|
||||
|
||||
reg A, B, C;
|
||||
wire [7:0] opCode;
|
||||
|
||||
opCode uut (
|
||||
.A(A),
|
||||
.B(B),
|
||||
.C(C),
|
||||
.opCode(opCode)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("opCode.vcd");
|
||||
$dumpvars;
|
||||
A = 1'b0; B = 1'b0; C = 1'b0; #3;
|
||||
A = 1'b0; B = 1'b0; C = 1'b1; #3;
|
||||
A = 1'b0; B = 1'b1; C = 1'b0; #3;
|
||||
A = 1'b0; B = 1'b1; C = 1'b1; #3;
|
||||
A = 1'b1; B = 1'b0; C = 1'b0; #3;
|
||||
A = 1'b1; B = 1'b0; C = 1'b1; #3;
|
||||
A = 1'b1; B = 1'b1; C = 1'b0; #3;
|
||||
A = 1'b1; B = 1'b1; C = 1'b1; #3;
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
25
project/overflowDetect.v
Normal file
25
project/overflowDetect.v
Normal file
@ -0,0 +1,25 @@
|
||||
module overflowDetect (
|
||||
input [1:0] opCode,
|
||||
input [3:0] A, B,
|
||||
input [4:0] Y,
|
||||
output overflowDetect
|
||||
);
|
||||
|
||||
wire opC,AandSum;
|
||||
wire sign1, sign2, sign3, sign4;
|
||||
wire detect1, detect2;
|
||||
|
||||
or o1 (opC, opCode[0], opCode[1]);
|
||||
xor xo1 (AandSum, Y[4], A[3]);
|
||||
|
||||
and a1 (sign1, A[3], B[3]);
|
||||
or o2 (sign2, opCode[0], sign1);
|
||||
|
||||
xor a2 (sign3, A[3], B[3]);
|
||||
or o3 (sign4, opCode[1], sign3);
|
||||
|
||||
or o4 (detect1, sign2, sign4);
|
||||
and a3 (detect2, AandSum, opC);
|
||||
and a4 (overflowDetect, detect1, detect2);
|
||||
|
||||
endmodule
|
||||
476
project/subtraction
Normal file
476
project/subtraction
Normal file
@ -0,0 +1,476 @@
|
||||
#! /usr/bin/vvp
|
||||
:ivl_version "11.0 (stable)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||
S_0x563bc4582ac0 .scope module, "subtractionTB" "subtractionTB" 2 1;
|
||||
.timescale 0 0;
|
||||
L_0x563bc45b7070 .functor BUFZ 1, L_0x563bc45b61f0, C4<0>, C4<0>, C4<0>;
|
||||
v0x563bc45b09d0_0 .var "A", 3 0;
|
||||
v0x563bc45b0a90_0 .var "B", 3 0;
|
||||
v0x563bc45b0b50_0 .net "Y", 4 0, L_0x563bc45b6c20; 1 drivers
|
||||
v0x563bc45b0c20_0 .net "overflow", 0 0, L_0x563bc45b7070; 1 drivers
|
||||
S_0x563bc4581020 .scope module, "uut" "subtraction" 2 7, 3 1 0, S_0x563bc4582ac0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 4 "A";
|
||||
.port_info 1 /INPUT 4 "B";
|
||||
.port_info 2 /OUTPUT 5 "Y";
|
||||
L_0x563bc45b0cc0 .functor NOT 1, L_0x563bc45b0db0, C4<0>, C4<0>, C4<0>;
|
||||
L_0x563bc45b0ea0 .functor NOT 1, L_0x563bc45b0f60, C4<0>, C4<0>, C4<0>;
|
||||
L_0x563bc45b1050 .functor NOT 1, L_0x563bc45b10f0, C4<0>, C4<0>, C4<0>;
|
||||
L_0x563bc45b13a0 .functor NOT 1, L_0x563bc45b1490, C4<0>, C4<0>, C4<0>;
|
||||
L_0x7fe52ee620a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
L_0x563bc45b6350 .functor OR 1, L_0x563bc45b63c0, L_0x7fe52ee620a8, C4<0>, C4<0>;
|
||||
L_0x7fe52ee620f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
L_0x563bc45b6500 .functor OR 1, L_0x563bc45b6570, L_0x7fe52ee620f0, C4<0>, C4<0>;
|
||||
L_0x7fe52ee62138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
L_0x563bc45b6700 .functor OR 1, L_0x563bc45b6770, L_0x7fe52ee62138, C4<0>, C4<0>;
|
||||
L_0x7fe52ee62180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
L_0x563bc45b6900 .functor OR 1, L_0x563bc45b69c0, L_0x7fe52ee62180, C4<0>, C4<0>;
|
||||
L_0x563bc45b6e50 .functor XOR 1, L_0x563bc45b61f0, L_0x563bc45b6f10, C4<0>, C4<0>;
|
||||
v0x563bc45af080_0 .net "A", 3 0, v0x563bc45b09d0_0; 1 drivers
|
||||
v0x563bc45af160_0 .net "B", 3 0, v0x563bc45b0a90_0; 1 drivers
|
||||
v0x563bc45af220_0 .net "Y", 4 0, L_0x563bc45b6c20; alias, 1 drivers
|
||||
v0x563bc45af2c0_0 .net "Y1", 4 0, L_0x563bc45b4e80; 1 drivers
|
||||
v0x563bc45af3d0_0 .net *"_ivl_0", 0 0, L_0x563bc45b0cc0; 1 drivers
|
||||
v0x563bc45af500_0 .net *"_ivl_11", 0 0, L_0x563bc45b10f0; 1 drivers
|
||||
v0x563bc45af5e0_0 .net *"_ivl_12", 0 0, L_0x563bc45b13a0; 1 drivers
|
||||
v0x563bc45af6c0_0 .net *"_ivl_16", 0 0, L_0x563bc45b1490; 1 drivers
|
||||
v0x563bc45af7a0_0 .net *"_ivl_23", 0 0, L_0x563bc45b6350; 1 drivers
|
||||
v0x563bc45af880_0 .net *"_ivl_26", 0 0, L_0x563bc45b63c0; 1 drivers
|
||||
v0x563bc45af960_0 .net/2u *"_ivl_27", 0 0, L_0x7fe52ee620a8; 1 drivers
|
||||
v0x563bc45afa40_0 .net *"_ivl_29", 0 0, L_0x563bc45b6500; 1 drivers
|
||||
v0x563bc45afb20_0 .net *"_ivl_3", 0 0, L_0x563bc45b0db0; 1 drivers
|
||||
v0x563bc45afc00_0 .net *"_ivl_32", 0 0, L_0x563bc45b6570; 1 drivers
|
||||
v0x563bc45afce0_0 .net/2u *"_ivl_33", 0 0, L_0x7fe52ee620f0; 1 drivers
|
||||
v0x563bc45afdc0_0 .net *"_ivl_35", 0 0, L_0x563bc45b6700; 1 drivers
|
||||
v0x563bc45afea0_0 .net *"_ivl_38", 0 0, L_0x563bc45b6770; 1 drivers
|
||||
v0x563bc45aff80_0 .net/2u *"_ivl_39", 0 0, L_0x7fe52ee62138; 1 drivers
|
||||
v0x563bc45b0060_0 .net *"_ivl_4", 0 0, L_0x563bc45b0ea0; 1 drivers
|
||||
v0x563bc45b0140_0 .net *"_ivl_41", 0 0, L_0x563bc45b6900; 1 drivers
|
||||
v0x563bc45b0220_0 .net *"_ivl_44", 0 0, L_0x563bc45b69c0; 1 drivers
|
||||
v0x563bc45b0300_0 .net/2u *"_ivl_45", 0 0, L_0x7fe52ee62180; 1 drivers
|
||||
v0x563bc45b03e0_0 .net *"_ivl_48", 0 0, L_0x563bc45b6e50; 1 drivers
|
||||
v0x563bc45b04c0_0 .net *"_ivl_52", 0 0, L_0x563bc45b6f10; 1 drivers
|
||||
v0x563bc45b05a0_0 .net *"_ivl_7", 0 0, L_0x563bc45b0f60; 1 drivers
|
||||
v0x563bc45b0680_0 .net *"_ivl_8", 0 0, L_0x563bc45b1050; 1 drivers
|
||||
v0x563bc45b0760_0 .net "notB", 4 0, L_0x563bc45b3210; 1 drivers
|
||||
v0x563bc45b0820_0 .net "overflow", 0 0, L_0x563bc45b61f0; 1 drivers
|
||||
v0x563bc45b08c0_0 .net "xB", 3 0, L_0x563bc45b1190; 1 drivers
|
||||
L_0x563bc45b0db0 .part v0x563bc45b0a90_0, 0, 1;
|
||||
L_0x563bc45b0f60 .part v0x563bc45b0a90_0, 1, 1;
|
||||
L_0x563bc45b10f0 .part v0x563bc45b0a90_0, 2, 1;
|
||||
L_0x563bc45b1190 .concat8 [ 1 1 1 1], L_0x563bc45b0cc0, L_0x563bc45b0ea0, L_0x563bc45b1050, L_0x563bc45b13a0;
|
||||
L_0x563bc45b1490 .part v0x563bc45b0a90_0, 3, 1;
|
||||
L_0x563bc45b4f90 .part L_0x563bc45b3210, 0, 4;
|
||||
L_0x563bc45b63c0 .part L_0x563bc45b4e80, 0, 1;
|
||||
L_0x563bc45b6570 .part L_0x563bc45b4e80, 1, 1;
|
||||
L_0x563bc45b6770 .part L_0x563bc45b4e80, 2, 1;
|
||||
L_0x563bc45b69c0 .part L_0x563bc45b4e80, 3, 1;
|
||||
LS_0x563bc45b6c20_0_0 .concat8 [ 1 1 1 1], L_0x563bc45b6350, L_0x563bc45b6500, L_0x563bc45b6700, L_0x563bc45b6900;
|
||||
LS_0x563bc45b6c20_0_4 .concat8 [ 1 0 0 0], L_0x563bc45b6e50;
|
||||
L_0x563bc45b6c20 .concat8 [ 4 1 0 0], LS_0x563bc45b6c20_0_0, LS_0x563bc45b6c20_0_4;
|
||||
L_0x563bc45b6f10 .part L_0x563bc45b4e80, 4, 1;
|
||||
S_0x563bc457f580 .scope module, "a1" "addition" 3 16, 4 1 0, S_0x563bc4581020;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 4 "A";
|
||||
.port_info 1 /INPUT 4 "B";
|
||||
.port_info 2 /OUTPUT 5 "Y";
|
||||
v0x563bc45a8870_0 .net "A", 3 0, L_0x563bc45b1190; alias, 1 drivers
|
||||
L_0x7fe52ee62018 .functor BUFT 1, C4<0001>, C4<0>, C4<0>, C4<0>;
|
||||
v0x563bc45a8970_0 .net "B", 3 0, L_0x7fe52ee62018; 1 drivers
|
||||
v0x563bc45a8a50_0 .net "Carry4", 3 0, L_0x563bc45b70e0; 1 drivers
|
||||
v0x563bc45a8b10_0 .net "Y", 4 0, L_0x563bc45b3210; alias, 1 drivers
|
||||
o0x7fe52eeabe28 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
; Elide local net with no drivers, v0x563bc45a8bf0_0 name=_ivl_41
|
||||
L_0x563bc45b1700 .part L_0x563bc45b1190, 0, 1;
|
||||
L_0x563bc45b17a0 .part L_0x7fe52ee62018, 0, 1;
|
||||
L_0x563bc45b1c90 .part L_0x563bc45b1190, 1, 1;
|
||||
L_0x563bc45b1e50 .part L_0x7fe52ee62018, 1, 1;
|
||||
L_0x563bc45b1fb0 .part L_0x563bc45b70e0, 0, 1;
|
||||
L_0x563bc45b24e0 .part L_0x563bc45b1190, 2, 1;
|
||||
L_0x563bc45b2650 .part L_0x7fe52ee62018, 2, 1;
|
||||
L_0x563bc45b2780 .part L_0x563bc45b70e0, 1, 1;
|
||||
L_0x563bc45b2d90 .part L_0x563bc45b1190, 3, 1;
|
||||
L_0x563bc45b2ec0 .part L_0x7fe52ee62018, 3, 1;
|
||||
L_0x563bc45b30e0 .part L_0x563bc45b70e0, 2, 1;
|
||||
LS_0x563bc45b3210_0_0 .concat8 [ 1 1 1 1], L_0x563bc45b15f0, L_0x563bc45b1b60, L_0x563bc45b2370, L_0x563bc45b2c20;
|
||||
LS_0x563bc45b3210_0_4 .concat8 [ 1 0 0 0], L_0x563bc45b2d00;
|
||||
L_0x563bc45b3210 .concat8 [ 4 1 0 0], LS_0x563bc45b3210_0_0, LS_0x563bc45b3210_0_4;
|
||||
L_0x563bc45b70e0 .concat [ 1 1 1 1], L_0x563bc45b1580, L_0x563bc45b1c20, L_0x563bc45b2450, o0x7fe52eeabe28;
|
||||
S_0x563bc457c980 .scope module, "f1" "fulladder" 4 9, 5 1 0, S_0x563bc457f580;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x563bc45b1c20 .functor OR 1, L_0x563bc45b1840, L_0x563bc45b1a10, C4<0>, C4<0>;
|
||||
v0x563bc45a53b0_0 .net "A", 0 0, L_0x563bc45b1c90; 1 drivers
|
||||
v0x563bc45a5470_0 .net "B", 0 0, L_0x563bc45b1e50; 1 drivers
|
||||
v0x563bc45a5540_0 .net "Carry", 0 0, L_0x563bc45b1fb0; 1 drivers
|
||||
v0x563bc45a5640_0 .net "CarryO", 0 0, L_0x563bc45b1c20; 1 drivers
|
||||
v0x563bc45a56e0_0 .net "Sum", 0 0, L_0x563bc45b1b60; 1 drivers
|
||||
v0x563bc45a57d0_0 .net "and1", 0 0, L_0x563bc45b1840; 1 drivers
|
||||
v0x563bc45a58a0_0 .net "and2", 0 0, L_0x563bc45b1a10; 1 drivers
|
||||
v0x563bc45a5970_0 .net "xor1", 0 0, L_0x563bc45b19a0; 1 drivers
|
||||
S_0x563bc457aee0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x563bc457c980;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x563bc45b1840 .functor AND 1, L_0x563bc45b1c90, L_0x563bc45b1e50, C4<1>, C4<1>;
|
||||
L_0x563bc45b19a0 .functor XOR 1, L_0x563bc45b1c90, L_0x563bc45b1e50, C4<0>, C4<0>;
|
||||
v0x563bc4581650_0 .net "A", 0 0, L_0x563bc45b1c90; alias, 1 drivers
|
||||
v0x563bc457fbb0_0 .net "B", 0 0, L_0x563bc45b1e50; alias, 1 drivers
|
||||
v0x563bc457e130_0 .net "Carry", 0 0, L_0x563bc45b1840; alias, 1 drivers
|
||||
v0x563bc4579a70_0 .net "Sum", 0 0, L_0x563bc45b19a0; alias, 1 drivers
|
||||
S_0x563bc45a5010 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x563bc457c980;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x563bc45b1a10 .functor AND 1, L_0x563bc45b19a0, L_0x563bc45b1fb0, C4<1>, C4<1>;
|
||||
L_0x563bc45b1b60 .functor XOR 1, L_0x563bc45b19a0, L_0x563bc45b1fb0, C4<0>, C4<0>;
|
||||
v0x563bc4577ff0_0 .net "A", 0 0, L_0x563bc45b19a0; alias, 1 drivers
|
||||
v0x563bc45877b0_0 .net "B", 0 0, L_0x563bc45b1fb0; alias, 1 drivers
|
||||
v0x563bc4586c70_0 .net "Carry", 0 0, L_0x563bc45b1a10; alias, 1 drivers
|
||||
v0x563bc45a5240_0 .net "Sum", 0 0, L_0x563bc45b1b60; alias, 1 drivers
|
||||
S_0x563bc45a5a60 .scope module, "f2" "fulladder" 4 10, 5 1 0, S_0x563bc457f580;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x563bc45b2450 .functor OR 1, L_0x563bc45b20e0, L_0x563bc45b21e0, C4<0>, C4<0>;
|
||||
v0x563bc45a67e0_0 .net "A", 0 0, L_0x563bc45b24e0; 1 drivers
|
||||
v0x563bc45a68a0_0 .net "B", 0 0, L_0x563bc45b2650; 1 drivers
|
||||
v0x563bc45a6970_0 .net "Carry", 0 0, L_0x563bc45b2780; 1 drivers
|
||||
v0x563bc45a6a70_0 .net "CarryO", 0 0, L_0x563bc45b2450; 1 drivers
|
||||
v0x563bc45a6b10_0 .net "Sum", 0 0, L_0x563bc45b2370; 1 drivers
|
||||
v0x563bc45a6c00_0 .net "and1", 0 0, L_0x563bc45b20e0; 1 drivers
|
||||
v0x563bc45a6cd0_0 .net "and2", 0 0, L_0x563bc45b21e0; 1 drivers
|
||||
v0x563bc45a6da0_0 .net "xor1", 0 0, L_0x563bc45b2150; 1 drivers
|
||||
S_0x563bc45a5c40 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x563bc45a5a60;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x563bc45b20e0 .functor AND 1, L_0x563bc45b24e0, L_0x563bc45b2650, C4<1>, C4<1>;
|
||||
L_0x563bc45b2150 .functor XOR 1, L_0x563bc45b24e0, L_0x563bc45b2650, C4<0>, C4<0>;
|
||||
v0x563bc45a5e50_0 .net "A", 0 0, L_0x563bc45b24e0; alias, 1 drivers
|
||||
v0x563bc45a5f30_0 .net "B", 0 0, L_0x563bc45b2650; alias, 1 drivers
|
||||
v0x563bc45a5ff0_0 .net "Carry", 0 0, L_0x563bc45b20e0; alias, 1 drivers
|
||||
v0x563bc45a60c0_0 .net "Sum", 0 0, L_0x563bc45b2150; alias, 1 drivers
|
||||
S_0x563bc45a6230 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x563bc45a5a60;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x563bc45b21e0 .functor AND 1, L_0x563bc45b2150, L_0x563bc45b2780, C4<1>, C4<1>;
|
||||
L_0x563bc45b2370 .functor XOR 1, L_0x563bc45b2150, L_0x563bc45b2780, C4<0>, C4<0>;
|
||||
v0x563bc45a6430_0 .net "A", 0 0, L_0x563bc45b2150; alias, 1 drivers
|
||||
v0x563bc45a6500_0 .net "B", 0 0, L_0x563bc45b2780; alias, 1 drivers
|
||||
v0x563bc45a65a0_0 .net "Carry", 0 0, L_0x563bc45b21e0; alias, 1 drivers
|
||||
v0x563bc45a6670_0 .net "Sum", 0 0, L_0x563bc45b2370; alias, 1 drivers
|
||||
S_0x563bc45a6e90 .scope module, "f3" "fulladder" 4 11, 5 1 0, S_0x563bc457f580;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x563bc45b2d00 .functor OR 1, L_0x563bc45b2900, L_0x563bc45b2a90, C4<0>, C4<0>;
|
||||
v0x563bc45a7c20_0 .net "A", 0 0, L_0x563bc45b2d90; 1 drivers
|
||||
v0x563bc45a7ce0_0 .net "B", 0 0, L_0x563bc45b2ec0; 1 drivers
|
||||
v0x563bc45a7db0_0 .net "Carry", 0 0, L_0x563bc45b30e0; 1 drivers
|
||||
v0x563bc45a7eb0_0 .net "CarryO", 0 0, L_0x563bc45b2d00; 1 drivers
|
||||
v0x563bc45a7f50_0 .net "Sum", 0 0, L_0x563bc45b2c20; 1 drivers
|
||||
v0x563bc45a8040_0 .net "and1", 0 0, L_0x563bc45b2900; 1 drivers
|
||||
v0x563bc45a8110_0 .net "and2", 0 0, L_0x563bc45b2a90; 1 drivers
|
||||
v0x563bc45a81e0_0 .net "xor1", 0 0, L_0x563bc45b2a00; 1 drivers
|
||||
S_0x563bc45a70a0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x563bc45a6e90;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x563bc45b2900 .functor AND 1, L_0x563bc45b2d90, L_0x563bc45b2ec0, C4<1>, C4<1>;
|
||||
L_0x563bc45b2a00 .functor XOR 1, L_0x563bc45b2d90, L_0x563bc45b2ec0, C4<0>, C4<0>;
|
||||
v0x563bc45a72b0_0 .net "A", 0 0, L_0x563bc45b2d90; alias, 1 drivers
|
||||
v0x563bc45a7370_0 .net "B", 0 0, L_0x563bc45b2ec0; alias, 1 drivers
|
||||
v0x563bc45a7430_0 .net "Carry", 0 0, L_0x563bc45b2900; alias, 1 drivers
|
||||
v0x563bc45a7500_0 .net "Sum", 0 0, L_0x563bc45b2a00; alias, 1 drivers
|
||||
S_0x563bc45a7670 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x563bc45a6e90;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x563bc45b2a90 .functor AND 1, L_0x563bc45b2a00, L_0x563bc45b30e0, C4<1>, C4<1>;
|
||||
L_0x563bc45b2c20 .functor XOR 1, L_0x563bc45b2a00, L_0x563bc45b30e0, C4<0>, C4<0>;
|
||||
v0x563bc45a7870_0 .net "A", 0 0, L_0x563bc45b2a00; alias, 1 drivers
|
||||
v0x563bc45a7940_0 .net "B", 0 0, L_0x563bc45b30e0; alias, 1 drivers
|
||||
v0x563bc45a79e0_0 .net "Carry", 0 0, L_0x563bc45b2a90; alias, 1 drivers
|
||||
v0x563bc45a7ab0_0 .net "Sum", 0 0, L_0x563bc45b2c20; alias, 1 drivers
|
||||
S_0x563bc45a82d0 .scope module, "h1" "halfadder" 4 8, 6 1 0, S_0x563bc457f580;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x563bc45b1580 .functor AND 1, L_0x563bc45b1700, L_0x563bc45b17a0, C4<1>, C4<1>;
|
||||
L_0x563bc45b15f0 .functor XOR 1, L_0x563bc45b1700, L_0x563bc45b17a0, C4<0>, C4<0>;
|
||||
v0x563bc45a84b0_0 .net "A", 0 0, L_0x563bc45b1700; 1 drivers
|
||||
v0x563bc45a8570_0 .net "B", 0 0, L_0x563bc45b17a0; 1 drivers
|
||||
v0x563bc45a8630_0 .net "Carry", 0 0, L_0x563bc45b1580; 1 drivers
|
||||
v0x563bc45a8700_0 .net "Sum", 0 0, L_0x563bc45b15f0; 1 drivers
|
||||
S_0x563bc45a8da0 .scope module, "a2" "addition" 3 17, 4 1 0, S_0x563bc4581020;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 4 "A";
|
||||
.port_info 1 /INPUT 4 "B";
|
||||
.port_info 2 /OUTPUT 5 "Y";
|
||||
v0x563bc45ad4f0_0 .net "A", 3 0, v0x563bc45b09d0_0; alias, 1 drivers
|
||||
v0x563bc45ad5f0_0 .net "B", 3 0, L_0x563bc45b4f90; 1 drivers
|
||||
v0x563bc45ad6d0_0 .net "Carry4", 3 0, L_0x563bc45b71d0; 1 drivers
|
||||
v0x563bc45ad790_0 .net "Y", 4 0, L_0x563bc45b4e80; alias, 1 drivers
|
||||
o0x7fe52eeaccf8 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
; Elide local net with no drivers, v0x563bc45ad870_0 name=_ivl_41
|
||||
L_0x563bc45b3400 .part v0x563bc45b09d0_0, 0, 1;
|
||||
L_0x563bc45b3530 .part L_0x563bc45b4f90, 0, 1;
|
||||
L_0x563bc45b3930 .part v0x563bc45b09d0_0, 1, 1;
|
||||
L_0x563bc45b3a60 .part L_0x563bc45b4f90, 1, 1;
|
||||
L_0x563bc45b3be0 .part L_0x563bc45b71d0, 0, 1;
|
||||
L_0x563bc45b4150 .part v0x563bc45b09d0_0, 2, 1;
|
||||
L_0x563bc45b42c0 .part L_0x563bc45b4f90, 2, 1;
|
||||
L_0x563bc45b43f0 .part L_0x563bc45b71d0, 1, 1;
|
||||
L_0x563bc45b4a00 .part v0x563bc45b09d0_0, 3, 1;
|
||||
L_0x563bc45b4b30 .part L_0x563bc45b4f90, 3, 1;
|
||||
L_0x563bc45b4d50 .part L_0x563bc45b71d0, 2, 1;
|
||||
LS_0x563bc45b4e80_0_0 .concat8 [ 1 1 1 1], L_0x563bc45b3390, L_0x563bc45b3800, L_0x563bc45b3fe0, L_0x563bc45b4890;
|
||||
LS_0x563bc45b4e80_0_4 .concat8 [ 1 0 0 0], L_0x563bc45b4970;
|
||||
L_0x563bc45b4e80 .concat8 [ 4 1 0 0], LS_0x563bc45b4e80_0_0, LS_0x563bc45b4e80_0_4;
|
||||
L_0x563bc45b71d0 .concat [ 1 1 1 1], L_0x563bc45b3320, L_0x563bc45b38c0, L_0x563bc45b40c0, o0x7fe52eeaccf8;
|
||||
S_0x563bc45a8fd0 .scope module, "f1" "fulladder" 4 9, 5 1 0, S_0x563bc45a8da0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x563bc45b38c0 .functor OR 1, L_0x563bc45b35d0, L_0x563bc45b36b0, C4<0>, C4<0>;
|
||||
v0x563bc45a9e00_0 .net "A", 0 0, L_0x563bc45b3930; 1 drivers
|
||||
v0x563bc45a9ec0_0 .net "B", 0 0, L_0x563bc45b3a60; 1 drivers
|
||||
v0x563bc45a9f90_0 .net "Carry", 0 0, L_0x563bc45b3be0; 1 drivers
|
||||
v0x563bc45aa090_0 .net "CarryO", 0 0, L_0x563bc45b38c0; 1 drivers
|
||||
v0x563bc45aa130_0 .net "Sum", 0 0, L_0x563bc45b3800; 1 drivers
|
||||
v0x563bc45aa220_0 .net "and1", 0 0, L_0x563bc45b35d0; 1 drivers
|
||||
v0x563bc45aa2f0_0 .net "and2", 0 0, L_0x563bc45b36b0; 1 drivers
|
||||
v0x563bc45aa3c0_0 .net "xor1", 0 0, L_0x563bc45b3640; 1 drivers
|
||||
S_0x563bc45a91d0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x563bc45a8fd0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x563bc45b35d0 .functor AND 1, L_0x563bc45b3930, L_0x563bc45b3a60, C4<1>, C4<1>;
|
||||
L_0x563bc45b3640 .functor XOR 1, L_0x563bc45b3930, L_0x563bc45b3a60, C4<0>, C4<0>;
|
||||
v0x563bc45a9400_0 .net "A", 0 0, L_0x563bc45b3930; alias, 1 drivers
|
||||
v0x563bc45a94e0_0 .net "B", 0 0, L_0x563bc45b3a60; alias, 1 drivers
|
||||
v0x563bc45a95a0_0 .net "Carry", 0 0, L_0x563bc45b35d0; alias, 1 drivers
|
||||
v0x563bc45a9670_0 .net "Sum", 0 0, L_0x563bc45b3640; alias, 1 drivers
|
||||
S_0x563bc45a97e0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x563bc45a8fd0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x563bc45b36b0 .functor AND 1, L_0x563bc45b3640, L_0x563bc45b3be0, C4<1>, C4<1>;
|
||||
L_0x563bc45b3800 .functor XOR 1, L_0x563bc45b3640, L_0x563bc45b3be0, C4<0>, C4<0>;
|
||||
v0x563bc45a9a50_0 .net "A", 0 0, L_0x563bc45b3640; alias, 1 drivers
|
||||
v0x563bc45a9b20_0 .net "B", 0 0, L_0x563bc45b3be0; alias, 1 drivers
|
||||
v0x563bc45a9bc0_0 .net "Carry", 0 0, L_0x563bc45b36b0; alias, 1 drivers
|
||||
v0x563bc45a9c90_0 .net "Sum", 0 0, L_0x563bc45b3800; alias, 1 drivers
|
||||
S_0x563bc45aa4b0 .scope module, "f2" "fulladder" 4 10, 5 1 0, S_0x563bc45a8da0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x563bc45b40c0 .functor OR 1, L_0x563bc45b3d10, L_0x563bc45b3e90, C4<0>, C4<0>;
|
||||
v0x563bc45ab310_0 .net "A", 0 0, L_0x563bc45b4150; 1 drivers
|
||||
v0x563bc45ab3d0_0 .net "B", 0 0, L_0x563bc45b42c0; 1 drivers
|
||||
v0x563bc45ab4a0_0 .net "Carry", 0 0, L_0x563bc45b43f0; 1 drivers
|
||||
v0x563bc45ab5a0_0 .net "CarryO", 0 0, L_0x563bc45b40c0; 1 drivers
|
||||
v0x563bc45ab640_0 .net "Sum", 0 0, L_0x563bc45b3fe0; 1 drivers
|
||||
v0x563bc45ab730_0 .net "and1", 0 0, L_0x563bc45b3d10; 1 drivers
|
||||
v0x563bc45ab800_0 .net "and2", 0 0, L_0x563bc45b3e90; 1 drivers
|
||||
v0x563bc45ab8d0_0 .net "xor1", 0 0, L_0x563bc45b3e20; 1 drivers
|
||||
S_0x563bc45aa690 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x563bc45aa4b0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x563bc45b3d10 .functor AND 1, L_0x563bc45b4150, L_0x563bc45b42c0, C4<1>, C4<1>;
|
||||
L_0x563bc45b3e20 .functor XOR 1, L_0x563bc45b4150, L_0x563bc45b42c0, C4<0>, C4<0>;
|
||||
v0x563bc45aa910_0 .net "A", 0 0, L_0x563bc45b4150; alias, 1 drivers
|
||||
v0x563bc45aa9f0_0 .net "B", 0 0, L_0x563bc45b42c0; alias, 1 drivers
|
||||
v0x563bc45aaab0_0 .net "Carry", 0 0, L_0x563bc45b3d10; alias, 1 drivers
|
||||
v0x563bc45aab80_0 .net "Sum", 0 0, L_0x563bc45b3e20; alias, 1 drivers
|
||||
S_0x563bc45aacf0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x563bc45aa4b0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x563bc45b3e90 .functor AND 1, L_0x563bc45b3e20, L_0x563bc45b43f0, C4<1>, C4<1>;
|
||||
L_0x563bc45b3fe0 .functor XOR 1, L_0x563bc45b3e20, L_0x563bc45b43f0, C4<0>, C4<0>;
|
||||
v0x563bc45aaf60_0 .net "A", 0 0, L_0x563bc45b3e20; alias, 1 drivers
|
||||
v0x563bc45ab030_0 .net "B", 0 0, L_0x563bc45b43f0; alias, 1 drivers
|
||||
v0x563bc45ab0d0_0 .net "Carry", 0 0, L_0x563bc45b3e90; alias, 1 drivers
|
||||
v0x563bc45ab1a0_0 .net "Sum", 0 0, L_0x563bc45b3fe0; alias, 1 drivers
|
||||
S_0x563bc45ab9c0 .scope module, "f3" "fulladder" 4 11, 5 1 0, S_0x563bc45a8da0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x563bc45b4970 .functor OR 1, L_0x563bc45b4570, L_0x563bc45b4700, C4<0>, C4<0>;
|
||||
v0x563bc45ac830_0 .net "A", 0 0, L_0x563bc45b4a00; 1 drivers
|
||||
v0x563bc45ac8f0_0 .net "B", 0 0, L_0x563bc45b4b30; 1 drivers
|
||||
v0x563bc45ac9c0_0 .net "Carry", 0 0, L_0x563bc45b4d50; 1 drivers
|
||||
v0x563bc45acac0_0 .net "CarryO", 0 0, L_0x563bc45b4970; 1 drivers
|
||||
v0x563bc45acb60_0 .net "Sum", 0 0, L_0x563bc45b4890; 1 drivers
|
||||
v0x563bc45acc50_0 .net "and1", 0 0, L_0x563bc45b4570; 1 drivers
|
||||
v0x563bc45acd20_0 .net "and2", 0 0, L_0x563bc45b4700; 1 drivers
|
||||
v0x563bc45acdf0_0 .net "xor1", 0 0, L_0x563bc45b4670; 1 drivers
|
||||
S_0x563bc45abbd0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x563bc45ab9c0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x563bc45b4570 .functor AND 1, L_0x563bc45b4a00, L_0x563bc45b4b30, C4<1>, C4<1>;
|
||||
L_0x563bc45b4670 .functor XOR 1, L_0x563bc45b4a00, L_0x563bc45b4b30, C4<0>, C4<0>;
|
||||
v0x563bc45abe50_0 .net "A", 0 0, L_0x563bc45b4a00; alias, 1 drivers
|
||||
v0x563bc45abf10_0 .net "B", 0 0, L_0x563bc45b4b30; alias, 1 drivers
|
||||
v0x563bc45abfd0_0 .net "Carry", 0 0, L_0x563bc45b4570; alias, 1 drivers
|
||||
v0x563bc45ac0a0_0 .net "Sum", 0 0, L_0x563bc45b4670; alias, 1 drivers
|
||||
S_0x563bc45ac210 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x563bc45ab9c0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x563bc45b4700 .functor AND 1, L_0x563bc45b4670, L_0x563bc45b4d50, C4<1>, C4<1>;
|
||||
L_0x563bc45b4890 .functor XOR 1, L_0x563bc45b4670, L_0x563bc45b4d50, C4<0>, C4<0>;
|
||||
v0x563bc45ac480_0 .net "A", 0 0, L_0x563bc45b4670; alias, 1 drivers
|
||||
v0x563bc45ac550_0 .net "B", 0 0, L_0x563bc45b4d50; alias, 1 drivers
|
||||
v0x563bc45ac5f0_0 .net "Carry", 0 0, L_0x563bc45b4700; alias, 1 drivers
|
||||
v0x563bc45ac6c0_0 .net "Sum", 0 0, L_0x563bc45b4890; alias, 1 drivers
|
||||
S_0x563bc45acee0 .scope module, "h1" "halfadder" 4 8, 6 1 0, S_0x563bc45a8da0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x563bc45b3320 .functor AND 1, L_0x563bc45b3400, L_0x563bc45b3530, C4<1>, C4<1>;
|
||||
L_0x563bc45b3390 .functor XOR 1, L_0x563bc45b3400, L_0x563bc45b3530, C4<0>, C4<0>;
|
||||
v0x563bc45ad130_0 .net "A", 0 0, L_0x563bc45b3400; 1 drivers
|
||||
v0x563bc45ad1f0_0 .net "B", 0 0, L_0x563bc45b3530; 1 drivers
|
||||
v0x563bc45ad2b0_0 .net "Carry", 0 0, L_0x563bc45b3320; 1 drivers
|
||||
v0x563bc45ad380_0 .net "Sum", 0 0, L_0x563bc45b3390; 1 drivers
|
||||
S_0x563bc45ada20 .scope module, "od1" "overflowDetect" 3 18, 7 1 0, S_0x563bc4581020;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 2 "opCode";
|
||||
.port_info 1 /INPUT 4 "A";
|
||||
.port_info 2 /INPUT 4 "B";
|
||||
.port_info 3 /INPUT 5 "Y";
|
||||
.port_info 4 /OUTPUT 1 "overflowDetect";
|
||||
L_0x563bc45b5070 .functor OR 1, L_0x563bc45b5100, L_0x563bc45b51a0, C4<0>, C4<0>;
|
||||
L_0x563bc45b5240 .functor XOR 1, L_0x563bc45b52b0, L_0x563bc45b5430, C4<0>, C4<0>;
|
||||
L_0x563bc45b55e0 .functor AND 1, L_0x563bc45b5650, L_0x563bc45b5740, C4<1>, C4<1>;
|
||||
L_0x563bc45b5870 .functor OR 1, L_0x563bc45b5930, L_0x563bc45b55e0, C4<0>, C4<0>;
|
||||
L_0x563bc45b5a20 .functor XOR 1, L_0x563bc45b5a90, L_0x563bc45b5bd0, C4<0>, C4<0>;
|
||||
L_0x563bc45b5dd0 .functor OR 1, L_0x563bc45b5ed0, L_0x563bc45b5a20, C4<0>, C4<0>;
|
||||
L_0x563bc45b6020 .functor OR 1, L_0x563bc45b5870, L_0x563bc45b5dd0, C4<0>, C4<0>;
|
||||
L_0x563bc45b6090 .functor AND 1, L_0x563bc45b5240, L_0x563bc45b5070, C4<1>, C4<1>;
|
||||
L_0x563bc45b61f0 .functor AND 1, L_0x563bc45b6020, L_0x563bc45b6090, C4<1>, C4<1>;
|
||||
v0x563bc45adc30_0 .net "A", 3 0, v0x563bc45b09d0_0; alias, 1 drivers
|
||||
v0x563bc45add00_0 .net "AandSum", 0 0, L_0x563bc45b5240; 1 drivers
|
||||
v0x563bc45adda0_0 .net "B", 3 0, v0x563bc45b0a90_0; alias, 1 drivers
|
||||
v0x563bc45ade90_0 .net "Y", 4 0, L_0x563bc45b4e80; alias, 1 drivers
|
||||
v0x563bc45adf80_0 .net *"_ivl_1", 0 0, L_0x563bc45b5100; 1 drivers
|
||||
v0x563bc45ae090_0 .net *"_ivl_11", 0 0, L_0x563bc45b5740; 1 drivers
|
||||
v0x563bc45ae170_0 .net *"_ivl_13", 0 0, L_0x563bc45b5930; 1 drivers
|
||||
v0x563bc45ae250_0 .net *"_ivl_15", 0 0, L_0x563bc45b5a90; 1 drivers
|
||||
v0x563bc45ae330_0 .net *"_ivl_17", 0 0, L_0x563bc45b5bd0; 1 drivers
|
||||
v0x563bc45ae4a0_0 .net *"_ivl_19", 0 0, L_0x563bc45b5ed0; 1 drivers
|
||||
v0x563bc45ae580_0 .net *"_ivl_3", 0 0, L_0x563bc45b51a0; 1 drivers
|
||||
v0x563bc45ae660_0 .net *"_ivl_5", 0 0, L_0x563bc45b52b0; 1 drivers
|
||||
v0x563bc45ae740_0 .net *"_ivl_7", 0 0, L_0x563bc45b5430; 1 drivers
|
||||
v0x563bc45ae820_0 .net *"_ivl_9", 0 0, L_0x563bc45b5650; 1 drivers
|
||||
v0x563bc45ae900_0 .net "detect1", 0 0, L_0x563bc45b6020; 1 drivers
|
||||
v0x563bc45ae9c0_0 .net "detect2", 0 0, L_0x563bc45b6090; 1 drivers
|
||||
v0x563bc45aea80_0 .net "opC", 0 0, L_0x563bc45b5070; 1 drivers
|
||||
L_0x7fe52ee62060 .functor BUFT 1, C4<10>, C4<0>, C4<0>, C4<0>;
|
||||
v0x563bc45aeb40_0 .net "opCode", 1 0, L_0x7fe52ee62060; 1 drivers
|
||||
v0x563bc45aec20_0 .net "overflowDetect", 0 0, L_0x563bc45b61f0; alias, 1 drivers
|
||||
v0x563bc45aece0_0 .net "sign1", 0 0, L_0x563bc45b55e0; 1 drivers
|
||||
v0x563bc45aeda0_0 .net "sign2", 0 0, L_0x563bc45b5870; 1 drivers
|
||||
v0x563bc45aee60_0 .net "sign3", 0 0, L_0x563bc45b5a20; 1 drivers
|
||||
v0x563bc45aef20_0 .net "sign4", 0 0, L_0x563bc45b5dd0; 1 drivers
|
||||
L_0x563bc45b5100 .part L_0x7fe52ee62060, 0, 1;
|
||||
L_0x563bc45b51a0 .part L_0x7fe52ee62060, 1, 1;
|
||||
L_0x563bc45b52b0 .part L_0x563bc45b4e80, 4, 1;
|
||||
L_0x563bc45b5430 .part v0x563bc45b09d0_0, 3, 1;
|
||||
L_0x563bc45b5650 .part v0x563bc45b09d0_0, 3, 1;
|
||||
L_0x563bc45b5740 .part v0x563bc45b0a90_0, 3, 1;
|
||||
L_0x563bc45b5930 .part L_0x7fe52ee62060, 0, 1;
|
||||
L_0x563bc45b5a90 .part v0x563bc45b09d0_0, 3, 1;
|
||||
L_0x563bc45b5bd0 .part v0x563bc45b0a90_0, 3, 1;
|
||||
L_0x563bc45b5ed0 .part L_0x7fe52ee62060, 1, 1;
|
||||
.scope S_0x563bc4582ac0;
|
||||
T_0 ;
|
||||
%vpi_call 2 16 "$dumpfile", "subtraction.vcd" {0 0 0};
|
||||
%vpi_call 2 17 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 5, 0, 4;
|
||||
%store/vec4 v0x563bc45b09d0_0, 0, 4;
|
||||
%pushi/vec4 4, 0, 4;
|
||||
%store/vec4 v0x563bc45b0a90_0, 0, 4;
|
||||
%delay 5, 0;
|
||||
%pushi/vec4 8, 0, 4;
|
||||
%store/vec4 v0x563bc45b09d0_0, 0, 4;
|
||||
%pushi/vec4 7, 0, 4;
|
||||
%store/vec4 v0x563bc45b0a90_0, 0, 4;
|
||||
%delay 5, 0;
|
||||
%pushi/vec4 5, 0, 4;
|
||||
%store/vec4 v0x563bc45b09d0_0, 0, 4;
|
||||
%pushi/vec4 8, 0, 4;
|
||||
%store/vec4 v0x563bc45b0a90_0, 0, 4;
|
||||
%delay 5, 0;
|
||||
%vpi_call 2 21 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 8;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"subtractionTB.v";
|
||||
"subtraction.v";
|
||||
"addition.v";
|
||||
"fulladder.v";
|
||||
"halfadder.v";
|
||||
"overflowDetect.v";
|
||||
27
project/subtraction.v
Normal file
27
project/subtraction.v
Normal file
@ -0,0 +1,27 @@
|
||||
module subtraction (
|
||||
input [3:0] A, B,
|
||||
output [4:0] Y
|
||||
);
|
||||
|
||||
wire [3:0] xB;
|
||||
wire [4:0] notB;
|
||||
wire [4:0] Y1;
|
||||
wire overflow;
|
||||
|
||||
not n1 (xB[0], B[0]);
|
||||
not n2 (xB[1], B[1]);
|
||||
not n3 (xB[2], B[2]);
|
||||
not n4 (xB[3], B[3]);
|
||||
|
||||
addition a1 (.A(xB), .B(4'b0001), .Y(notB));
|
||||
addition a2 (.A(A), .B(notB[3:0]), .Y(Y1));
|
||||
overflowDetect od1 (.opCode(2'b10), .A(A), .B(B), .Y(Y1), .overflowDetect(overflow));
|
||||
|
||||
or o1 (Y[0], Y1[0], 1'b0);
|
||||
or o2 (Y[1], Y1[1], 1'b0);
|
||||
or o3 (Y[2], Y1[2], 1'b0);
|
||||
or o4 (Y[3], Y1[3], 1'b0);
|
||||
|
||||
xor(Y[4], overflow, Y1[4]);
|
||||
|
||||
endmodule
|
||||
408
project/subtraction.vcd
Normal file
408
project/subtraction.vcd
Normal file
@ -0,0 +1,408 @@
|
||||
$date
|
||||
Sat Dec 14 04:55:25 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module subtractionTB $end
|
||||
$var wire 1 ! overflow $end
|
||||
$var wire 5 " Y [4:0] $end
|
||||
$var reg 4 # A [3:0] $end
|
||||
$var reg 4 $ B [3:0] $end
|
||||
$scope module uut $end
|
||||
$var wire 4 % A [3:0] $end
|
||||
$var wire 4 & B [3:0] $end
|
||||
$var wire 4 ' xB [3:0] $end
|
||||
$var wire 1 ( overflow $end
|
||||
$var wire 5 ) notB [4:0] $end
|
||||
$var wire 5 * Y1 [4:0] $end
|
||||
$var wire 5 + Y [4:0] $end
|
||||
$scope module a1 $end
|
||||
$var wire 4 , A [3:0] $end
|
||||
$var wire 4 - B [3:0] $end
|
||||
$var wire 5 . Y [4:0] $end
|
||||
$var wire 4 / Carry4 [3:0] $end
|
||||
$scope module f1 $end
|
||||
$var wire 1 0 A $end
|
||||
$var wire 1 1 B $end
|
||||
$var wire 1 2 Carry $end
|
||||
$var wire 1 3 CarryO $end
|
||||
$var wire 1 4 xor1 $end
|
||||
$var wire 1 5 and2 $end
|
||||
$var wire 1 6 and1 $end
|
||||
$var wire 1 7 Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 0 A $end
|
||||
$var wire 1 1 B $end
|
||||
$var wire 1 6 Carry $end
|
||||
$var wire 1 4 Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 4 A $end
|
||||
$var wire 1 2 B $end
|
||||
$var wire 1 5 Carry $end
|
||||
$var wire 1 7 Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module f2 $end
|
||||
$var wire 1 8 A $end
|
||||
$var wire 1 9 B $end
|
||||
$var wire 1 : Carry $end
|
||||
$var wire 1 ; CarryO $end
|
||||
$var wire 1 < xor1 $end
|
||||
$var wire 1 = and2 $end
|
||||
$var wire 1 > and1 $end
|
||||
$var wire 1 ? Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 8 A $end
|
||||
$var wire 1 9 B $end
|
||||
$var wire 1 > Carry $end
|
||||
$var wire 1 < Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 < A $end
|
||||
$var wire 1 : B $end
|
||||
$var wire 1 = Carry $end
|
||||
$var wire 1 ? Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module f3 $end
|
||||
$var wire 1 @ A $end
|
||||
$var wire 1 A B $end
|
||||
$var wire 1 B Carry $end
|
||||
$var wire 1 C CarryO $end
|
||||
$var wire 1 D xor1 $end
|
||||
$var wire 1 E and2 $end
|
||||
$var wire 1 F and1 $end
|
||||
$var wire 1 G Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 @ A $end
|
||||
$var wire 1 A B $end
|
||||
$var wire 1 F Carry $end
|
||||
$var wire 1 D Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 D A $end
|
||||
$var wire 1 B B $end
|
||||
$var wire 1 E Carry $end
|
||||
$var wire 1 G Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 H A $end
|
||||
$var wire 1 I B $end
|
||||
$var wire 1 J Carry $end
|
||||
$var wire 1 K Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module a2 $end
|
||||
$var wire 4 L A [3:0] $end
|
||||
$var wire 4 M B [3:0] $end
|
||||
$var wire 5 N Y [4:0] $end
|
||||
$var wire 4 O Carry4 [3:0] $end
|
||||
$scope module f1 $end
|
||||
$var wire 1 P A $end
|
||||
$var wire 1 Q B $end
|
||||
$var wire 1 R Carry $end
|
||||
$var wire 1 S CarryO $end
|
||||
$var wire 1 T xor1 $end
|
||||
$var wire 1 U and2 $end
|
||||
$var wire 1 V and1 $end
|
||||
$var wire 1 W Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 P A $end
|
||||
$var wire 1 Q B $end
|
||||
$var wire 1 V Carry $end
|
||||
$var wire 1 T Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 T A $end
|
||||
$var wire 1 R B $end
|
||||
$var wire 1 U Carry $end
|
||||
$var wire 1 W Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module f2 $end
|
||||
$var wire 1 X A $end
|
||||
$var wire 1 Y B $end
|
||||
$var wire 1 Z Carry $end
|
||||
$var wire 1 [ CarryO $end
|
||||
$var wire 1 \ xor1 $end
|
||||
$var wire 1 ] and2 $end
|
||||
$var wire 1 ^ and1 $end
|
||||
$var wire 1 _ Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 X A $end
|
||||
$var wire 1 Y B $end
|
||||
$var wire 1 ^ Carry $end
|
||||
$var wire 1 \ Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 \ A $end
|
||||
$var wire 1 Z B $end
|
||||
$var wire 1 ] Carry $end
|
||||
$var wire 1 _ Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module f3 $end
|
||||
$var wire 1 ` A $end
|
||||
$var wire 1 a B $end
|
||||
$var wire 1 b Carry $end
|
||||
$var wire 1 c CarryO $end
|
||||
$var wire 1 d xor1 $end
|
||||
$var wire 1 e and2 $end
|
||||
$var wire 1 f and1 $end
|
||||
$var wire 1 g Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 ` A $end
|
||||
$var wire 1 a B $end
|
||||
$var wire 1 f Carry $end
|
||||
$var wire 1 d Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 d A $end
|
||||
$var wire 1 b B $end
|
||||
$var wire 1 e Carry $end
|
||||
$var wire 1 g Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 h A $end
|
||||
$var wire 1 i B $end
|
||||
$var wire 1 j Carry $end
|
||||
$var wire 1 k Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module od1 $end
|
||||
$var wire 4 l A [3:0] $end
|
||||
$var wire 1 m AandSum $end
|
||||
$var wire 4 n B [3:0] $end
|
||||
$var wire 5 o Y [4:0] $end
|
||||
$var wire 1 p detect1 $end
|
||||
$var wire 1 q detect2 $end
|
||||
$var wire 1 r opC $end
|
||||
$var wire 2 s opCode [1:0] $end
|
||||
$var wire 1 ( overflowDetect $end
|
||||
$var wire 1 t sign1 $end
|
||||
$var wire 1 u sign2 $end
|
||||
$var wire 1 v sign3 $end
|
||||
$var wire 1 w sign4 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
1w
|
||||
0v
|
||||
0u
|
||||
0t
|
||||
b10 s
|
||||
1r
|
||||
1q
|
||||
1p
|
||||
b10001 o
|
||||
b100 n
|
||||
1m
|
||||
b101 l
|
||||
1k
|
||||
0j
|
||||
0i
|
||||
1h
|
||||
0g
|
||||
0f
|
||||
1e
|
||||
1d
|
||||
1c
|
||||
1b
|
||||
1a
|
||||
0`
|
||||
0_
|
||||
1^
|
||||
0]
|
||||
0\
|
||||
1[
|
||||
0Z
|
||||
1Y
|
||||
1X
|
||||
0W
|
||||
0V
|
||||
0U
|
||||
0T
|
||||
0S
|
||||
0R
|
||||
0Q
|
||||
0P
|
||||
bz100 O
|
||||
b10001 N
|
||||
b1100 M
|
||||
b101 L
|
||||
0K
|
||||
1J
|
||||
1I
|
||||
1H
|
||||
1G
|
||||
0F
|
||||
0E
|
||||
1D
|
||||
0C
|
||||
0B
|
||||
0A
|
||||
1@
|
||||
1?
|
||||
0>
|
||||
0=
|
||||
0<
|
||||
0;
|
||||
1:
|
||||
09
|
||||
08
|
||||
07
|
||||
06
|
||||
15
|
||||
14
|
||||
13
|
||||
12
|
||||
01
|
||||
10
|
||||
bz011 /
|
||||
b1100 .
|
||||
b1 -
|
||||
b1011 ,
|
||||
b1 +
|
||||
b10001 *
|
||||
b1100 )
|
||||
1(
|
||||
b1011 '
|
||||
b100 &
|
||||
b101 %
|
||||
b100 $
|
||||
b101 #
|
||||
b1 "
|
||||
1!
|
||||
$end
|
||||
#5
|
||||
0Y
|
||||
0W
|
||||
0?
|
||||
0T
|
||||
0:
|
||||
1i
|
||||
0Q
|
||||
03
|
||||
02
|
||||
b1001 M
|
||||
05
|
||||
07
|
||||
bz000 /
|
||||
0J
|
||||
b1001 )
|
||||
b1001 .
|
||||
1K
|
||||
04
|
||||
b10001 "
|
||||
b10001 +
|
||||
0b
|
||||
0!
|
||||
0(
|
||||
0H
|
||||
00
|
||||
bz000 O
|
||||
0[
|
||||
0_
|
||||
0e
|
||||
0g
|
||||
0q
|
||||
b1000 '
|
||||
b1000 ,
|
||||
b10001 *
|
||||
b10001 N
|
||||
b10001 o
|
||||
1k
|
||||
0^
|
||||
0\
|
||||
1f
|
||||
0d
|
||||
0m
|
||||
1v
|
||||
0h
|
||||
0X
|
||||
1`
|
||||
b111 $
|
||||
b111 &
|
||||
b111 n
|
||||
b1000 #
|
||||
b1000 %
|
||||
b1000 L
|
||||
b1000 l
|
||||
#10
|
||||
1B
|
||||
1;
|
||||
0Z
|
||||
1=
|
||||
0S
|
||||
0b
|
||||
1:
|
||||
0U
|
||||
0[
|
||||
13
|
||||
0T
|
||||
0^
|
||||
15
|
||||
0i
|
||||
0Q
|
||||
0Y
|
||||
1a
|
||||
12
|
||||
b1000 M
|
||||
07
|
||||
0?
|
||||
1G
|
||||
bz111 /
|
||||
1J
|
||||
b1000 )
|
||||
b1000 .
|
||||
0K
|
||||
14
|
||||
1<
|
||||
0D
|
||||
0W
|
||||
b1101 "
|
||||
b1101 +
|
||||
0!
|
||||
0(
|
||||
1H
|
||||
10
|
||||
18
|
||||
0@
|
||||
0R
|
||||
1_
|
||||
0c
|
||||
1g
|
||||
0q
|
||||
b111 '
|
||||
b111 ,
|
||||
bz000 O
|
||||
0j
|
||||
b1101 *
|
||||
b1101 N
|
||||
b1101 o
|
||||
1k
|
||||
1\
|
||||
0f
|
||||
1d
|
||||
0m
|
||||
1h
|
||||
1X
|
||||
0`
|
||||
b1000 $
|
||||
b1000 &
|
||||
b1000 n
|
||||
b101 #
|
||||
b101 %
|
||||
b101 L
|
||||
b101 l
|
||||
#15
|
||||
24
project/subtractionTB.v
Normal file
24
project/subtractionTB.v
Normal file
@ -0,0 +1,24 @@
|
||||
module subtractionTB();
|
||||
|
||||
reg [3:0] A, B;
|
||||
wire [4:0] Y;
|
||||
wire overflow;
|
||||
|
||||
subtraction uut (
|
||||
.A(A),
|
||||
.B(B),
|
||||
.Y(Y)
|
||||
);
|
||||
|
||||
assign overflow = uut.overflow;
|
||||
|
||||
initial begin
|
||||
$dumpfile("subtraction.vcd");
|
||||
$dumpvars;
|
||||
A = 4'b0101; B = 4'b0100; #5;
|
||||
A = 4'b1000; B = 4'b0111; #5;
|
||||
A = 4'b0101; B = 4'b1000; #5;
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
x
Reference in New Issue
Block a user