13 lines
247 B
Verilog
13 lines
247 B
Verilog
module fulladder (
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input A, B, Carry,
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output Sum, CarryO
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);
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wire xor1, and1, and2;
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halfadder h1(.A(A), .B(B), .Sum(xor1), .Carry(and1));
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halfadder h2 (.A(xor1), .B(Carry), .Sum(Sum), .Carry(and2));
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or o1 (CarryO, and1, and2);
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endmodule
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