kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
21 Commits 1 Branch 0 Tags
cbf97501ea7ef556355ab3ad9fb5e9078ce7a88b
T
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
kaltinsoy cbf97501ea 4-bit ALU
2024-12-14 05:00:35 +03:00
gowin
xorGate
2024-12-09 22:57:42 +03:00
iverilog
lab3
2024-12-12 01:05:57 +03:00
project
4-bit ALU
2024-12-14 05:00:35 +03:00
tests
rearrangement
2024-12-01 02:01:08 +03:00
S
Description
No description provided
1.1 MiB
Languages
Verilog 99.2%
Shell 0.5%
Coq 0.3%