95 lines
839 B
Plaintext
95 lines
839 B
Plaintext
$date
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Fri Dec 13 20:24:01 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module opCodeTB $end
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$var wire 8 ! opCode [7:0] $end
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$var reg 1 " A $end
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$var reg 1 # B $end
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$var reg 1 $ C $end
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$scope module uut $end
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$var wire 1 " A $end
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$var wire 1 # B $end
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$var wire 1 $ C $end
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$var wire 1 % and1 $end
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$var wire 1 & and2 $end
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$var wire 1 ' and3 $end
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$var wire 1 ( and4 $end
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$var wire 1 ) notA $end
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$var wire 1 * notB $end
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$var wire 1 + notC $end
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$var wire 8 , opCode [7:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b1 ,
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1+
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1*
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1)
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1(
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0'
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0&
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0%
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0$
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0#
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0"
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b1 !
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$end
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#3
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0+
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b10 !
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b10 ,
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1$
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#6
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0(
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1+
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b100 !
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b100 ,
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0*
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1&
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0$
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1#
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#9
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0+
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b1000 !
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b1000 ,
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1$
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#12
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1'
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1+
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b10000 !
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b10000 ,
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1*
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0&
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0)
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0$
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0#
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1"
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#15
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0+
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b100000 !
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b100000 ,
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1$
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#18
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0'
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1+
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b1000000 !
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b1000000 ,
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0*
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1%
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0$
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1#
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#21
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0+
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b10000000 !
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b10000000 ,
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1$
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#24
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