28 lines
513 B
Verilog
28 lines
513 B
Verilog
module opCodeTB();
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reg A, B, C;
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wire [7:0] opCode;
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opCode uut (
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.A(A),
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.B(B),
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.C(C),
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.opCode(opCode)
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);
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initial begin
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$dumpfile("opCode.vcd");
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$dumpvars;
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A = 1'b0; B = 1'b0; C = 1'b0; #3;
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A = 1'b0; B = 1'b0; C = 1'b1; #3;
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A = 1'b0; B = 1'b1; C = 1'b0; #3;
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A = 1'b0; B = 1'b1; C = 1'b1; #3;
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A = 1'b1; B = 1'b0; C = 1'b0; #3;
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A = 1'b1; B = 1'b0; C = 1'b1; #3;
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A = 1'b1; B = 1'b1; C = 1'b0; #3;
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A = 1'b1; B = 1'b1; C = 1'b1; #3;
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$finish;
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end
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endmodule
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