26 lines
502 B
Verilog
26 lines
502 B
Verilog
module overflowDetect (
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input [1:0] opCode,
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input [3:0] A, B,
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input [4:0] Y,
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output overflowDetect
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);
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wire opC,AandSum;
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wire sign1, sign2, sign3, sign4;
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wire detect1, detect2;
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or o1 (opC, opCode[0], opCode[1]);
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xor xo1 (AandSum, Y[4], A[3]);
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and a1 (sign1, A[3], B[3]);
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or o2 (sign2, opCode[0], sign1);
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xor a2 (sign3, A[3], B[3]);
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or o3 (sign4, opCode[1], sign3);
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or o4 (detect1, sign2, sign4);
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and a3 (detect2, AandSum, opC);
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and a4 (overflowDetect, detect1, detect2);
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endmodule
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