lab3
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192
iverilog/tobb/lab3/bit3Adder
Normal file
192
iverilog/tobb/lab3/bit3Adder
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@ -0,0 +1,192 @@
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#! /usr/bin/vvp
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:ivl_version "11.0 (stable)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
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S_0x5635a3500ed0 .scope module, "bit3AdderTB" "bit3AdderTB" 2 1;
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.timescale 0 0;
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v0x5635a352f990_0 .var "A", 2 0;
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v0x5635a352fa50_0 .var "B", 2 0;
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v0x5635a352fb20_0 .net "Sum", 3 0, L_0x5635a3531200; 1 drivers
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S_0x5635a350cec0 .scope module, "uut" "bit3Adder" 2 7, 3 1 0, S_0x5635a3500ed0;
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.timescale 0 0;
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.port_info 0 /INPUT 3 "A";
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.port_info 1 /INPUT 3 "B";
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.port_info 2 /OUTPUT 4 "Sum";
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v0x5635a352f460_0 .net "A", 2 0, v0x5635a352f990_0; 1 drivers
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v0x5635a352f560_0 .net "B", 2 0, v0x5635a352fa50_0; 1 drivers
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v0x5635a352f640_0 .net "Carry3", 2 0, L_0x5635a35312a0; 1 drivers
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v0x5635a352f700_0 .net "Sum", 3 0, L_0x5635a3531200; alias, 1 drivers
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o0x7f05b0813a38 .functor BUFZ 1, C4<z>; HiZ drive
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; Elide local net with no drivers, v0x5635a352f7e0_0 name=_ivl_31
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L_0x5635a352fe60 .part v0x5635a352f990_0, 0, 1;
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L_0x5635a352ff50 .part v0x5635a352fa50_0, 0, 1;
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L_0x5635a3530530 .part v0x5635a352f990_0, 1, 1;
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L_0x5635a3530660 .part v0x5635a352fa50_0, 1, 1;
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L_0x5635a3530790 .part L_0x5635a35312a0, 0, 1;
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L_0x5635a3530cc0 .part v0x5635a352f990_0, 2, 1;
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L_0x5635a3530ec0 .part v0x5635a352fa50_0, 2, 1;
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L_0x5635a3531080 .part L_0x5635a35312a0, 1, 1;
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L_0x5635a3531200 .concat8 [ 1 1 1 1], L_0x5635a352fc20, L_0x5635a3530230, L_0x5635a35309c0, L_0x5635a3530c30;
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L_0x5635a35312a0 .concat [ 1 1 1 0], L_0x5635a352fd20, L_0x5635a35304a0, o0x7f05b0813a38;
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S_0x5635a350d050 .scope module, "f1" "fulladder" 3 10, 4 1 0, S_0x5635a350cec0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /INPUT 1 "CarryIn";
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.port_info 3 /OUTPUT 1 "Sum";
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.port_info 4 /OUTPUT 1 "CarryOut";
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L_0x5635a35304a0 .functor OR 1, L_0x5635a3530150, L_0x5635a35303c0, C4<0>, C4<0>;
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v0x5635a352d3d0_0 .net "A", 0 0, L_0x5635a3530530; 1 drivers
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v0x5635a352d490_0 .net "ABandCIn", 0 0, L_0x5635a35303c0; 1 drivers
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v0x5635a352d560_0 .net "AandB", 0 0, L_0x5635a3530150; 1 drivers
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v0x5635a352d660_0 .net "AxorB", 0 0, L_0x5635a3530040; 1 drivers
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v0x5635a352d750_0 .net "B", 0 0, L_0x5635a3530660; 1 drivers
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v0x5635a352d840_0 .net "CarryIn", 0 0, L_0x5635a3530790; 1 drivers
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v0x5635a352d8e0_0 .net "CarryOut", 0 0, L_0x5635a35304a0; 1 drivers
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v0x5635a352d980_0 .net "Sum", 0 0, L_0x5635a3530230; 1 drivers
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S_0x5635a35114b0 .scope module, "h1" "halfadder" 4 8, 5 1 0, S_0x5635a350d050;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "Sum";
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.port_info 3 /OUTPUT 1 "CarryOut";
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L_0x5635a3530040 .functor XOR 1, L_0x5635a3530530, L_0x5635a3530660, C4<0>, C4<0>;
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L_0x5635a3530150 .functor AND 1, L_0x5635a3530530, L_0x5635a3530660, C4<1>, C4<1>;
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v0x5635a3501500_0 .net "A", 0 0, L_0x5635a3530530; alias, 1 drivers
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v0x5635a34ffa60_0 .net "B", 0 0, L_0x5635a3530660; alias, 1 drivers
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v0x5635a34fdfe0_0 .net "CarryOut", 0 0, L_0x5635a3530150; alias, 1 drivers
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v0x5635a3501270_0 .net "Sum", 0 0, L_0x5635a3530040; alias, 1 drivers
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S_0x5635a352cf90 .scope module, "h2" "halfadder" 4 9, 5 1 0, S_0x5635a350d050;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "Sum";
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.port_info 3 /OUTPUT 1 "CarryOut";
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L_0x5635a3530230 .functor XOR 1, L_0x5635a3530040, L_0x5635a3530790, C4<0>, C4<0>;
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L_0x5635a35303c0 .functor AND 1, L_0x5635a3530040, L_0x5635a3530790, C4<1>, C4<1>;
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v0x5635a34ff7d0_0 .net "A", 0 0, L_0x5635a3530040; alias, 1 drivers
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v0x5635a34fdcf0_0 .net "B", 0 0, L_0x5635a3530790; alias, 1 drivers
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v0x5635a352d190_0 .net "CarryOut", 0 0, L_0x5635a35303c0; alias, 1 drivers
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v0x5635a352d260_0 .net "Sum", 0 0, L_0x5635a3530230; alias, 1 drivers
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S_0x5635a352da80 .scope module, "f2" "fulladder" 3 11, 4 1 0, S_0x5635a350cec0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /INPUT 1 "CarryIn";
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.port_info 3 /OUTPUT 1 "Sum";
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.port_info 4 /OUTPUT 1 "CarryOut";
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L_0x5635a3530c30 .functor OR 1, L_0x5635a3530930, L_0x5635a3530b50, C4<0>, C4<0>;
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v0x5635a352e800_0 .net "A", 0 0, L_0x5635a3530cc0; 1 drivers
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v0x5635a352e8c0_0 .net "ABandCIn", 0 0, L_0x5635a3530b50; 1 drivers
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v0x5635a352e990_0 .net "AandB", 0 0, L_0x5635a3530930; 1 drivers
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v0x5635a352ea90_0 .net "AxorB", 0 0, L_0x5635a35308c0; 1 drivers
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v0x5635a352eb80_0 .net "B", 0 0, L_0x5635a3530ec0; 1 drivers
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v0x5635a352ec70_0 .net "CarryIn", 0 0, L_0x5635a3531080; 1 drivers
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v0x5635a352ed10_0 .net "CarryOut", 0 0, L_0x5635a3530c30; 1 drivers
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v0x5635a352edb0_0 .net "Sum", 0 0, L_0x5635a35309c0; 1 drivers
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S_0x5635a352dc60 .scope module, "h1" "halfadder" 4 8, 5 1 0, S_0x5635a352da80;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "Sum";
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.port_info 3 /OUTPUT 1 "CarryOut";
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L_0x5635a35308c0 .functor XOR 1, L_0x5635a3530cc0, L_0x5635a3530ec0, C4<0>, C4<0>;
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L_0x5635a3530930 .functor AND 1, L_0x5635a3530cc0, L_0x5635a3530ec0, C4<1>, C4<1>;
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v0x5635a352de70_0 .net "A", 0 0, L_0x5635a3530cc0; alias, 1 drivers
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v0x5635a352df50_0 .net "B", 0 0, L_0x5635a3530ec0; alias, 1 drivers
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v0x5635a352e010_0 .net "CarryOut", 0 0, L_0x5635a3530930; alias, 1 drivers
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v0x5635a352e0e0_0 .net "Sum", 0 0, L_0x5635a35308c0; alias, 1 drivers
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S_0x5635a352e250 .scope module, "h2" "halfadder" 4 9, 5 1 0, S_0x5635a352da80;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "Sum";
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.port_info 3 /OUTPUT 1 "CarryOut";
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L_0x5635a35309c0 .functor XOR 1, L_0x5635a35308c0, L_0x5635a3531080, C4<0>, C4<0>;
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L_0x5635a3530b50 .functor AND 1, L_0x5635a35308c0, L_0x5635a3531080, C4<1>, C4<1>;
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v0x5635a352e450_0 .net "A", 0 0, L_0x5635a35308c0; alias, 1 drivers
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v0x5635a352e520_0 .net "B", 0 0, L_0x5635a3531080; alias, 1 drivers
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v0x5635a352e5c0_0 .net "CarryOut", 0 0, L_0x5635a3530b50; alias, 1 drivers
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v0x5635a352e690_0 .net "Sum", 0 0, L_0x5635a35309c0; alias, 1 drivers
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S_0x5635a352eeb0 .scope module, "h1" "halfadder" 3 9, 5 1 0, S_0x5635a350cec0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "Sum";
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.port_info 3 /OUTPUT 1 "CarryOut";
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L_0x5635a352fc20 .functor XOR 1, L_0x5635a352fe60, L_0x5635a352ff50, C4<0>, C4<0>;
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L_0x5635a352fd20 .functor AND 1, L_0x5635a352fe60, L_0x5635a352ff50, C4<1>, C4<1>;
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v0x5635a352f0c0_0 .net "A", 0 0, L_0x5635a352fe60; 1 drivers
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v0x5635a352f160_0 .net "B", 0 0, L_0x5635a352ff50; 1 drivers
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v0x5635a352f220_0 .net "CarryOut", 0 0, L_0x5635a352fd20; 1 drivers
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v0x5635a352f2f0_0 .net "Sum", 0 0, L_0x5635a352fc20; 1 drivers
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.scope S_0x5635a3500ed0;
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T_0 ;
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%vpi_call 2 14 "$dumpfile", "bit3Adder.vcd" {0 0 0};
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%vpi_call 2 15 "$dumpvars" {0 0 0};
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%pushi/vec4 0, 0, 3;
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%store/vec4 v0x5635a352f990_0, 0, 3;
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%pushi/vec4 0, 0, 3;
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%store/vec4 v0x5635a352fa50_0, 0, 3;
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%delay 10, 0;
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%pushi/vec4 0, 0, 3;
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%store/vec4 v0x5635a352f990_0, 0, 3;
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%pushi/vec4 1, 0, 3;
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%store/vec4 v0x5635a352fa50_0, 0, 3;
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%delay 10, 0;
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%pushi/vec4 1, 0, 3;
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%store/vec4 v0x5635a352f990_0, 0, 3;
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%pushi/vec4 1, 0, 3;
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%store/vec4 v0x5635a352fa50_0, 0, 3;
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%delay 10, 0;
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%pushi/vec4 2, 0, 3;
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%store/vec4 v0x5635a352f990_0, 0, 3;
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%pushi/vec4 2, 0, 3;
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%store/vec4 v0x5635a352fa50_0, 0, 3;
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%delay 10, 0;
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%pushi/vec4 2, 0, 3;
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%store/vec4 v0x5635a352f990_0, 0, 3;
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%pushi/vec4 3, 0, 3;
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%store/vec4 v0x5635a352fa50_0, 0, 3;
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%delay 10, 0;
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%pushi/vec4 6, 0, 3;
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%store/vec4 v0x5635a352f990_0, 0, 3;
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%pushi/vec4 2, 0, 3;
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%store/vec4 v0x5635a352fa50_0, 0, 3;
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%delay 10, 0;
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%pushi/vec4 5, 0, 3;
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%store/vec4 v0x5635a352f990_0, 0, 3;
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%pushi/vec4 4, 0, 3;
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%store/vec4 v0x5635a352fa50_0, 0, 3;
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%delay 10, 0;
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%pushi/vec4 7, 0, 3;
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%store/vec4 v0x5635a352f990_0, 0, 3;
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%pushi/vec4 4, 0, 3;
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%store/vec4 v0x5635a352fa50_0, 0, 3;
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%delay 10, 0;
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%pushi/vec4 7, 0, 3;
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%store/vec4 v0x5635a352f990_0, 0, 3;
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%pushi/vec4 6, 0, 3;
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%store/vec4 v0x5635a352fa50_0, 0, 3;
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%delay 10, 0;
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%pushi/vec4 7, 0, 3;
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%store/vec4 v0x5635a352f990_0, 0, 3;
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%pushi/vec4 7, 0, 3;
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%store/vec4 v0x5635a352fa50_0, 0, 3;
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%delay 10, 0;
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%vpi_call 2 26 "$finish" {0 0 0};
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%end;
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.thread T_0;
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# The file index is used to find the file name in the following table.
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:file_names 6;
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"N/A";
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"<interactive>";
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"bit3AdderTB.v";
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"bit3Adder.v";
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"fulladder.v";
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"halfadder.v";
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13
iverilog/tobb/lab3/bit3Adder.v
Normal file
13
iverilog/tobb/lab3/bit3Adder.v
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module bit3Adder (
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input [2:0] A,
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input [2:0] B,
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output [3:0] Sum
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);
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wire [2:0] Carry3;
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halfadder h1(.A(A[0]), .B(B[0]), .Sum(Sum[0]), .CarryOut(Carry3[0]));
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fulladder f1(.A(A[1]), .B(B[1]), .CarryIn(Carry3[0]), .Sum(Sum[1]), .CarryOut(Carry3[1]));
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fulladder f2(.A(A[2]), .B(B[2]), .CarryIn(Carry3[1]), .Sum(Sum[2]), .CarryOut(Sum[3]));
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endmodule
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212
iverilog/tobb/lab3/bit3Adder.vcd
Normal file
212
iverilog/tobb/lab3/bit3Adder.vcd
Normal file
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$date
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Thu Dec 12 01:03:03 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module bit3AdderTB $end
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$var wire 4 ! Sum [3:0] $end
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$var reg 3 " A [2:0] $end
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$var reg 3 # B [2:0] $end
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$scope module uut $end
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$var wire 3 $ A [2:0] $end
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$var wire 3 % B [2:0] $end
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$var wire 4 & Sum [3:0] $end
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$var wire 3 ' Carry3 [2:0] $end
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$scope module f1 $end
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$var wire 1 ( A $end
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$var wire 1 ) B $end
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$var wire 1 * CarryIn $end
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$var wire 1 + CarryOut $end
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$var wire 1 , Sum $end
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$var wire 1 - AxorB $end
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$var wire 1 . AandB $end
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$var wire 1 / ABandCIn $end
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$scope module h1 $end
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$var wire 1 ( A $end
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$var wire 1 ) B $end
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$var wire 1 . CarryOut $end
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$var wire 1 - Sum $end
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$upscope $end
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$scope module h2 $end
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$var wire 1 - A $end
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$var wire 1 * B $end
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$var wire 1 / CarryOut $end
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$var wire 1 , Sum $end
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$upscope $end
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$upscope $end
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$scope module f2 $end
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$var wire 1 0 A $end
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$var wire 1 1 B $end
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$var wire 1 2 CarryIn $end
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$var wire 1 3 CarryOut $end
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$var wire 1 4 Sum $end
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$var wire 1 5 AxorB $end
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$var wire 1 6 AandB $end
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$var wire 1 7 ABandCIn $end
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$scope module h1 $end
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$var wire 1 0 A $end
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$var wire 1 1 B $end
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$var wire 1 6 CarryOut $end
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$var wire 1 5 Sum $end
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$upscope $end
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$scope module h2 $end
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$var wire 1 5 A $end
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$var wire 1 2 B $end
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$var wire 1 7 CarryOut $end
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$var wire 1 4 Sum $end
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$upscope $end
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$upscope $end
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$scope module h1 $end
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$var wire 1 8 A $end
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$var wire 1 9 B $end
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$var wire 1 : CarryOut $end
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$var wire 1 ; Sum $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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0;
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0:
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09
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08
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07
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06
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05
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04
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03
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02
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01
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00
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0/
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0.
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0-
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0,
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0+
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0*
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0)
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0(
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bz00 '
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b0 &
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b0 %
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b0 $
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b0 #
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b0 "
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b0 !
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$end
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#10
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b1 !
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b1 &
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1;
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19
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b1 #
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b1 %
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#20
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1,
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1*
|
||||
b10 !
|
||||
b10 &
|
||||
0;
|
||||
bz01 '
|
||||
1:
|
||||
18
|
||||
b1 "
|
||||
b1 $
|
||||
#30
|
||||
14
|
||||
b100 !
|
||||
b100 &
|
||||
0,
|
||||
12
|
||||
0*
|
||||
1+
|
||||
bz10 '
|
||||
0:
|
||||
1.
|
||||
09
|
||||
1)
|
||||
08
|
||||
1(
|
||||
b10 #
|
||||
b10 %
|
||||
b10 "
|
||||
b10 $
|
||||
#40
|
||||
b101 !
|
||||
b101 &
|
||||
1;
|
||||
19
|
||||
b11 #
|
||||
b11 %
|
||||
#50
|
||||
13
|
||||
04
|
||||
17
|
||||
b1000 !
|
||||
b1000 &
|
||||
0;
|
||||
15
|
||||
09
|
||||
10
|
||||
b10 #
|
||||
b10 %
|
||||
b110 "
|
||||
b110 $
|
||||
#60
|
||||
02
|
||||
04
|
||||
07
|
||||
bz00 '
|
||||
0+
|
||||
05
|
||||
16
|
||||
b1001 !
|
||||
b1001 &
|
||||
1;
|
||||
0.
|
||||
0)
|
||||
11
|
||||
18
|
||||
0(
|
||||
b100 #
|
||||
b100 %
|
||||
b101 "
|
||||
b101 $
|
||||
#70
|
||||
b1011 !
|
||||
b1011 &
|
||||
1,
|
||||
1-
|
||||
1(
|
||||
b111 "
|
||||
b111 $
|
||||
#80
|
||||
14
|
||||
12
|
||||
b1101 !
|
||||
b1101 &
|
||||
0,
|
||||
bz10 '
|
||||
1+
|
||||
0-
|
||||
1.
|
||||
1)
|
||||
b110 #
|
||||
b110 %
|
||||
#90
|
||||
1,
|
||||
1*
|
||||
b1110 !
|
||||
b1110 &
|
||||
0;
|
||||
bz11 '
|
||||
1:
|
||||
19
|
||||
b111 #
|
||||
b111 %
|
||||
#100
|
||||
29
iverilog/tobb/lab3/bit3AdderTB.v
Normal file
29
iverilog/tobb/lab3/bit3AdderTB.v
Normal file
@ -0,0 +1,29 @@
|
||||
module bit3AdderTB();
|
||||
|
||||
reg [2:0] A;
|
||||
reg [2:0] B;
|
||||
wire [3:0] Sum;
|
||||
|
||||
bit3Adder uut (
|
||||
.A(A),
|
||||
.B(B),
|
||||
.Sum(Sum)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("bit3Adder.vcd");
|
||||
$dumpvars;
|
||||
A = 3'b000; B = 3'b000; #10;
|
||||
A = 3'b000; B = 3'b001; #10;
|
||||
A = 3'b001; B = 3'b001; #10;
|
||||
A = 3'b010; B = 3'b010; #10;
|
||||
A = 3'b010; B = 3'b011; #10;
|
||||
A = 3'b110; B = 3'b010; #10;
|
||||
A = 3'b101; B = 3'b100; #10;
|
||||
A = 3'b111; B = 3'b100; #10;
|
||||
A = 3'b111; B = 3'b110; #10;
|
||||
A = 3'b111; B = 3'b111; #10;
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
126
iverilog/tobb/lab3/fulladder
Normal file
126
iverilog/tobb/lab3/fulladder
Normal file
@ -0,0 +1,126 @@
|
||||
#! /usr/bin/vvp
|
||||
:ivl_version "11.0 (stable)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||
S_0x5596b8f24c90 .scope module, "fulladderTB" "fulladderTB" 2 1;
|
||||
.timescale 0 0;
|
||||
v0x5596b8f38c50_0 .var "A", 0 0;
|
||||
v0x5596b8f38d40_0 .var "B", 0 0;
|
||||
v0x5596b8f38e50_0 .var "CarryIn", 0 0;
|
||||
v0x5596b8f38f40_0 .net "CarryOut", 0 0, L_0x5596b8f394b0; 1 drivers
|
||||
v0x5596b8f38fe0_0 .net "Sum", 0 0, L_0x5596b8f39250; 1 drivers
|
||||
S_0x5596b8f24e20 .scope module, "uut" "fulladder" 2 6, 3 1 0, S_0x5596b8f24c90;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "CarryIn";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryOut";
|
||||
L_0x5596b8f394b0 .functor OR 1, L_0x5596b8f39190, L_0x5596b8f39390, C4<0>, C4<0>;
|
||||
v0x5596b8f385a0_0 .net "A", 0 0, v0x5596b8f38c50_0; 1 drivers
|
||||
v0x5596b8f38660_0 .net "ABandCIn", 0 0, L_0x5596b8f39390; 1 drivers
|
||||
v0x5596b8f38730_0 .net "AandB", 0 0, L_0x5596b8f39190; 1 drivers
|
||||
v0x5596b8f38830_0 .net "AxorB", 0 0, L_0x5596b8f39120; 1 drivers
|
||||
v0x5596b8f38920_0 .net "B", 0 0, v0x5596b8f38d40_0; 1 drivers
|
||||
v0x5596b8f38a10_0 .net "CarryIn", 0 0, v0x5596b8f38e50_0; 1 drivers
|
||||
v0x5596b8f38ab0_0 .net "CarryOut", 0 0, L_0x5596b8f394b0; alias, 1 drivers
|
||||
v0x5596b8f38b50_0 .net "Sum", 0 0, L_0x5596b8f39250; alias, 1 drivers
|
||||
S_0x5596b8f1ff80 .scope module, "h1" "halfadder" 3 8, 4 1 0, S_0x5596b8f24e20;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "CarryOut";
|
||||
L_0x5596b8f39120 .functor XOR 1, v0x5596b8f38c50_0, v0x5596b8f38d40_0, C4<0>, C4<0>;
|
||||
L_0x5596b8f39190 .functor AND 1, v0x5596b8f38c50_0, v0x5596b8f38d40_0, C4<1>, C4<1>;
|
||||
v0x5596b8f20200_0 .net "A", 0 0, v0x5596b8f38c50_0; alias, 1 drivers
|
||||
v0x5596b8f37c80_0 .net "B", 0 0, v0x5596b8f38d40_0; alias, 1 drivers
|
||||
v0x5596b8f37d40_0 .net "CarryOut", 0 0, L_0x5596b8f39190; alias, 1 drivers
|
||||
v0x5596b8f37e10_0 .net "Sum", 0 0, L_0x5596b8f39120; alias, 1 drivers
|
||||
S_0x5596b8f37f80 .scope module, "h2" "halfadder" 3 9, 4 1 0, S_0x5596b8f24e20;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "CarryOut";
|
||||
L_0x5596b8f39250 .functor XOR 1, L_0x5596b8f39120, v0x5596b8f38e50_0, C4<0>, C4<0>;
|
||||
L_0x5596b8f39390 .functor AND 1, L_0x5596b8f39120, v0x5596b8f38e50_0, C4<1>, C4<1>;
|
||||
v0x5596b8f381f0_0 .net "A", 0 0, L_0x5596b8f39120; alias, 1 drivers
|
||||
v0x5596b8f382c0_0 .net "B", 0 0, v0x5596b8f38e50_0; alias, 1 drivers
|
||||
v0x5596b8f38360_0 .net "CarryOut", 0 0, L_0x5596b8f39390; alias, 1 drivers
|
||||
v0x5596b8f38430_0 .net "Sum", 0 0, L_0x5596b8f39250; alias, 1 drivers
|
||||
.scope S_0x5596b8f24c90;
|
||||
T_0 ;
|
||||
%vpi_call 2 15 "$dumpfile", "fulladder.vcd" {0 0 0};
|
||||
%vpi_call 2 16 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5596b8f38c50_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5596b8f38d40_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5596b8f38e50_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5596b8f38c50_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5596b8f38d40_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5596b8f38e50_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5596b8f38c50_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5596b8f38d40_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5596b8f38e50_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5596b8f38c50_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5596b8f38d40_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5596b8f38e50_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5596b8f38c50_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5596b8f38d40_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5596b8f38e50_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5596b8f38c50_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5596b8f38d40_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5596b8f38e50_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5596b8f38c50_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5596b8f38d40_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5596b8f38e50_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5596b8f38c50_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5596b8f38d40_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5596b8f38e50_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 25 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 5;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"fulladderTB.v";
|
||||
"fulladder.v";
|
||||
"halfadder.v";
|
||||
13
iverilog/tobb/lab3/fulladder.v
Normal file
13
iverilog/tobb/lab3/fulladder.v
Normal file
@ -0,0 +1,13 @@
|
||||
module fulladder (
|
||||
input A, B, CarryIn,
|
||||
output Sum, CarryOut
|
||||
);
|
||||
|
||||
wire AandB, AxorB, ABandCIn;
|
||||
|
||||
halfadder h1 (.A(A),.B(B),.Sum(AxorB), .CarryOut(AandB));
|
||||
halfadder h2 (.A(AxorB), .B(CarryIn), .Sum(Sum), .CarryOut(ABandCIn));
|
||||
|
||||
or o1 (CarryOut, AandB, ABandCIn);
|
||||
|
||||
endmodule
|
||||
84
iverilog/tobb/lab3/fulladder.vcd
Normal file
84
iverilog/tobb/lab3/fulladder.vcd
Normal file
@ -0,0 +1,84 @@
|
||||
$date
|
||||
Thu Dec 12 00:41:38 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module fulladderTB $end
|
||||
$var wire 1 ! Sum $end
|
||||
$var wire 1 " CarryOut $end
|
||||
$var reg 1 # A $end
|
||||
$var reg 1 $ B $end
|
||||
$var reg 1 % CarryIn $end
|
||||
$scope module uut $end
|
||||
$var wire 1 # A $end
|
||||
$var wire 1 $ B $end
|
||||
$var wire 1 % CarryIn $end
|
||||
$var wire 1 " CarryOut $end
|
||||
$var wire 1 ! Sum $end
|
||||
$var wire 1 & AxorB $end
|
||||
$var wire 1 ' AandB $end
|
||||
$var wire 1 ( ABandCIn $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 # A $end
|
||||
$var wire 1 $ B $end
|
||||
$var wire 1 ' CarryOut $end
|
||||
$var wire 1 & Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 & A $end
|
||||
$var wire 1 % B $end
|
||||
$var wire 1 ( CarryOut $end
|
||||
$var wire 1 ! Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
0(
|
||||
0'
|
||||
0&
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
0"
|
||||
0!
|
||||
$end
|
||||
#10
|
||||
1!
|
||||
1%
|
||||
#20
|
||||
1&
|
||||
0%
|
||||
1$
|
||||
#30
|
||||
1"
|
||||
0!
|
||||
1(
|
||||
1%
|
||||
#40
|
||||
0"
|
||||
1!
|
||||
0(
|
||||
0%
|
||||
0$
|
||||
1#
|
||||
#50
|
||||
1"
|
||||
0!
|
||||
1(
|
||||
1%
|
||||
#60
|
||||
0(
|
||||
0&
|
||||
1'
|
||||
0%
|
||||
1$
|
||||
#70
|
||||
1!
|
||||
1%
|
||||
#80
|
||||
28
iverilog/tobb/lab3/fulladderTB.v
Normal file
28
iverilog/tobb/lab3/fulladderTB.v
Normal file
@ -0,0 +1,28 @@
|
||||
module fulladderTB();
|
||||
|
||||
reg A, B, CarryIn;
|
||||
wire Sum, CarryOut;
|
||||
|
||||
fulladder uut(
|
||||
.A(A),
|
||||
.B(B),
|
||||
.CarryIn(CarryIn),
|
||||
.Sum(Sum),
|
||||
.CarryOut(CarryOut)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("fulladder.vcd");
|
||||
$dumpvars;
|
||||
A = 1'b0; B = 1'b0; CarryIn = 1'b0; #10;
|
||||
A = 1'b0; B = 1'b0; CarryIn = 1'b1; #10;
|
||||
A = 1'b0; B = 1'b1; CarryIn = 1'b0; #10;
|
||||
A = 1'b0; B = 1'b1; CarryIn = 1'b1; #10;
|
||||
A = 1'b1; B = 1'b0; CarryIn = 1'b0; #10;
|
||||
A = 1'b1; B = 1'b0; CarryIn = 1'b1; #10;
|
||||
A = 1'b1; B = 1'b1; CarryIn = 1'b0; #10;
|
||||
A = 1'b1; B = 1'b1; CarryIn = 1'b1; #10;
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
9
iverilog/tobb/lab3/halfadder.v
Normal file
9
iverilog/tobb/lab3/halfadder.v
Normal file
@ -0,0 +1,9 @@
|
||||
module halfadder (
|
||||
input A, B,
|
||||
output Sum, CarryOut
|
||||
);
|
||||
|
||||
xor xor1(Sum, A, B);
|
||||
and and1(CarryOut, A, B);
|
||||
|
||||
endmodule
|
||||
Loading…
x
Reference in New Issue
Block a user