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verilog

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This commit is contained in:
k0rrluna 2024-05-07 16:15:21 +03:00
parent ed465dd690
commit 492a55d360
44 changed files with 11289 additions and 194 deletions
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44
lab3/impl/gwsynthesis/lab3.log
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@ -1,23 +1,27 @@
GowinSynthesis start
Running parser ...
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v'
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v'
ERROR (EX3615) : '.name implicit port connection' is not allowed in this dialect, use SystemVerilog mode instead("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":7)
ERROR (EX3863) : Syntax error near '['("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":7)
ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
Sorry, too many errors..
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v'
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v'
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v'
Compiling module 'mult2bit'("C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v":1)
Compiling module 'halfAdder'("C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v":1)
NOTE (EX0101) : Current top module is "mult2bit"
[5%] Running netlist conversion ...
Running device independent optimization ...
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg" completed
[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3_syn.rpt.html" completed
GowinSynthesis finish

5
lab3/impl/gwsynthesis/lab3.prj
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@ -4,8 +4,9 @@
<Version>beta</Version>
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
<FileList>
<File path="C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v" type="verilog"/>
<File path="C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v" type="verilog"/>
<File path="C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v" type="verilog"/>
<File path="C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v" type="verilog"/>
<File path="C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v" type="verilog"/>
</FileList>
<OptionList>
<Option type="disable_insert_pad" value="0"/>

195
lab3/impl/gwsynthesis/lab3.vg
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@ -1,118 +1,137 @@
//
//Written by GowinSynthesis
//Tool Version "V1.9.9.02"
//Sat Apr 13 05:09:20 2024
//Sat May 4 01:07:38 2024
//Source file index table:
//file0 "\C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v"
//file0 "\C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v"
//file1 "\C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v"
//file2 "\C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v"
`timescale 100 ps/100 ps
module Adder3Bit (
num1,
num2,
Carry,
sum
module halfAdder (
A_d,
B_d,
C_d
)
;
input [2:0] num1;
input [2:0] num2;
output [2:0] Carry;
output [2:0] sum;
wire [2:0] num1_d;
wire [2:0] num2_d;
wire [2:0] sum_d;
wire [2:0] Carry_d;
input [1:0] A_d;
input [1:0] B_d;
output [1:1] C_d;
wire VCC;
wire GND;
IBUF num1_0_ibuf (
.O(num1_d[0]),
.I(num1[0])
LUT4 C_d_1_s (
.F(C_d[1]),
.I0(A_d[1]),
.I1(B_d[0]),
.I2(A_d[0]),
.I3(B_d[1])
);
IBUF num1_1_ibuf (
.O(num1_d[1]),
.I(num1[1])
defparam C_d_1_s.INIT=16'h7888;
VCC VCC_cZ (
.V(VCC)
);
IBUF num1_2_ibuf (
.O(num1_d[2]),
.I(num1[2])
GND GND_cZ (
.G(GND)
);
IBUF num2_0_ibuf (
.O(num2_d[0]),
.I(num2[0])
endmodule /* halfAdder */
module halfAdder_0 (
A_d,
B_d,
C_d
)
;
input [1:0] A_d;
input [1:0] B_d;
output [3:2] C_d;
wire VCC;
wire GND;
LUT4 C_d_3_s (
.F(C_d[3]),
.I0(A_d[0]),
.I1(B_d[0]),
.I2(A_d[1]),
.I3(B_d[1])
);
IBUF num2_1_ibuf (
.O(num2_d[1]),
.I(num2[1])
defparam C_d_3_s.INIT=16'h7000;
LUT4 C_d_2_s (
.F(C_d[2]),
.I0(A_d[1]),
.I1(B_d[0]),
.I2(A_d[0]),
.I3(B_d[1])
);
IBUF num2_2_ibuf (
.O(num2_d[2]),
.I(num2[2])
defparam C_d_2_s.INIT=16'h8000;
VCC VCC_cZ (
.V(VCC)
);
OBUF Carry_0_obuf (
.O(Carry[0]),
.I(Carry_d[0])
GND GND_cZ (
.G(GND)
);
OBUF Carry_1_obuf (
.O(Carry[1]),
.I(Carry_d[1])
endmodule /* halfAdder_0 */
module mult2bit (
A,
B,
C
)
;
input [1:0] A;
input [1:0] B;
output [3:0] C;
wire [1:0] A_d;
wire [1:0] B_d;
wire [0:0] C_d;
wire [1:1] C_d_0;
wire [3:2] C_d_1;
wire VCC;
wire GND;
IBUF A_0_ibuf (
.O(A_d[0]),
.I(A[0])
);
OBUF Carry_2_obuf (
.O(Carry[2]),
.I(Carry_d[2])
IBUF A_1_ibuf (
.O(A_d[1]),
.I(A[1])
);
OBUF sum_0_obuf (
.O(sum[0]),
.I(sum_d[0])
IBUF B_0_ibuf (
.O(B_d[0]),
.I(B[0])
);
OBUF sum_1_obuf (
.O(sum[1]),
.I(sum_d[1])
IBUF B_1_ibuf (
.O(B_d[1]),
.I(B[1])
);
OBUF sum_2_obuf (
.O(sum[2]),
.I(sum_d[2])
OBUF C_0_obuf (
.O(C[0]),
.I(C_d[0])
);
LUT2 sum_d_0_s (
.F(sum_d[0]),
.I0(num1_d[0]),
.I1(num2_d[0])
OBUF C_1_obuf (
.O(C[1]),
.I(C_d_0[1])
);
defparam sum_d_0_s.INIT=4'h6;
LUT2 Carry_d_0_s (
.F(Carry_d[0]),
.I0(num1_d[0]),
.I1(num2_d[0])
OBUF C_2_obuf (
.O(C[2]),
.I(C_d_1[2])
);
defparam Carry_d_0_s.INIT=4'h8;
LUT4 Carry_d_1_s (
.F(Carry_d[1]),
.I0(num1_d[1]),
.I1(num2_d[1]),
.I2(num1_d[0]),
.I3(num2_d[0])
OBUF C_3_obuf (
.O(C[3]),
.I(C_d_1[3])
);
defparam Carry_d_1_s.INIT=16'hE888;
LUT3 sum_d_2_s (
.F(sum_d[2]),
.I0(Carry_d[1]),
.I1(num1_d[2]),
.I2(num2_d[2])
LUT2 C_d_0_s (
.F(C_d[0]),
.I0(B_d[0]),
.I1(A_d[0])
);
defparam sum_d_2_s.INIT=8'h96;
LUT3 Carry_d_2_s (
.F(Carry_d[2]),
.I0(Carry_d[1]),
.I1(num1_d[2]),
.I2(num2_d[2])
defparam C_d_0_s.INIT=4'h8;
halfAdder h0 (
.A_d(A_d[1:0]),
.B_d(B_d[1:0]),
.C_d(C_d_0[1])
);
defparam Carry_d_2_s.INIT=8'hE8;
LUT4 sum_d_1_s0 (
.F(sum_d[1]),
.I0(num1_d[0]),
.I1(num2_d[0]),
.I2(num1_d[1]),
.I3(num2_d[1])
halfAdder_0 h1 (
.A_d(A_d[1:0]),
.B_d(B_d[1:0]),
.C_d(C_d_1[3:2])
);
defparam sum_d_1_s0.INIT=16'h8778;
VCC VCC_cZ (
.V(VCC)
);
@ -122,4 +141,4 @@ defparam sum_d_1_s0.INIT=16'h8778;
GSR GSR (
.GSRI(VCC)
);
endmodule /* Adder3Bit */
endmodule /* mult2bit */

32
lab3/impl/gwsynthesis/lab3_syn.rpt.html
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@ -48,7 +48,9 @@ table.detail_table td.label { min-width: 100px; width: 8%;}
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v<br>
<td>C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v<br>
C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v<br>
C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v<br>
</td>
</tr>
<tr>
@ -73,7 +75,7 @@ table.detail_table td.label { min-width: 100px; width: 8%;}
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sat Apr 13 05:09:20 2024
<td>Sat May 4 01:07:38 2024
</td>
</tr>
<tr>
@ -85,15 +87,15 @@ table.detail_table td.label { min-width: 100px; width: 8%;}
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>Adder3Bit</td>
<td>mult2bit</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.093s, Peak memory usage = 156.254MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 156.254MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 156.254MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 156.254MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 156.254MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 156.254MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 156.254MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.301s, Peak memory usage = 172.207MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 172.207MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 172.207MB<br/></td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.134s, Peak memory usage = 417.762MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.308s, Peak memory usage = 417.762MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 417.762MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.483s, Peak memory usage = 172.207MB</td>
<td>CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.447s, Peak memory usage = 417.762MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
@ -105,35 +107,31 @@ table.detail_table td.label { min-width: 100px; width: 8%;}
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>12</td>
<td>8</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>12</td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>6</td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>6</td>
<td>4</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>6</td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>2</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>2</td>
<td>3</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
@ -145,7 +143,7 @@ table.detail_table td.label { min-width: 100px; width: 8%;}
</tr>
<tr>
<td class="label">Logic</td>
<td>6(6 LUT, 0 ALU) / 20736</td>
<td>4(4 LUT, 0 ALU) / 20736</td>
<td><1%</td>
</tr>
<tr>

24
lab3/impl/gwsynthesis/lab3_syn_resource.html
View File

@ -30,10 +30,30 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
<th class="label">ROM16 NUMBER</th>
</tr>
<tr>
<td class="label">Adder3Bit (C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v)</td>
<td class="label">mult2bit (C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">6</td>
<td align = "center">1</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp|--h0
(C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">1</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp|--h1
(C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">2</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>

5
lab3/impl/gwsynthesis/lab3_syn_rsc.xml
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@ -1,2 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<Module name="Adder3Bit" Lut="6" T_Lut="6(6)"/>
<Module name="mult2bit" Lut="1" T_Lut="4(1)">
<SubModule name="h0" Lut="1" T_Lut="1(1)"/>
<SubModule name="h1" Lut="2" T_Lut="2(2)"/>
</Module>

12
lab3/impl/pnr/cmd.do Normal file
View File

@ -0,0 +1,12 @@
-d C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg
-p GW2A-18C-PBGA256-8
-pn GW2A-LV18PG256C8/I7
-cfg C:\cygwin64\home\koray\verilog\lab3\impl\pnr\device.cfg
-bit
-tr
-ph
-timing
-cst_error
-correct_hold 1
-route_maxfan 23
-global_freq 100.000

21
lab3/impl/pnr/device.cfg Normal file
View File

@ -0,0 +1,21 @@
set JTAG regular_io = false
set SSPI regular_io = false
set MSPI regular_io = false
set READY regular_io = false
set DONE regular_io = false
set I2C regular_io = false
set RECONFIG_N regular_io = false
set CRC_check = true
set compress = false
set encryption = false
set security_bit_enable = true
set bsram_init_fuse_print = true
set background_programming = off
set secure_mode = false
set program_done_bypass = false
set wake_up = 0
set format = binary
set power_on_reset_monitor = true
set multiboot_spi_flash_address = 0x00000000
set vccx = 3.3
set unused_pin = default

BIN
lab3/impl/pnr/lab3.bin Normal file
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BIN
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Reading netlist file: "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg"
Parsing netlist file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg" completed
Processing netlist completed
Running placement......
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
[30%] Placement Phase 2 completed
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "C:\cygwin64\home\koray\verilog\lab3\impl\pnr\lab3.power.html" completed
Generate file "C:\cygwin64\home\koray\verilog\lab3\impl\pnr\lab3.pin.html" completed
Generate file "C:\cygwin64\home\koray\verilog\lab3\impl\pnr\lab3.rpt.html" completed
Generate file "C:\cygwin64\home\koray\verilog\lab3\impl\pnr\lab3.rpt.txt" completed
Generate file "C:\cygwin64\home\koray\verilog\lab3\impl\pnr\lab3.tr.html" completed
Sat May 4 01:07:45 2024

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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//ENhttp://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Power Analysis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper { width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td {white-space:pre; border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.thermal_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.Configure_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table th.label { min-width: 8%; width: 8%; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#Message" style=" font-size: 16px;">Power Messages</a>
</li>
<li><a href="#Summary" style=" font-size: 16px;">Power Summary</a>
<ul>
<li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li>
<li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li>
<li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li>
<li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li>
</ul>
</li>
<li><a href="#Detail" style=" font-size: 16px;">Power Details</a>
<ul>
<li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li>
<li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li>
<li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="Message">Power Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Power Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.9.02</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sat May 4 01:07:45 2024
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Power Summary</a></h1>
<h2><a name="Power_Info">Power Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Total Power (mW)</td>
<td>92.439</td>
</tr>
<tr>
<td class="label">Quiescent Power (mW)</td>
<td>91.608</td>
</tr>
<tr>
<td class="label">Dynamic Power (mW)</td>
<td>0.832</td>
</tr>
</table>
<h2><a name="Thermal_Info">Thermal Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Junction Temperature</td>
<td>27.960</td>
</tr>
<tr>
<td class="label">Theta JA</td>
<td>32.020</td>
</tr>
<tr>
<td class="label">Max Allowed Ambient Temperature</td>
<td>82.040</td>
</tr>
</table>
<h2><a name="Configure_Info">Configure Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Default IO Toggle Rate</td>
<td>0.125</td>
</tr>
<td class="label">Default Remain Toggle Rate</td>
<td>0.125</td>
</tr>
<tr>
<td class="label">Use Vectorless Estimation</td>
<td>false</td>
</tr>
<tr>
<td class="label">Filter Glitches</td>
<td>false</td>
</tr>
<tr>
<td class="label">Related Vcd File</td>
<td></td>
</tr>
<tr>
<td class="label">Related Saif File</td>
<td></td>
</tr>
<tr>
<td class="label">Use Custom Theta JA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Air Flow</td>
<td>LFM_0</td>
</tr>
<tr>
<td class="label">Heat Sink</td>
<td>None</td>
</tr>
<tr>
<td class="label">Use Custom Theta SA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Board Thermal Model</td>
<td>None</td>
</tr>
<tr>
<td class="label">Use Custom Theta JB</td>
<td>false</td>
</tr>
<tr>
<td class="label">Ambient Temperature</td>
<td>25.000
</tr>
</table>
<h2><a name="Supply_Summary">Supply Information:</a></h2>
<table class="summary_table">
<tr>
<th class="label">Voltage Source</th>
<th class="label">Voltage</th>
<th class="label">Dynamic Current(mA)</th>
<th class="label">Quiescent Current(mA)</th>
<th class="label">Power(mW)</th>
</tr>
<tr>
<td>VCC</td>
<td>1.000</td>
<td>0.158</td>
<td>61.510</td>
<td>61.668</td>
</tr>
<tr>
<td>VCCX</td>
<td>2.500</td>
<td>0.158</td>
<td>11.364</td>
<td>28.803</td>
</tr>
<tr>
<td>VCCIO18</td>
<td>1.800</td>
<td>0.155</td>
<td>0.938</td>
<td>1.968</td>
</tr>
</table>
<h1><a name="Detail">Power Details</a></h1>
<h2><a name="By_Block_Type">Power By Block Type:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Block Type</th>
<th class="label">Total Power(mW)</th>
<th class="label">Static Power(mW)</th>
<th class="label">Average Toggle Rate(millions of transitions/sec)</th>
</tr>
<tr>
<td>IO</td>
<td>3.335
<td>2.503
<td>6.250
</tr>
</table>
<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Hierarchy Entity</th>
<th class="label">Total Power(mW)</th>
<th class="label">Block Dynamic Power(mW)</th>
</tr>
<tr>
<td>mult2bit</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>mult2bit/h0/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>mult2bit/h1/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
</table>
<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Domain</th>
<th class="label">Clock Frequency(Mhz)</th>
<th class="label">Total Dynamic Power(mW)</th>
</tr>
<tr>
<td>NO CLOCK DOMAIN</td>
<td>0.000</td>
<td>0.000</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
1. PnR Messages
<Report Title>: PnR Report
<Design File>: C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg
<Physical Constraints File>: ---
<Timing Constraints File>: ---
<Tool Version>: V1.9.9.02
<Part Number>: GW2A-LV18PG256C8/I7
<Device>: GW2A-18
<Device Version>: C
<Created Time>:Sat May 4 01:07:45 2024
2. PnR Details
Running placement:
Placement Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s
Placement Phase 1: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.545s
Placement Phase 2: CPU time = 0h 0m 0.005s, Elapsed time = 0h 0m 0.005s
Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Running routing:
Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Routing Phase 1: CPU time = 0h 0m 0.314s, Elapsed time = 0h 0m 0.314s
Routing Phase 2: CPU time = 0h 0m 0.152s, Elapsed time = 0h 0m 0.152s
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Total Routing: CPU time = 0h 0m 0.466s, Elapsed time = 0h 0m 0.466s
Generate output files:
CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
Total Time and Memory Usage: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 420MB
3. Resource Usage Summary
----------------------------------------------------------
Resources | Usage
----------------------------------------------------------
Logic | 4/20736 <1%
--LUT,ALU,ROM16 | 4(4 LUT, 0 ALU, 0 ROM16)
--SSRAM(RAM16) | 0
Register | 0/16173 0%
--Logic Register as Latch | 0/15552 0%
--Logic Register as FF | 0/15552 0%
--I/O Register as Latch | 0/621 0%
--I/O Register as FF | 0/621 0%
CLS | 3/10368 <1%
I/O Port | 8
I/O Buf | 8
--Input Buf | 4
--Output Buf | 4
--Inout Buf | 0
IOLOGIC | 0%
BSRAM | 0%
DSP | 0%
PLL | 0/4 0%
DCS | 0/8 0%
DQCE | 0/24 0%
OSC | 0/1 0%
CLKDIV | 0/8 0%
DLLDLY | 0/8 0%
DQS | 0/9 0%
DHCEN | 0/16 0%
==========================================================
4. I/O Bank Usage Summary
-----------------------
I/O Bank | Usage
-----------------------
bank 0 | 4/29(13%)
bank 1 | 0/20(0%)
bank 2 | 0/20(0%)
bank 3 | 0/32(0%)
bank 4 | 0/36(0%)
bank 5 | 0/36(0%)
bank 6 | 0/18(0%)
bank 7 | 4/16(25%)
=======================
5. Global Clock Usage Summary
-------------------------------
Global Clock | Usage
-------------------------------
PRIMARY | 0/8(0%)
LW | 0/8(0%)
GCLK_PIN | 0/8(0%)
PLL | 0/4(0%)
CLKDIV | 0/8(0%)
DLLDLY | 0/8(0%)
===============================
6. Global Clock Signals
-------------------------------------------
Signal | Global Clock | Location
-------------------------------------------
===========================================
7. Pinout by Port Name
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | BankVccio
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
A[0] | | A15/7 | N | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
A[1] | | L15/0 | N | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B[0] | | D16/0 | N | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B[1] | | B12/7 | N | in | IOL7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
C[0] | | E14/0 | N | out | IOT4[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
C[1] | | B14/7 | N | out | IOL2[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
C[2] | | C12/7 | N | out | IOL7[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
C[3] | | C16/0 | N | out | IOT5[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
==================================================================================================================================================================================================================
8. All Package Pins
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | Bank Vccio
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
L15/0 | A[1] | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D16/0 | B[0] | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E14/0 | C[0] | out | IOT4[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
C16/0 | C[3] | out | IOT5[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
D15/0 | - | in | IOT5[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E16/0 | - | in | IOT6[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F15/0 | - | in | IOT6[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F13/0 | - | in | IOT8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G12/0 | - | in | IOT8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F14/0 | - | in | IOT9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F16/0 | - | in | IOT9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F12/0 | - | in | IOT12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G13/0 | - | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G15/0 | - | in | IOT13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G14/0 | - | in | IOT13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G11/0 | - | in | IOT14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H12/0 | - | in | IOT14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G16/0 | - | in | IOT16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H15/0 | - | in | IOT16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H13/0 | - | in | IOT18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J12/0 | - | in | IOT18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H14/0 | - | in | IOT20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H16/0 | - | in | IOT20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J16/0 | - | in | IOT22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J14/0 | - | in | IOT22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J15/0 | - | in | IOT24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K16/0 | - | in | IOT24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H11/0 | - | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J13/0 | - | in | IOT27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K14/1 | - | in | IOT30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K15/1 | - | in | IOT30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J11/1 | - | in | IOT32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L12/1 | - | in | IOT32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L16/1 | - | in | IOT34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L14/1 | - | in | IOT34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K13/1 | - | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K12/1 | - | in | IOT36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K11/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L13/1 | - | in | IOT38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M14/1 | - | in | IOT40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M15/1 | - | in | IOT40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D14/1 | - | in | IOT44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E15/1 | - | in | IOT44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N15/1 | - | in | IOT48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P16/1 | - | in | IOT48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N16/1 | - | in | IOT52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N14/1 | - | in | IOT52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P15/1 | - | in | IOT54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R16/1 | - | in | IOT54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
A4/5 | - | in | IOB2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C5/5 | - | in | IOB2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D6/5 | - | in | IOB3[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E7/5 | - | in | IOB3[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A3/5 | - | in | IOB4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B4/5 | - | in | IOB4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A5/5 | - | in | IOB7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B6/5 | - | in | IOB7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B1/5 | - | in | IOB8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C2/5 | - | in | IOB8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D3/5 | - | in | IOB9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D1/5 | - | in | IOB9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E2/5 | - | in | IOB12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E3/5 | - | in | IOB12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B3/5 | - | in | IOB13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A2/5 | - | in | IOB13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C1/5 | - | in | IOB14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D2/5 | - | in | IOB14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E1/5 | - | in | IOB16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F2/5 | - | in | IOB16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F4/5 | - | in | IOB18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G6/5 | - | in | IOB18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F3/5 | - | in | IOB19[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F1/5 | - | in | IOB19[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G5/5 | - | in | IOB20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G4/5 | - | in | IOB20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G2/5 | - | in | IOB21[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G3/5 | - | in | IOB21[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F5/5 | - | in | IOB22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H6/5 | - | in | IOB22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G1/5 | - | in | IOB24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H2/5 | - | in | IOB24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H4/5 | - | in | IOB26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J6/5 | - | in | IOB26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J1/5 | - | in | IOB27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J3/5 | - | in | IOB27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L2/4 | - | in | IOB30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M1/4 | - | in | IOB30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H3/4 | - | in | IOB32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H1/4 | - | in | IOB32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J2/4 | - | in | IOB34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K1/4 | - | in | IOB34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H5/4 | - | in | IOB35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J4/4 | - | in | IOB35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K3/4 | - | in | IOB36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K2/4 | - | in | IOB36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J5/4 | - | in | IOB37[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K6/4 | - | in | IOB37[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L1/4 | - | in | IOB38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L3/4 | - | in | IOB38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K4/4 | - | in | IOB39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L5/4 | - | in | IOB39[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K5/4 | - | in | IOB40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L4/4 | - | in | IOB40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N2/4 | - | in | IOB41[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P1/4 | - | in | IOB41[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M3/4 | - | in | IOB42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N1/4 | - | in | IOB42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M2/4 | - | in | IOB43[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N3/4 | - | in | IOB43[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R1/4 | - | in | IOB44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P2/4 | - | in | IOB44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P4/4 | - | in | IOB45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T4/4 | - | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R3/4 | - | in | IOB48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T2/4 | - | in | IOB48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P5/4 | - | in | IOB50[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R5/4 | - | in | IOB50[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R4/4 | - | in | IOB52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T3/4 | - | in | IOB52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R6/4 | - | in | IOB54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T5/4 | - | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
B14/7 | C[1] | out | IOL2[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
A15/7 | A[0] | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
C12/7 | C[2] | out | IOL7[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
B12/7 | B[1] | in | IOL7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
B13/7 | - | in | IOL8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A14/7 | - | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F10/7 | - | in | IOL11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B11/7 | - | in | IOL13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A12/7 | - | in | IOL13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A11/7 | - | in | IOL15[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C11/7 | - | in | IOL15[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D10/7 | - | in | IOL17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E10/7 | - | in | IOL17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D11/7 | - | in | IOL22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A9/7 | - | in | IOL27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C9/7 | - | in | IOL27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C8/6 | - | in | IOL29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A8/6 | - | in | IOL29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F9/6 | - | in | IOL31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E11/6 | - | in | IOL31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B9/6 | - | in | IOL33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A10/6 | - | in | IOL33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F8/6 | - | in | IOL35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D9/6 | - | in | IOL35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D8/6 | - | in | IOL38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E9/6 | - | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B7/6 | - | in | IOL40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C7/6 | - | in | IOL40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F7/6 | - | in | IOL45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E8/6 | - | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C4/6 | - | in | IOL47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B5/6 | - | in | IOL47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E6/6 | - | in | IOL53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D7/6 | - | in | IOL53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
T15/2 | - | in | IOR7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R14/2 | - | in | IOR7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P12/2 | - | in | IOR8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T13/2 | - | in | IOR8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R12/2 | - | in | IOR11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P13/2 | - | in | IOR11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R11/2 | - | in | IOR17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T12/2 | - | in | IOR17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R13/2 | - | in | IOR20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T14/2 | - | in | IOR20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M10/2 | - | in | IOR22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N11/2 | - | in | IOR22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T11/2 | - | in | IOR24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P11/2 | - | in | IOR24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C6/2 | - | out | IOR25[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
B8/2 | - | in | IOR25[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A7/2 | - | in | IOR26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A6/2 | - | in | IOR26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N10/2 | - | in | IOR27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M11/2 | - | in | IOR27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T7/3 | - | in | IOR29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R8/3 | - | in | IOR29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M16/3 | - | in | IOR30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B16/3 | - | in | IOR30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C15/3 | - | in | IOR31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B10/3 | - | in | IOR31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A13/3 | - | in | IOR32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C13/3 | - | in | IOR32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P10/3 | - | in | IOR33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R10/3 | - | in | IOR33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M9/3 | - | in | IOR34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L10/3 | - | in | IOR34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R9/3 | - | in | IOR35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T10/3 | - | in | IOR35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M8/3 | - | in | IOR36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N9/3 | - | in | IOR36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T9/3 | - | in | IOR38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P9/3 | - | in | IOR38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C10/3 | - | in | IOR39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N8/3 | - | in | IOR40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L9/3 | - | in | IOR40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P8/3 | - | in | IOR42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T8/3 | - | in | IOR42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M6/3 | - | in | IOR44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L8/3 | - | in | IOR44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M7/3 | - | in | IOR47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N7/3 | - | in | IOR47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R7/3 | - | in | IOR49[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P7/3 | - | in | IOR49[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N6/3 | - | in | IOR51[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P6/3 | - | in | IOR53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T6/3 | - | in | IOR53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
====================================================================================================================================================================================

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<li><div class="triangle" onclick="onClick(this)"></div><a href="lab3_tr_content.html#Timing_Report_by_Analysis_Type" style=" font-size: 14px;" target="mainFrame">Timing Report By Analysis Type</a>
<ul>
<!--Setup_Analysis begin-->
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Setup_Analysis" style=" font-size: 13px;" target="mainFrame">Setup Analysis Report</a>
</li>
<!--Setup_Analysis end-->
<!--Hold_Analysis begin-->
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Hold_Analysis" style=" font-size: 13px;" target="mainFrame">Hold Analysis Report</a>
</li>
<!--Hold_Analysis end-->
<!--Recovery_Analysis begin-->
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Recovery_Analysis" style=" font-size: 13px;" target="mainFrame">Recovery Analysis Report</a>
</li>
<!--Recovery_Analysis end-->
<!--Removal_Analysis begin-->
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Removal_Analysis" style=" font-size: 13px;" target="mainFrame">Removal Analysis Report</a>
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<!--Removal_Analysis end-->
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</li>
<!--Timing_Report_by_Analysis_Type end-->
<!--Minimum_Pulse_Width_Report begin-->
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Minimum_Pulse_Width_Report" style=" font-size: 14px;" target="mainFrame">Minimum Pulse Width Report</a>
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<!--Minimum_Pulse_Width_Report end-->
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<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#High_Fanout_Nets_Report" style=" font-size: 14px;" target="mainFrame">High Fanout Nets Report</a></li>
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<!--Route_Congestions_Report begin-->
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Route_Congestions_Report" style=" font-size: 14px;" target="mainFrame">Route Congestions Report</a></li>
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<!--Timing_Exceptions_Report begin-->
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<!--Setup_Analysis_Exceptions begin-->
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Setup_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Setup Analysis Report</a>
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lab3/impl/pnr/lab3_tr_content.html Normal file
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Timing Analysis Report</title>
<style type="text/css">
@import url(../temp/style.css);
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#content { width: 100%; margin: }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td {white-space:pre; border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table th.label { min-width: 8%; width: 8%; }
</style>
</head>
<body>
<div id="content">
<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.9.02</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sat May 4 01:07:45 2024
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.95V 85C C8/I7</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.05V 0C C8/I7</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>14</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>4</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
</table>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h4>Nothing to report!</h4>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h4>No setup paths to report!</h4>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h4>No hold paths to report!</h4>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>No recovery paths to report!</h4>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>No removal paths to report!</h4>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h4>Nothing to report!</h4>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R2C2</td>
<td>8.33%</td>
</tr>
<tr>
<td>R2C1</td>
<td>5.56%</td>
</tr>
<tr>
<td>R1C2</td>
<td>2.78%</td>
</tr>
<tr>
<td>R2C4</td>
<td>2.78%</td>
</tr>
<tr>
<td>R7C1</td>
<td>2.78%</td>
</tr>
<tr>
<td>R1C4</td>
<td>2.78%</td>
</tr>
<tr>
<td>R28C51</td>
<td>1.39%</td>
</tr>
<tr>
<td>R2C3</td>
<td>1.39%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
</div><!-- content -->
</body>
</html>

52
lab3/impl/temp/rtl_parser.result
View File

@ -1,10 +1,54 @@
[
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
"InstLine" : 1,
"InstName" : "Adder3Bit",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
"InstName" : "fullAdder",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
"ModuleLine" : 1,
"ModuleName" : "Adder3Bit"
"ModuleName" : "fullAdder",
"SubInsts" : [
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
"InstLine" : 7,
"InstName" : "h0",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
"ModuleLine" : 1,
"ModuleName" : "halfAdder"
},
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
"ModuleLine" : 1,
"ModuleName" : "halfAdder"
}
]
},
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
"InstLine" : 1,
"InstName" : "mult2bit",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
"ModuleLine" : 1,
"ModuleName" : "mult2bit",
"SubInsts" : [
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
"InstLine" : 14,
"InstName" : "h0",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
"ModuleLine" : 1,
"ModuleName" : "halfAdder"
},
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
"InstLine" : 15,
"InstName" : "h1",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
"ModuleLine" : 1,
"ModuleName" : "halfAdder"
}
]
}
]

8
lab3/impl/temp/rtl_parser_arg.json
View File

@ -2,11 +2,15 @@
"Device" : "GW2A-18C",
"Files" : [
{
"Path" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
"Path" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
"Type" : "verilog"
},
{
"Path" : "C:/cygwin64/home/koray/verilog/lab3/src/tbAdder3Bit.v",
"Path" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
"Type" : "verilog"
},
{
"Path" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
"Type" : "verilog"
}
],

0
lab3/impl/temp/style.css Normal file
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7
lab3/lab3.gprj
View File

@ -5,7 +5,10 @@
<Version>5</Version>
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
<FileList>
<File path="src/Adder3Bit.v" type="file.verilog" enable="1"/>
<File path="src/tbAdder3Bit.v" type="file.verilog" enable="1"/>
<File path="src/Adder3Bit.v" type="file.verilog" enable="0"/>
<File path="src/fullAdder.v" type="file.verilog" enable="1"/>
<File path="src/halfAdder.v" type="file.verilog" enable="1"/>
<File path="src/mult2bit.v" type="file.verilog" enable="1"/>
<File path="src/tbAdder3Bit.v" type="file.verilog" enable="0"/>
</FileList>
</Project>

21
lab3/lab3.gprj.user
View File

@ -3,11 +3,22 @@
<UserConfig>
<Version>1.0</Version>
<FlowState>
<Process ID="Synthesis" State="3"/>
<Process ID="Pnr" State="0"/>
<Process ID="Gao" State="0"/>
<Process ID="Synthesis" State="2"/>
<Process ID="Pnr" State="2"/>
<Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/>
</FlowState>
<ResultFileList/>
<Ui>000000ff00000001fd00000002000000000000017000000281fc0200000001fc00000063000002810000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000078000000121fc0100000001fc0000000000000780000000a100fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000007800fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100ffffff000006080000028100000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000</Ui>
<ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/lab3.vg"/>
<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/lab3.fs"/>
<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/lab3.pin.html"/>
<ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/lab3.db"/>
<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/lab3.power.html"/>
<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/lab3.rpt.html"/>
<ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/lab3.timing_paths"/>
<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/lab3.tr.html"/>
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/lab3_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/lab3_syn_rsc.xml"/>
</ResultFileList>
<Ui>000000ff00000001fd000000020000000000000170000002b1fc0200000001fc00000037000002b10000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000078000000121fc0100000001fc00000000000007800000009b00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000009b00ffffff0000060c000002b100000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e00450064006900740100000099ffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000153ffffffff0000000000000000</Ui>
</UserConfig>

217
lab3/src/3bit Normal file
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@ -0,0 +1,217 @@
#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_00000154a426eaa0 .scope module, "tb" "tb" 2 1;
.timescale 0 0;
v00000154a4316c30_0 .var "A", 2 0;
v00000154a4316370_0 .var "B", 2 0;
v00000154a4317770_0 .net "C", 3 0, L_00000154a43162d0; 1 drivers
S_00000154a426ec30 .scope module, "uut" "Adder3Bit" 2 5, 3 1 0, S_00000154a426eaa0;
.timescale 0 0;
.port_info 0 /INPUT 3 "A";
.port_info 1 /INPUT 3 "B";
.port_info 2 /OUTPUT 4 "C";
v00000154a4316230_0 .net "A", 2 0, v00000154a4316c30_0; 1 drivers
v00000154a43173b0_0 .net "B", 2 0, v00000154a4316370_0; 1 drivers
v00000154a4317450_0 .net "C", 3 0, L_00000154a43162d0; alias, 1 drivers
v00000154a4316050_0 .net "c1", 0 0, L_00000154a42aabe0; 1 drivers
v00000154a43174f0_0 .net "c2", 0 0, L_00000154a42ab200; 1 drivers
L_00000154a4315fb0 .part v00000154a4316c30_0, 0, 1;
L_00000154a4315b50 .part v00000154a4316370_0, 0, 1;
L_00000154a4316190 .part v00000154a4316c30_0, 1, 1;
L_00000154a4317590 .part v00000154a4316370_0, 1, 1;
L_00000154a4317630 .part v00000154a4316c30_0, 2, 1;
L_00000154a4316a50 .part v00000154a4316370_0, 2, 1;
L_00000154a43162d0 .concat8 [ 1 1 1 1], L_00000154a42aa8d0, L_00000154a42ab580, L_00000154a42ab660, L_00000154a42aad30;
S_00000154a426d820 .scope module, "a0" "halfAdder" 3 8, 4 1 0, S_00000154a426ec30;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_00000154a42aa8d0 .functor XOR 1, L_00000154a4315fb0, L_00000154a4315b50, C4<0>, C4<0>;
L_00000154a42aabe0 .functor AND 1, L_00000154a4315fb0, L_00000154a4315b50, C4<1>, C4<1>;
v00000154a42aa140_0 .net "A", 0 0, L_00000154a4315fb0; 1 drivers
v00000154a42a9c40_0 .net "B", 0 0, L_00000154a4315b50; 1 drivers
v00000154a42aa000_0 .net "C", 0 0, L_00000154a42aabe0; alias, 1 drivers
v00000154a42a9880_0 .net "S", 0 0, L_00000154a42aa8d0; 1 drivers
S_00000154a426d9b0 .scope module, "a1" "fullAdder" 3 10, 5 1 0, S_00000154a426ec30;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Z";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "C";
L_00000154a42ab200 .functor OR 1, L_00000154a42aab70, L_00000154a42aa940, C4<0>, C4<0>;
v00000154a42a99c0_0 .net "A", 0 0, L_00000154a4316190; 1 drivers
v00000154a42aa6e0_0 .net "B", 0 0, L_00000154a4317590; 1 drivers
v00000154a42aa320_0 .net "C", 0 0, L_00000154a42ab200; alias, 1 drivers
v00000154a42aa500_0 .net "S", 0 0, L_00000154a42ab580; 1 drivers
v00000154a42a9b00_0 .net "W0", 0 0, L_00000154a42ab510; 1 drivers
v00000154a42aa640_0 .net "W1", 0 0, L_00000154a42aab70; 1 drivers
v00000154a42a9d80_0 .net "W2", 0 0, L_00000154a42aa940; 1 drivers
v00000154a42a9ec0_0 .net "Z", 0 0, L_00000154a42aabe0; alias, 1 drivers
S_00000154a426c910 .scope module, "h0" "halfAdder" 5 7, 4 1 0, S_00000154a426d9b0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_00000154a42ab510 .functor XOR 1, L_00000154a4316190, L_00000154a4317590, C4<0>, C4<0>;
L_00000154a42aab70 .functor AND 1, L_00000154a4316190, L_00000154a4317590, C4<1>, C4<1>;
v00000154a42aa0a0_0 .net "A", 0 0, L_00000154a4316190; alias, 1 drivers
v00000154a42a9a60_0 .net "B", 0 0, L_00000154a4317590; alias, 1 drivers
v00000154a42aa1e0_0 .net "C", 0 0, L_00000154a42aab70; alias, 1 drivers
v00000154a42aa280_0 .net "S", 0 0, L_00000154a42ab510; alias, 1 drivers
S_00000154a426caa0 .scope module, "h1" "halfAdder" 5 8, 4 1 0, S_00000154a426d9b0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_00000154a42ab580 .functor XOR 1, L_00000154a42ab510, L_00000154a42aabe0, C4<0>, C4<0>;
L_00000154a42aa940 .functor AND 1, L_00000154a42ab510, L_00000154a42aabe0, C4<1>, C4<1>;
v00000154a42a97e0_0 .net "A", 0 0, L_00000154a42ab510; alias, 1 drivers
v00000154a42a9ce0_0 .net "B", 0 0, L_00000154a42aabe0; alias, 1 drivers
v00000154a42a9920_0 .net "C", 0 0, L_00000154a42aa940; alias, 1 drivers
v00000154a42aa460_0 .net "S", 0 0, L_00000154a42ab580; alias, 1 drivers
S_00000154a4282990 .scope module, "a2" "fullAdder" 3 11, 5 1 0, S_00000154a426ec30;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Z";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "C";
L_00000154a42aad30 .functor OR 1, L_00000154a42ab3c0, L_00000154a42aa9b0, C4<0>, C4<0>;
v00000154a4316910_0 .net "A", 0 0, L_00000154a4317630; 1 drivers
v00000154a43160f0_0 .net "B", 0 0, L_00000154a4316a50; 1 drivers
v00000154a4317270_0 .net "C", 0 0, L_00000154a42aad30; 1 drivers
v00000154a4316ff0_0 .net "S", 0 0, L_00000154a42ab660; 1 drivers
v00000154a4316b90_0 .net "W0", 0 0, L_00000154a42ab350; 1 drivers
v00000154a43171d0_0 .net "W1", 0 0, L_00000154a42ab3c0; 1 drivers
v00000154a4317310_0 .net "W2", 0 0, L_00000154a42aa9b0; 1 drivers
v00000154a43176d0_0 .net "Z", 0 0, L_00000154a42ab200; alias, 1 drivers
S_00000154a4282b20 .scope module, "h0" "halfAdder" 5 7, 4 1 0, S_00000154a4282990;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_00000154a42ab350 .functor XOR 1, L_00000154a4317630, L_00000154a4316a50, C4<0>, C4<0>;
L_00000154a42ab3c0 .functor AND 1, L_00000154a4317630, L_00000154a4316a50, C4<1>, C4<1>;
v00000154a42a9e20_0 .net "A", 0 0, L_00000154a4317630; alias, 1 drivers
v00000154a42aa5a0_0 .net "B", 0 0, L_00000154a4316a50; alias, 1 drivers
v00000154a4316870_0 .net "C", 0 0, L_00000154a42ab3c0; alias, 1 drivers
v00000154a4315c90_0 .net "S", 0 0, L_00000154a42ab350; alias, 1 drivers
S_00000154a4282cb0 .scope module, "h1" "halfAdder" 5 8, 4 1 0, S_00000154a4282990;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_00000154a42ab660 .functor XOR 1, L_00000154a42ab350, L_00000154a42ab200, C4<0>, C4<0>;
L_00000154a42aa9b0 .functor AND 1, L_00000154a42ab350, L_00000154a42ab200, C4<1>, C4<1>;
v00000154a4315ab0_0 .net "A", 0 0, L_00000154a42ab350; alias, 1 drivers
v00000154a4316730_0 .net "B", 0 0, L_00000154a42ab200; alias, 1 drivers
v00000154a43169b0_0 .net "C", 0 0, L_00000154a42aa9b0; alias, 1 drivers
v00000154a4317130_0 .net "S", 0 0, L_00000154a42ab660; alias, 1 drivers
.scope S_00000154a426eaa0;
T_0 ;
%vpi_call 2 8 "$dumpfile", "dmp.vcd" {0 0 0};
%vpi_call 2 9 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 3;
%store/vec4 v00000154a4316c30_0, 0, 3;
%pushi/vec4 7, 0, 3;
%store/vec4 v00000154a4316370_0, 0, 3;
%delay 10, 0;
%pushi/vec4 1, 0, 3;
%store/vec4 v00000154a4316c30_0, 0, 3;
%pushi/vec4 6, 0, 3;
%store/vec4 v00000154a4316370_0, 0, 3;
%delay 10, 0;
%pushi/vec4 2, 0, 3;
%store/vec4 v00000154a4316c30_0, 0, 3;
%pushi/vec4 5, 0, 3;
%store/vec4 v00000154a4316370_0, 0, 3;
%delay 10, 0;
%pushi/vec4 3, 0, 3;
%store/vec4 v00000154a4316c30_0, 0, 3;
%pushi/vec4 4, 0, 3;
%store/vec4 v00000154a4316370_0, 0, 3;
%delay 10, 0;
%pushi/vec4 4, 0, 3;
%store/vec4 v00000154a4316c30_0, 0, 3;
%pushi/vec4 3, 0, 3;
%store/vec4 v00000154a4316370_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v00000154a4316c30_0, 0, 3;
%pushi/vec4 2, 0, 3;
%store/vec4 v00000154a4316370_0, 0, 3;
%delay 10, 0;
%pushi/vec4 6, 0, 3;
%store/vec4 v00000154a4316c30_0, 0, 3;
%pushi/vec4 1, 0, 3;
%store/vec4 v00000154a4316370_0, 0, 3;
%delay 10, 0;
%pushi/vec4 7, 0, 3;
%store/vec4 v00000154a4316c30_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v00000154a4316370_0, 0, 3;
%delay 10, 0;
%pushi/vec4 0, 0, 3;
%store/vec4 v00000154a4316c30_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v00000154a4316370_0, 0, 3;
%delay 10, 0;
%pushi/vec4 1, 0, 3;
%store/vec4 v00000154a4316c30_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v00000154a4316370_0, 0, 3;
%delay 10, 0;
%pushi/vec4 2, 0, 3;
%store/vec4 v00000154a4316c30_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v00000154a4316370_0, 0, 3;
%delay 10, 0;
%pushi/vec4 3, 0, 3;
%store/vec4 v00000154a4316c30_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v00000154a4316370_0, 0, 3;
%delay 10, 0;
%pushi/vec4 4, 0, 3;
%store/vec4 v00000154a4316c30_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v00000154a4316370_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v00000154a4316c30_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v00000154a4316370_0, 0, 3;
%delay 10, 0;
%pushi/vec4 6, 0, 3;
%store/vec4 v00000154a4316c30_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v00000154a4316370_0, 0, 3;
%delay 10, 0;
%pushi/vec4 7, 0, 3;
%store/vec4 v00000154a4316c30_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v00000154a4316370_0, 0, 3;
%delay 10, 0;
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 6;
"N/A";
"<interactive>";
".\tb.v";
".\Adder3Bit.v";
".\halfAdder.v";
".\fullAdder.v";

142
lab3/src/3dmp.vcd Normal file
View File

@ -0,0 +1,142 @@
$date
Sat May 04 01:15:09 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module fullAdder $end
$var wire 1 ! A $end
$var wire 1 " B $end
$var wire 1 # C $end
$var wire 1 $ Z $end
$var wire 1 % W2 $end
$var wire 1 & W1 $end
$var wire 1 ' W0 $end
$var wire 1 ( S $end
$scope module h0 $end
$var wire 1 ! A $end
$var wire 1 " B $end
$var wire 1 & C $end
$var wire 1 ' S $end
$upscope $end
$scope module h1 $end
$var wire 1 ' A $end
$var wire 1 $ B $end
$var wire 1 % C $end
$var wire 1 ( S $end
$upscope $end
$upscope $end
$scope module mtb $end
$var wire 4 ) C [3:0] $end
$var reg 2 * A [1:0] $end
$var reg 2 + B [1:0] $end
$scope module uut $end
$var wire 2 , A [1:0] $end
$var wire 2 - B [1:0] $end
$var wire 1 . c1 $end
$var wire 1 / c2 $end
$var wire 1 0 c5 $end
$var wire 1 1 c4 $end
$var wire 4 2 C [3:0] $end
$scope module h0 $end
$var wire 1 . A $end
$var wire 1 / B $end
$var wire 1 1 C $end
$var wire 1 3 S $end
$upscope $end
$scope module h1 $end
$var wire 1 0 A $end
$var wire 1 1 B $end
$var wire 1 4 C $end
$var wire 1 5 S $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
05
04
03
b0 2
01
00
0/
0.
b11 -
b0 ,
b11 +
b0 *
b0 )
x(
x'
x&
x%
z$
x#
z"
z!
$end
#10
b10 )
b10 2
13
1/
b10 +
b10 -
b1 *
b1 ,
#20
1.
0/
b1 +
b1 -
b10 *
b10 ,
#30
b0 )
b0 2
03
0.
b0 +
b0 -
b11 *
b11 ,
#40
b0 *
b0 ,
#50
b1 )
b1 2
b1 +
b1 -
b1 *
b1 ,
#60
15
10
b1000 )
b1000 2
b10 +
b10 -
b10 *
b10 ,
#70
05
14
11
1.
1/
b101 )
b101 2
b11 +
b11 -
b11 *
b11 ,
#80

140
lab3/src/Adder3Bit Normal file
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@ -0,0 +1,140 @@
#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_000001e07a11e640 .scope module, "tbAdder3Bit" "tbAdder3Bit" 2 1;
.timescale 0 0;
v000001e07a09f780_0 .var "r1", 2 0;
v000001e07a09f5a0_0 .var "r2", 2 0;
v000001e07a0a0d60_0 .net "w1", 2 0, L_000001e07a0a0ea0; 1 drivers
v000001e07a0a0360_0 .net "w2", 2 0, L_000001e07a0a05e0; 1 drivers
S_000001e07a11e7d0 .scope module, "uut" "Adder3Bit" 2 6, 3 1 0, S_000001e07a11e640;
.timescale 0 0;
.port_info 0 /INPUT 3 "num1";
.port_info 1 /INPUT 3 "num2";
.port_info 2 /OUTPUT 3 "Carry";
.port_info 3 /OUTPUT 3 "sum";
L_000001e07a118f90 .functor XOR 1, L_000001e07a09fdc0, L_000001e07a09f000, C4<0>, C4<0>;
L_000001e07a1190e0 .functor AND 1, L_000001e07a0a0400, L_000001e07a0a0220, C4<1>, C4<1>;
L_000001e07a119000 .functor XOR 1, L_000001e07a09fbe0, L_000001e07a0a0e00, C4<0>, C4<0>;
L_000001e07a1191c0 .functor XOR 1, L_000001e07a119000, L_000001e07a09f8c0, C4<0>, C4<0>;
L_000001e07a119310 .functor AND 1, L_000001e07a119000, L_000001e07a09f460, C4<1>, C4<1>;
L_000001e07a119070 .functor AND 1, L_000001e07a09fa00, L_000001e07a0a09a0, C4<1>, C4<1>;
L_000001e07a0a2d40 .functor OR 1, L_000001e07a119310, L_000001e07a119070, C4<0>, C4<0>;
L_000001e07a0a25d0 .functor XOR 1, L_000001e07a09fc80, L_000001e07a0a0b80, C4<0>, C4<0>;
L_000001e07a0a2bf0 .functor XOR 1, L_000001e07a0a25d0, L_000001e07a09faa0, C4<0>, C4<0>;
L_000001e07a0a24f0 .functor AND 1, L_000001e07a0a25d0, L_000001e07a09f500, C4<1>, C4<1>;
L_000001e07a0a2170 .functor AND 1, L_000001e07a09f280, L_000001e07a0a0540, C4<1>, C4<1>;
L_000001e07a0a2640 .functor OR 1, L_000001e07a0a24f0, L_000001e07a0a2170, C4<0>, C4<0>;
v000001e07a036150_0 .net "Carry", 2 0, L_000001e07a0a05e0; alias, 1 drivers
v000001e07a035750_0 .net *"_ivl_1", 0 0, L_000001e07a118f90; 1 drivers
v000001e07a0357f0_0 .net *"_ivl_11", 0 0, L_000001e07a0a0400; 1 drivers
v000001e07a035d90_0 .net *"_ivl_13", 0 0, L_000001e07a0a0220; 1 drivers
v000001e07a036470_0 .net *"_ivl_17", 0 0, L_000001e07a09fbe0; 1 drivers
v000001e07a035ed0_0 .net *"_ivl_19", 0 0, L_000001e07a0a0e00; 1 drivers
v000001e07a036510_0 .net *"_ivl_21", 0 0, L_000001e07a1191c0; 1 drivers
v000001e07a036010_0 .net *"_ivl_25", 0 0, L_000001e07a09f8c0; 1 drivers
v000001e07a035890_0 .net *"_ivl_30", 0 0, L_000001e07a09f460; 1 drivers
v000001e07a0365b0_0 .net *"_ivl_34", 0 0, L_000001e07a09fa00; 1 drivers
v000001e07a035930_0 .net *"_ivl_36", 0 0, L_000001e07a0a09a0; 1 drivers
v000001e07a0a04a0_0 .net *"_ivl_38", 0 0, L_000001e07a0a2d40; 1 drivers
v000001e07a0a0cc0_0 .net *"_ivl_4", 0 0, L_000001e07a09fdc0; 1 drivers
v000001e07a09f1e0_0 .net *"_ivl_45", 0 0, L_000001e07a09fc80; 1 drivers
v000001e07a09f140_0 .net *"_ivl_47", 0 0, L_000001e07a0a0b80; 1 drivers
v000001e07a0a0a40_0 .net *"_ivl_49", 0 0, L_000001e07a0a2bf0; 1 drivers
v000001e07a09f320_0 .net *"_ivl_54", 0 0, L_000001e07a09faa0; 1 drivers
v000001e07a09fe60_0 .net *"_ivl_59", 0 0, L_000001e07a09f500; 1 drivers
v000001e07a09f960_0 .net *"_ivl_6", 0 0, L_000001e07a09f000; 1 drivers
v000001e07a09f820_0 .net *"_ivl_63", 0 0, L_000001e07a09f280; 1 drivers
v000001e07a09f6e0_0 .net *"_ivl_65", 0 0, L_000001e07a0a0540; 1 drivers
v000001e07a0a0040_0 .net *"_ivl_67", 0 0, L_000001e07a0a2640; 1 drivers
v000001e07a09f0a0_0 .net *"_ivl_8", 0 0, L_000001e07a1190e0; 1 drivers
v000001e07a09f640_0 .net "num1", 2 0, v000001e07a09f780_0; 1 drivers
v000001e07a09f3c0 .array "num12", 0 1;
v000001e07a09f3c0_0 .net v000001e07a09f3c0 0, 0 0, L_000001e07a119000; 1 drivers
v000001e07a09f3c0_1 .net v000001e07a09f3c0 1, 0 0, L_000001e07a0a25d0; 1 drivers
v000001e07a09ff00 .array "num12Carry", 0 1;
v000001e07a09ff00_0 .net v000001e07a09ff00 0, 0 0, L_000001e07a119310; 1 drivers
v000001e07a09ff00_1 .net v000001e07a09ff00 1, 0 0, L_000001e07a0a24f0; 1 drivers
v000001e07a0a0900 .array "num1a2", 0 1;
v000001e07a0a0900_0 .net v000001e07a0a0900 0, 0 0, L_000001e07a119070; 1 drivers
v000001e07a0a0900_1 .net v000001e07a0a0900 1, 0 0, L_000001e07a0a2170; 1 drivers
v000001e07a09fb40_0 .net "num2", 2 0, v000001e07a09f5a0_0; 1 drivers
v000001e07a09fd20_0 .net "sum", 2 0, L_000001e07a0a0ea0; alias, 1 drivers
L_000001e07a09fdc0 .part v000001e07a09f780_0, 0, 1;
L_000001e07a09f000 .part v000001e07a09f5a0_0, 0, 1;
L_000001e07a0a0400 .part v000001e07a09f780_0, 0, 1;
L_000001e07a0a0220 .part v000001e07a09f5a0_0, 0, 1;
L_000001e07a09fbe0 .part v000001e07a09f780_0, 1, 1;
L_000001e07a0a0e00 .part v000001e07a09f5a0_0, 1, 1;
L_000001e07a09f8c0 .part L_000001e07a0a05e0, 0, 1;
L_000001e07a09f460 .part L_000001e07a0a05e0, 0, 1;
L_000001e07a09fa00 .part v000001e07a09f780_0, 1, 1;
L_000001e07a0a09a0 .part v000001e07a09f5a0_0, 1, 1;
L_000001e07a09fc80 .part v000001e07a09f780_0, 2, 1;
L_000001e07a0a0b80 .part v000001e07a09f5a0_0, 2, 1;
L_000001e07a0a0ea0 .concat8 [ 1 1 1 0], L_000001e07a118f90, L_000001e07a1191c0, L_000001e07a0a2bf0;
L_000001e07a09faa0 .part L_000001e07a0a05e0, 1, 1;
L_000001e07a09f500 .part L_000001e07a0a05e0, 1, 1;
L_000001e07a09f280 .part v000001e07a09f780_0, 2, 1;
L_000001e07a0a0540 .part v000001e07a09f5a0_0, 2, 1;
L_000001e07a0a05e0 .concat8 [ 1 1 1 0], L_000001e07a1190e0, L_000001e07a0a2d40, L_000001e07a0a2640;
.scope S_000001e07a11e640;
T_0 ;
%vpi_call 2 14 "$dumpfile", "Admp.vcd" {0 0 0};
%vpi_call 2 15 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 3;
%store/vec4 v000001e07a09f780_0, 0, 3;
%pushi/vec4 0, 0, 3;
%store/vec4 v000001e07a09f5a0_0, 0, 3;
%delay 10, 0;
%pushi/vec4 1, 0, 3;
%store/vec4 v000001e07a09f780_0, 0, 3;
%pushi/vec4 1, 0, 3;
%store/vec4 v000001e07a09f5a0_0, 0, 3;
%delay 10, 0;
%pushi/vec4 2, 0, 3;
%store/vec4 v000001e07a09f780_0, 0, 3;
%pushi/vec4 2, 0, 3;
%store/vec4 v000001e07a09f5a0_0, 0, 3;
%delay 10, 0;
%pushi/vec4 4, 0, 3;
%store/vec4 v000001e07a09f780_0, 0, 3;
%pushi/vec4 4, 0, 3;
%store/vec4 v000001e07a09f5a0_0, 0, 3;
%delay 10, 0;
%pushi/vec4 3, 0, 3;
%store/vec4 v000001e07a09f780_0, 0, 3;
%pushi/vec4 3, 0, 3;
%store/vec4 v000001e07a09f5a0_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v000001e07a09f780_0, 0, 3;
%pushi/vec4 5, 0, 3;
%store/vec4 v000001e07a09f5a0_0, 0, 3;
%delay 10, 0;
%pushi/vec4 6, 0, 3;
%store/vec4 v000001e07a09f780_0, 0, 3;
%pushi/vec4 6, 0, 3;
%store/vec4 v000001e07a09f5a0_0, 0, 3;
%delay 10, 0;
%pushi/vec4 7, 0, 3;
%store/vec4 v000001e07a09f780_0, 0, 3;
%pushi/vec4 7, 0, 3;
%store/vec4 v000001e07a09f5a0_0, 0, 3;
%delay 10, 0;
%vpi_call 2 24 "$display", v000001e07a0a0d60_0 {0 0 0};
%vpi_call 2 25 "$display", v000001e07a0a0360_0 {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
".\tbAdder3Bit.v";
".\Adder3Bit.v";

31
lab3/src/Adder3Bit.v
View File

@ -1,30 +1,15 @@
module Adder3Bit (
input [2:0] num1,
input [2:0] num2,
output [2:0] Carry,
output [2:0] sum
input [2:0] A,
input [2:0] B,
output [3:0] C
);
xor (sum[0], num1[0], num2[0]);
and (Carry[0], num1[0], num2[0]);
wire c1, c2;
halfAdder a0(A[0], B[0], C[0], c1);
wire num12[1:0];
wire num12Carry[1:0], num1a2[1:0];
fullAdder a1(A[1], B[1], c1, C[1], c2);
fullAdder a2(A[2], B[2], c2, C[2], C[3]);
xor (num12[0], num1[1], num2[1]);
xor (sum[1], num12[0], Carry[0]);
and (num12Carry[0], num12[0], Carry[0]);
and (num1a2[0], num1[1], num2[1]);
or (Carry[1], num12Carry[0], num1a2[0]);
xor (num12[1], num1[2], num2[2]);
xor (sum[2], num12[1], Carry[1]);
and (num12Carry[1], num12[1], Carry[1]);
and (num1a2[1], num1[2], num2[2]);
or (Carry[2], num12Carry[1], num1a2[1]);
endmodule

100
lab3/src/Admp.vcd Normal file
View File

@ -0,0 +1,100 @@
$date
Sat Apr 13 14:50:50 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module tbAdder3Bit $end
$var wire 3 ! w2 [2:0] $end
$var wire 3 " w1 [2:0] $end
$var reg 3 # r1 [2:0] $end
$var reg 3 $ r2 [2:0] $end
$scope module uut $end
$var wire 3 % num1 [2:0] $end
$var wire 3 & num2 [2:0] $end
$var wire 3 ' sum [2:0] $end
$var wire 3 ( Carry [2:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
b0 (
b0 '
b0 &
b0 %
b0 $
b0 #
b0 "
b0 !
$end
#10
b10 "
b10 '
b1 !
b1 (
b1 $
b1 &
b1 #
b1 %
#20
b100 "
b100 '
b10 !
b10 (
b10 $
b10 &
b10 #
b10 %
#30
b0 "
b0 '
b100 !
b100 (
b100 $
b100 &
b100 #
b100 %
#40
b110 "
b110 '
b11 !
b11 (
b11 $
b11 &
b11 #
b11 %
#50
b10 "
b10 '
b101 !
b101 (
b101 $
b101 &
b101 #
b101 %
#60
b100 "
b100 '
b110 !
b110 (
b110 $
b110 &
b110 #
b110 %
#70
b110 "
b110 '
b111 !
b111 (
b111 $
b111 &
b111 #
b111 %
#80

234
lab3/src/dmp.vcd Normal file
View File

@ -0,0 +1,234 @@
$date
Fri May 03 11:28:11 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module tb $end
$var wire 4 ! C [3:0] $end
$var reg 3 " A [2:0] $end
$var reg 3 # B [2:0] $end
$scope module uut $end
$var wire 3 $ A [2:0] $end
$var wire 3 % B [2:0] $end
$var wire 1 & c2 $end
$var wire 1 ' c1 $end
$var wire 4 ( C [3:0] $end
$scope module a0 $end
$var wire 1 ) A $end
$var wire 1 * B $end
$var wire 1 ' C $end
$var wire 1 + S $end
$upscope $end
$scope module a1 $end
$var wire 1 , A $end
$var wire 1 - B $end
$var wire 1 & C $end
$var wire 1 ' Z $end
$var wire 1 . W2 $end
$var wire 1 / W1 $end
$var wire 1 0 W0 $end
$var wire 1 1 S $end
$scope module h0 $end
$var wire 1 , A $end
$var wire 1 - B $end
$var wire 1 / C $end
$var wire 1 0 S $end
$upscope $end
$scope module h1 $end
$var wire 1 0 A $end
$var wire 1 ' B $end
$var wire 1 . C $end
$var wire 1 1 S $end
$upscope $end
$upscope $end
$scope module a2 $end
$var wire 1 2 A $end
$var wire 1 3 B $end
$var wire 1 4 C $end
$var wire 1 & Z $end
$var wire 1 5 W2 $end
$var wire 1 6 W1 $end
$var wire 1 7 W0 $end
$var wire 1 8 S $end
$scope module h0 $end
$var wire 1 2 A $end
$var wire 1 3 B $end
$var wire 1 6 C $end
$var wire 1 7 S $end
$upscope $end
$scope module h1 $end
$var wire 1 7 A $end
$var wire 1 & B $end
$var wire 1 5 C $end
$var wire 1 8 S $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
18
17
06
05
04
13
02
11
10
0/
0.
1-
0,
1+
1*
0)
b111 (
0'
0&
b111 %
b0 $
b111 #
b0 "
b111 !
$end
#10
0*
1)
b110 #
b110 %
b1 "
b1 $
#20
1*
0-
0)
1,
b101 #
b101 %
b10 "
b10 $
#30
0*
1)
b100 #
b100 %
b11 "
b11 $
#40
1*
1-
03
0)
0,
12
b11 #
b11 %
b100 "
b100 $
#50
0*
1)
b10 #
b10 %
b101 "
b101 $
#60
1*
0-
0)
1,
b1 #
b1 %
b110 "
b110 $
#70
0*
1)
b0 #
b0 %
b111 "
b111 $
#80
01
08
b0 !
b0 (
0+
00
07
0)
0,
02
b0 "
b0 $
#90
b1 !
b1 (
1+
1)
b1 "
b1 $
#100
11
b10 !
b10 (
0+
10
0)
1,
b10 "
b10 $
#110
b11 !
b11 (
1+
1)
b11 "
b11 $
#120
01
18
b100 !
b100 (
0+
00
17
0)
0,
12
b100 "
b100 $
#130
b101 !
b101 (
1+
1)
b101 "
b101 $
#140
11
b110 !
b110 (
0+
10
0)
1,
b110 "
b110 $
#150
b111 !
b111 (
1+
1)
b111 "
b111 $
#160

12
lab3/src/fullAdder.v Normal file
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@ -0,0 +1,12 @@
module fullAdder(
input A, B, Z,
output S, C
);
wire W0, W1, W2;
halfAdder h0(A, B, W0, W1);
halfAdder h1(W0, Z, S, W2);
or(C, W1, W2);
endmodule

9
lab3/src/halfAdder.v Normal file
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@ -0,0 +1,9 @@
module halfAdder(
input A, B,
output S, C
);
xor(S, A, B);
and(C, A, B);
endmodule

23
lab3/src/mtb.v Normal file
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@ -0,0 +1,23 @@
module mtb();
reg[1:0] A, B;
wire [3:0] C;
mult2bit uut(A,B,C);
initial begin
$dumpfile("3dmp.vcd");
$dumpvars;
A = 2'd0; B = 2'd3; #10;
A = 2'd1; B = 2'd2; #10;
A = 2'd2; B = 2'd1; #10;
A = 2'd3; B = 2'd0; #10;
A = 2'd0; B = 2'd0; #10;
A = 2'd1; B = 2'd1; #10;
A = 2'd2; B = 2'd2; #10;
A = 2'd3; B = 2'd3; #10;
end
endmodule

169
lab3/src/mult2 Normal file
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@ -0,0 +1,169 @@
#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_0000025ecd40d010 .scope module, "fullAdder" "fullAdder" 2 1;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Z";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "C";
L_0000025ecd257f60 .functor OR 1, L_0000025ecd258660, L_0000025ecd2585f0, C4<0>, C4<0>;
o0000025ecd26dfb8 .functor BUFZ 1, C4<z>; HiZ drive
v0000025ecd25a670_0 .net "A", 0 0, o0000025ecd26dfb8; 0 drivers
o0000025ecd26dfe8 .functor BUFZ 1, C4<z>; HiZ drive
v0000025ecd25ae90_0 .net "B", 0 0, o0000025ecd26dfe8; 0 drivers
v0000025ecd25a710_0 .net "C", 0 0, L_0000025ecd257f60; 1 drivers
v0000025ecd25a8f0_0 .net "S", 0 0, L_0000025ecd258580; 1 drivers
v0000025ecd25afd0_0 .net "W0", 0 0, L_0000025ecd2584a0; 1 drivers
v0000025ecd25a990_0 .net "W1", 0 0, L_0000025ecd258660; 1 drivers
v0000025ecd25aa30_0 .net "W2", 0 0, L_0000025ecd2585f0; 1 drivers
o0000025ecd26e138 .functor BUFZ 1, C4<z>; HiZ drive
v0000025ecd25b070_0 .net "Z", 0 0, o0000025ecd26e138; 0 drivers
S_0000025ecd40e9d0 .scope module, "h0" "halfAdder" 2 7, 3 1 0, S_0000025ecd40d010;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0000025ecd2584a0 .functor XOR 1, o0000025ecd26dfb8, o0000025ecd26dfe8, C4<0>, C4<0>;
L_0000025ecd258660 .functor AND 1, o0000025ecd26dfb8, o0000025ecd26dfe8, C4<1>, C4<1>;
v0000025ecd25a530_0 .net "A", 0 0, o0000025ecd26dfb8; alias, 0 drivers
v0000025ecd25adf0_0 .net "B", 0 0, o0000025ecd26dfe8; alias, 0 drivers
v0000025ecd25a5d0_0 .net "C", 0 0, L_0000025ecd258660; alias, 1 drivers
v0000025ecd25b2f0_0 .net "S", 0 0, L_0000025ecd2584a0; alias, 1 drivers
S_0000025ecd40eb60 .scope module, "h1" "halfAdder" 2 8, 3 1 0, S_0000025ecd40d010;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0000025ecd258580 .functor XOR 1, L_0000025ecd2584a0, o0000025ecd26e138, C4<0>, C4<0>;
L_0000025ecd2585f0 .functor AND 1, L_0000025ecd2584a0, o0000025ecd26e138, C4<1>, C4<1>;
v0000025ecd25b110_0 .net "A", 0 0, L_0000025ecd2584a0; alias, 1 drivers
v0000025ecd25a850_0 .net "B", 0 0, o0000025ecd26e138; alias, 0 drivers
v0000025ecd25b1b0_0 .net "C", 0 0, L_0000025ecd2585f0; alias, 1 drivers
v0000025ecd25a3f0_0 .net "S", 0 0, L_0000025ecd258580; alias, 1 drivers
S_0000025ecd40d1a0 .scope module, "mtb" "mtb" 4 1;
.timescale 0 0;
v0000025ecd2c1fb0_0 .var "A", 1 0;
v0000025ecd2c1bf0_0 .var "B", 1 0;
v0000025ecd2c1f10_0 .net "C", 3 0, L_0000025ecd2c0f70; 1 drivers
S_0000025ecd26aae0 .scope module, "uut" "mult2bit" 4 5, 5 1 0, S_0000025ecd40d1a0;
.timescale 0 0;
.port_info 0 /INPUT 2 "A";
.port_info 1 /INPUT 2 "B";
.port_info 2 /OUTPUT 4 "C";
L_0000025ecd257fd0 .functor AND 1, L_0000025ecd2c1dd0, L_0000025ecd2c0ed0, C4<1>, C4<1>;
L_0000025ecd2c2a60 .functor AND 1, L_0000025ecd2c2230, L_0000025ecd2c0890, C4<1>, C4<1>;
L_0000025ecd2c2de0 .functor AND 1, L_0000025ecd2c0b10, L_0000025ecd2c22d0, C4<1>, C4<1>;
L_0000025ecd2c28a0 .functor AND 1, L_0000025ecd2c2410, L_0000025ecd2c24b0, C4<1>, C4<1>;
v0000025ecd2c15b0_0 .net "A", 1 0, v0000025ecd2c1fb0_0; 1 drivers
v0000025ecd2c1d30_0 .net "B", 1 0, v0000025ecd2c1bf0_0; 1 drivers
v0000025ecd2c0bb0_0 .net "C", 3 0, L_0000025ecd2c0f70; alias, 1 drivers
v0000025ecd2c1e70_0 .net *"_ivl_1", 0 0, L_0000025ecd2c1dd0; 1 drivers
v0000025ecd2c1830_0 .net *"_ivl_11", 0 0, L_0000025ecd2c22d0; 1 drivers
v0000025ecd2c0c50_0 .net *"_ivl_12", 0 0, L_0000025ecd2c28a0; 1 drivers
v0000025ecd2c2370_0 .net *"_ivl_15", 0 0, L_0000025ecd2c2410; 1 drivers
v0000025ecd2c18d0_0 .net *"_ivl_17", 0 0, L_0000025ecd2c24b0; 1 drivers
v0000025ecd2c2690_0 .net *"_ivl_3", 0 0, L_0000025ecd2c0ed0; 1 drivers
v0000025ecd2c0a70_0 .net *"_ivl_5", 0 0, L_0000025ecd2c2230; 1 drivers
v0000025ecd2c0cf0_0 .net *"_ivl_7", 0 0, L_0000025ecd2c0890; 1 drivers
v0000025ecd2c1c90_0 .net *"_ivl_9", 0 0, L_0000025ecd2c0b10; 1 drivers
v0000025ecd2c1470_0 .net "c1", 0 0, L_0000025ecd257fd0; 1 drivers
v0000025ecd2c2190_0 .net "c2", 0 0, L_0000025ecd2c2a60; 1 drivers
v0000025ecd2c1650_0 .net "c4", 0 0, L_0000025ecd2c2f30; 1 drivers
v0000025ecd2c0d90_0 .net "c5", 0 0, L_0000025ecd2c2de0; 1 drivers
L_0000025ecd2c1dd0 .part v0000025ecd2c1fb0_0, 1, 1;
L_0000025ecd2c0ed0 .part v0000025ecd2c1bf0_0, 0, 1;
L_0000025ecd2c2230 .part v0000025ecd2c1fb0_0, 0, 1;
L_0000025ecd2c0890 .part v0000025ecd2c1bf0_0, 1, 1;
L_0000025ecd2c0b10 .part v0000025ecd2c1fb0_0, 1, 1;
L_0000025ecd2c22d0 .part v0000025ecd2c1bf0_0, 1, 1;
L_0000025ecd2c2410 .part v0000025ecd2c1fb0_0, 0, 1;
L_0000025ecd2c24b0 .part v0000025ecd2c1bf0_0, 0, 1;
L_0000025ecd2c0f70 .concat8 [ 1 1 1 1], L_0000025ecd2c28a0, L_0000025ecd2c35c0, L_0000025ecd2c2fa0, L_0000025ecd2c32b0;
S_0000025ecd26ac70 .scope module, "h0" "halfAdder" 5 14, 3 1 0, S_0000025ecd26aae0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0000025ecd2c35c0 .functor XOR 1, L_0000025ecd257fd0, L_0000025ecd2c2a60, C4<0>, C4<0>;
L_0000025ecd2c2f30 .functor AND 1, L_0000025ecd257fd0, L_0000025ecd2c2a60, C4<1>, C4<1>;
v0000025ecd25ab70_0 .net "A", 0 0, L_0000025ecd257fd0; alias, 1 drivers
v0000025ecd25acb0_0 .net "B", 0 0, L_0000025ecd2c2a60; alias, 1 drivers
v0000025ecd25ad50_0 .net "C", 0 0, L_0000025ecd2c2f30; alias, 1 drivers
v0000025ecd25af30_0 .net "S", 0 0, L_0000025ecd2c35c0; 1 drivers
S_0000025ecd232990 .scope module, "h1" "halfAdder" 5 15, 3 1 0, S_0000025ecd26aae0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0000025ecd2c32b0 .functor XOR 1, L_0000025ecd2c2de0, L_0000025ecd2c2f30, C4<0>, C4<0>;
L_0000025ecd2c2fa0 .functor AND 1, L_0000025ecd2c2de0, L_0000025ecd2c2f30, C4<1>, C4<1>;
v0000025ecd2c25f0_0 .net "A", 0 0, L_0000025ecd2c2de0; alias, 1 drivers
v0000025ecd2c1330_0 .net "B", 0 0, L_0000025ecd2c2f30; alias, 1 drivers
v0000025ecd2c09d0_0 .net "C", 0 0, L_0000025ecd2c2fa0; 1 drivers
v0000025ecd2c1b50_0 .net "S", 0 0, L_0000025ecd2c32b0; 1 drivers
.scope S_0000025ecd40d1a0;
T_0 ;
%vpi_call 4 8 "$dumpfile", "3dmp.vcd" {0 0 0};
%vpi_call 4 9 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 2;
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
%pushi/vec4 3, 0, 2;
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
%delay 10, 0;
%pushi/vec4 1, 0, 2;
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
%pushi/vec4 2, 0, 2;
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
%delay 10, 0;
%pushi/vec4 2, 0, 2;
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
%pushi/vec4 1, 0, 2;
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
%delay 10, 0;
%pushi/vec4 3, 0, 2;
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
%pushi/vec4 0, 0, 2;
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
%delay 10, 0;
%pushi/vec4 0, 0, 2;
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
%pushi/vec4 0, 0, 2;
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
%delay 10, 0;
%pushi/vec4 1, 0, 2;
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
%pushi/vec4 1, 0, 2;
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
%delay 10, 0;
%pushi/vec4 2, 0, 2;
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
%pushi/vec4 2, 0, 2;
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
%delay 10, 0;
%pushi/vec4 3, 0, 2;
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
%pushi/vec4 3, 0, 2;
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
%delay 10, 0;
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 6;
"N/A";
"<interactive>";
".\fullAdder.v";
".\halfAdder.v";
".\mtb.v";
".\mult2bit.v";

17
lab3/src/mult2bit.v Normal file
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@ -0,0 +1,17 @@
module mult2bit (
input [1:0] A,
input [1:0] B,
output [3:0] C
);
wire c1, c2, c4, c5;
and a0(c1, A[1], B[0]);
and a1(c2, A[0], B[1]);
and a2(c5, A[1], B[1]);
and a3(C[0], A[0], B[0]);
halfAdder h0(c1, c2, C[1], c4);
halfAdder h1(c5, c4, C[3], C[2]);
endmodule

31
lab3/src/tb.v Normal file
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@ -0,0 +1,31 @@
module tb();
reg [2:0] A, B;
wire [3:0] C;
Adder3Bit uut(A, B, C);
initial begin
$dumpfile("dmp.vcd");
$dumpvars;
A = 3'd0; B = 3'd7; #10;
A = 3'd1; B = 3'd6; #10;
A = 3'd2; B = 3'd5; #10;
A = 3'd3; B = 3'd4; #10;
A = 3'd4; B = 3'd3; #10;
A = 3'd5; B = 3'd2; #10;
A = 3'd6; B = 3'd1; #10;
A = 3'd7; B = 3'd0; #10;
A = 3'd0; B = 3'd0; #10;
A = 3'd1; B = 3'd0; #10;
A = 3'd2; B = 3'd0; #10;
A = 3'd3; B = 3'd0; #10;
A = 3'd4; B = 3'd0; #10;
A = 3'd5; B = 3'd0; #10;
A = 3'd6; B = 3'd0; #10;
A = 3'd7; B = 3'd0; #10;
end
endmodule

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lab3/src/tbAdder3Bit.v
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@ -1,28 +0,0 @@
module tbAdder3Bit ();
reg r1[2:0], r2[2:0];
wire w1[2:0], w2[2:0];
Adder3Bit uut(
.num1[2:0](r1[2:0]),
.num2[2:0](r2[2:0]),
.sum[2:0](w1[2:0]),
.Carry[2:0](w2[2:0])
);
initial begin
$dumpfile("Admp.vcd");
$dumpvars;
r1 = 3'b000; r2 = 3'b000; #10
r1 = 3'b001; r2 = 3'b001; #10
r1 = 3'b010; r2 = 3'b010; #10
r1 = 3'b100; r2 = 3'b100; #10
r1 = 3'b011; r2 = 3'b011; #10
r1 = 3'b101; r2 = 3'b101; #10
r1 = 3'b110; r2 = 3'b110; #10
r1 = 3'b111; r2 = 3'b111; #10
$display(w1[2:0]);
$display(w2[2:0]);
end
endmodule

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lab3_solution/adder3bit.v Normal file
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module adder3bit(
input [2:0] A,
input [2:0] B,
output [3:0] C
);
wire c1, c2, c3, c4;
ha a0(A[0], B[0], C[0], c1);
fa a1(A[1], B[1], c1, C[1], c2);
fa a2(A[2], B[2], c2, C[2], C[3]);
endmodule

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lab3_solution/fa.v Normal file
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module fa(
input X, Y, Z,
output S, C
);
wire W0, W1, W2;
ha h0(X, Y, W0, W1);
ha h1(W0, Z, S, W2);
or(C, W1, W2);
endmodule

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lab3_solution/ha.v Normal file
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module ha(
input X, Y,
output S, C
);
xor(S, X, Y);
and(C, X, Y);
endmodule

3
lab3_solution/run.sh Normal file
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iverilog *.v &&
vvp a.out &&
gtkwave dmp.vcd

31
lab3_solution/tb.v Normal file
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module tb();
reg [2:0] A, B;
wire [3:0] C;
adder3bit uut(A, B, C);
initial begin
$dumpfile("dmp.vcd");
$dumpvars;
A = 3'd0; B = 3'd7; #10;
A = 3'd1; B = 3'd6; #10;
A = 3'd2; B = 3'd5; #10;
A = 3'd3; B = 3'd4; #10;
A = 3'd4; B = 3'd3; #10;
A = 3'd5; B = 3'd2; #10;
A = 3'd6; B = 3'd1; #10;
A = 3'd7; B = 3'd0; #10;
A = 3'd0; B = 3'd0; #10;
A = 3'd1; B = 3'd0; #10;
A = 3'd2; B = 3'd0; #10;
A = 3'd3; B = 3'd0; #10;
A = 3'd4; B = 3'd0; #10;
A = 3'd5; B = 3'd0; #10;
A = 3'd6; B = 3'd0; #10;
A = 3'd7; B = 3'd0; #10;
end
endmodule