verilog/lab3/impl/temp/rtl_parser_arg.json
2024-05-07 16:15:21 +03:00

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{
"Device" : "GW2A-18C",
"Files" : [
{
"Path" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
"Type" : "verilog"
},
{
"Path" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
"Type" : "verilog"
},
{
"Path" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
"Type" : "verilog"
}
],
"IncludePath" : [
],
"LoopLimit" : 2000,
"ResultFile" : "C:/cygwin64/home/koray/verilog/lab3/impl/temp/rtl_parser.result",
"Top" : "",
"VerilogStd" : "verilog_2001",
"VhdlStd" : "vhdl_93"
}