28 lines
1.3 KiB
Plaintext
28 lines
1.3 KiB
Plaintext
GowinSynthesis start
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Running parser ...
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v'
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v'
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v'
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Compiling module 'mult2bit'("C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v":1)
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Compiling module 'halfAdder'("C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v":1)
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NOTE (EX0101) : Current top module is "mult2bit"
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[5%] Running netlist conversion ...
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Running device independent optimization ...
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[10%] Optimizing Phase 0 completed
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[15%] Optimizing Phase 1 completed
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[25%] Optimizing Phase 2 completed
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Running inference ...
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[30%] Inferring Phase 0 completed
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[40%] Inferring Phase 1 completed
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[50%] Inferring Phase 2 completed
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[55%] Inferring Phase 3 completed
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Running technical mapping ...
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[60%] Tech-Mapping Phase 0 completed
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[65%] Tech-Mapping Phase 1 completed
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[75%] Tech-Mapping Phase 2 completed
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[80%] Tech-Mapping Phase 3 completed
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[90%] Tech-Mapping Phase 4 completed
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[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg" completed
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[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3_syn.rpt.html" completed
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GowinSynthesis finish
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