diff --git a/lab3/impl/gwsynthesis/lab3.log b/lab3/impl/gwsynthesis/lab3.log index 6712f17..ddf3ca3 100644 --- a/lab3/impl/gwsynthesis/lab3.log +++ b/lab3/impl/gwsynthesis/lab3.log @@ -1,23 +1,27 @@ GowinSynthesis start Running parser ... -Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v' -Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v' -ERROR (EX3615) : '.name implicit port connection' is not allowed in this dialect, use SystemVerilog mode instead("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":7) -ERROR (EX3863) : Syntax error near '['("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":7) -ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16) -ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16) -ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16) -ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16) -ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16) -ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17) -ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17) -ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17) -ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17) -ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17) -ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18) -ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18) -ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18) -ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18) -ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18) -Sorry, too many errors.. +Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v' +Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v' +Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v' +Compiling module 'mult2bit'("C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v":1) +Compiling module 'halfAdder'("C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v":1) +NOTE (EX0101) : Current top module is "mult2bit" +[5%] Running netlist conversion ... +Running device independent optimization ... +[10%] Optimizing Phase 0 completed +[15%] Optimizing Phase 1 completed +[25%] Optimizing Phase 2 completed +Running inference ... +[30%] Inferring Phase 0 completed +[40%] Inferring Phase 1 completed +[50%] Inferring Phase 2 completed +[55%] Inferring Phase 3 completed +Running technical mapping ... +[60%] Tech-Mapping Phase 0 completed +[65%] Tech-Mapping Phase 1 completed +[75%] Tech-Mapping Phase 2 completed +[80%] Tech-Mapping Phase 3 completed +[90%] Tech-Mapping Phase 4 completed +[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg" completed +[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3_syn.rpt.html" completed GowinSynthesis finish diff --git a/lab3/impl/gwsynthesis/lab3.prj b/lab3/impl/gwsynthesis/lab3.prj index 0e53b35..8ecf43c 100644 --- a/lab3/impl/gwsynthesis/lab3.prj +++ b/lab3/impl/gwsynthesis/lab3.prj @@ -4,8 +4,9 @@ beta - - + + +