15 lines
599 B
XML
15 lines
599 B
XML
<?xml version="1" encoding="UTF-8"?>
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<!DOCTYPE gowin-fpga-project>
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<Project>
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<Template>FPGA</Template>
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<Version>5</Version>
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<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
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<FileList>
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<File path="src/Adder3Bit.v" type="file.verilog" enable="0"/>
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<File path="src/fullAdder.v" type="file.verilog" enable="1"/>
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<File path="src/halfAdder.v" type="file.verilog" enable="1"/>
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<File path="src/mult2bit.v" type="file.verilog" enable="1"/>
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<File path="src/tbAdder3Bit.v" type="file.verilog" enable="0"/>
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</FileList>
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</Project>
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