From 492a55d36045d3d95d883e540434f553483d6757 Mon Sep 17 00:00:00 2001 From: k0rrluna Date: Tue, 7 May 2024 16:15:21 +0300 Subject: [PATCH] verilog --- lab3/impl/gwsynthesis/lab3.log | 44 +- lab3/impl/gwsynthesis/lab3.prj | 5 +- lab3/impl/gwsynthesis/lab3.vg | 195 +- lab3/impl/gwsynthesis/lab3_syn.rpt.html | 32 +- lab3/impl/gwsynthesis/lab3_syn_resource.html | 24 +- lab3/impl/gwsynthesis/lab3_syn_rsc.xml | 5 +- lab3/impl/pnr/cmd.do | 12 + lab3/impl/pnr/device.cfg | 21 + lab3/impl/pnr/lab3.bin | Bin 0 -> 577178 bytes lab3/impl/pnr/lab3.binx | Bin 0 -> 577680 bytes lab3/impl/pnr/lab3.db | Bin 0 -> 580 bytes lab3/impl/pnr/lab3.fs | 1378 +++++++ lab3/impl/pnr/lab3.log | 27 + lab3/impl/pnr/lab3.pin.html | 3591 ++++++++++++++++ lab3/impl/pnr/lab3.power.html | 266 ++ lab3/impl/pnr/lab3.rpt.html | 3837 ++++++++++++++++++ lab3/impl/pnr/lab3.rpt.txt | 346 ++ lab3/impl/pnr/lab3.timing_paths | 0 lab3/impl/pnr/lab3.tr.html | 10 + lab3/impl/pnr/lab3_tr_cata.html | 132 + lab3/impl/pnr/lab3_tr_content.html | 249 ++ lab3/impl/temp/rtl_parser.result | 52 +- lab3/impl/temp/rtl_parser_arg.json | 8 +- lab3/impl/temp/style.css | 0 lab3/lab3.gprj | 7 +- lab3/lab3.gprj.user | 21 +- lab3/src/3bit | 217 + lab3/src/3dmp.vcd | 142 + lab3/src/Adder3Bit | 140 + lab3/src/Adder3Bit.v | 31 +- lab3/src/Admp.vcd | 100 + lab3/src/dmp.vcd | 234 ++ lab3/src/fullAdder.v | 12 + lab3/src/halfAdder.v | 9 + lab3/src/mtb.v | 23 + lab3/src/mult2 | 169 + lab3/src/mult2bit.v | 17 + lab3/src/tb.v | 31 + lab3/src/tbAdder3Bit.v | 28 - lab3_solution/adder3bit.v | 13 + lab3_solution/fa.v | 12 + lab3_solution/ha.v | 9 + lab3_solution/run.sh | 3 + lab3_solution/tb.v | 31 + 44 files changed, 11289 insertions(+), 194 deletions(-) create mode 100644 lab3/impl/pnr/cmd.do create mode 100644 lab3/impl/pnr/device.cfg create mode 100644 lab3/impl/pnr/lab3.bin create mode 100644 lab3/impl/pnr/lab3.binx create mode 100644 lab3/impl/pnr/lab3.db create mode 100644 lab3/impl/pnr/lab3.fs create mode 100644 lab3/impl/pnr/lab3.log create mode 100644 lab3/impl/pnr/lab3.pin.html create mode 100644 lab3/impl/pnr/lab3.power.html create mode 100644 lab3/impl/pnr/lab3.rpt.html create mode 100644 lab3/impl/pnr/lab3.rpt.txt create mode 100644 lab3/impl/pnr/lab3.timing_paths create mode 100644 lab3/impl/pnr/lab3.tr.html create mode 100644 lab3/impl/pnr/lab3_tr_cata.html create mode 100644 lab3/impl/pnr/lab3_tr_content.html create mode 100644 lab3/impl/temp/style.css create mode 100644 lab3/src/3bit create mode 100644 lab3/src/3dmp.vcd create mode 100644 lab3/src/Adder3Bit create mode 100644 lab3/src/Admp.vcd create mode 100644 lab3/src/dmp.vcd create mode 100644 lab3/src/fullAdder.v create mode 100644 lab3/src/halfAdder.v create mode 100644 lab3/src/mtb.v create mode 100644 lab3/src/mult2 create mode 100644 lab3/src/mult2bit.v create mode 100644 lab3/src/tb.v delete mode 100644 lab3/src/tbAdder3Bit.v create mode 100644 lab3_solution/adder3bit.v create mode 100644 lab3_solution/fa.v create mode 100644 lab3_solution/ha.v create mode 100644 lab3_solution/run.sh create mode 100644 lab3_solution/tb.v diff --git a/lab3/impl/gwsynthesis/lab3.log b/lab3/impl/gwsynthesis/lab3.log index 6712f17..ddf3ca3 100644 --- a/lab3/impl/gwsynthesis/lab3.log +++ b/lab3/impl/gwsynthesis/lab3.log @@ -1,23 +1,27 @@ GowinSynthesis start Running parser ... -Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v' -Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v' -ERROR (EX3615) : '.name implicit port connection' is not allowed in this dialect, use SystemVerilog mode instead("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":7) -ERROR (EX3863) : Syntax error near '['("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":7) -ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16) -ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16) -ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16) -ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16) -ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16) -ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17) -ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17) -ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17) -ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17) -ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17) -ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18) -ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18) -ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18) -ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18) -ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18) -Sorry, too many errors.. +Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v' +Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v' +Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v' +Compiling module 'mult2bit'("C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v":1) +Compiling module 'halfAdder'("C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v":1) +NOTE (EX0101) : Current top module is "mult2bit" +[5%] Running netlist conversion ... +Running device independent optimization ... +[10%] Optimizing Phase 0 completed +[15%] Optimizing Phase 1 completed +[25%] Optimizing Phase 2 completed +Running inference ... +[30%] Inferring Phase 0 completed +[40%] Inferring Phase 1 completed +[50%] Inferring Phase 2 completed +[55%] Inferring Phase 3 completed +Running technical mapping ... +[60%] Tech-Mapping Phase 0 completed +[65%] Tech-Mapping Phase 1 completed +[75%] Tech-Mapping Phase 2 completed +[80%] Tech-Mapping Phase 3 completed +[90%] Tech-Mapping Phase 4 completed +[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg" completed +[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3_syn.rpt.html" completed GowinSynthesis finish diff --git a/lab3/impl/gwsynthesis/lab3.prj b/lab3/impl/gwsynthesis/lab3.prj index 0e53b35..8ecf43c 100644 --- a/lab3/impl/gwsynthesis/lab3.prj +++ b/lab3/impl/gwsynthesis/lab3.prj @@ -4,8 +4,9 @@ beta - - + + +