kaltinsoy/verilog
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verilog/project
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k0rrluna cbf97501ea 4-bit ALU
2024-12-14 05:00:35 +03:00
..
addition.v
4-bit ALU
2024-12-14 05:00:35 +03:00
fulladder.v
4-bit ALU
2024-12-14 05:00:35 +03:00
halfadder.v
4-bit ALU
2024-12-14 05:00:35 +03:00
logicUnit
4-bit ALU
2024-12-14 05:00:35 +03:00
logicUnit.v
4-bit ALU
2024-12-14 05:00:35 +03:00
logicUnit.vcd
4-bit ALU
2024-12-14 05:00:35 +03:00
logicUnitTB.v
4-bit ALU
2024-12-14 05:00:35 +03:00
opCode
4-bit ALU
2024-12-14 05:00:35 +03:00
opCode.v
4-bit ALU
2024-12-14 05:00:35 +03:00
opCode.vcd
4-bit ALU
2024-12-14 05:00:35 +03:00
opCodeTB.v
4-bit ALU
2024-12-14 05:00:35 +03:00
overflowDetect.v
4-bit ALU
2024-12-14 05:00:35 +03:00
subtraction
4-bit ALU
2024-12-14 05:00:35 +03:00
subtraction.v
4-bit ALU
2024-12-14 05:00:35 +03:00
subtraction.vcd
4-bit ALU
2024-12-14 05:00:35 +03:00
subtractionTB.v
4-bit ALU
2024-12-14 05:00:35 +03:00