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xorGate

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This commit is contained in:
k0rrluna 2024-12-09 22:57:42 +03:00
parent 6f6f491135
commit 2acbfd9d8d
29 changed files with 1478 additions and 1231 deletions
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0
bit3-ledTest/bit3 → gowin/OldBit3-ledTest/bit3
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0
bit3-ledTest/bit3.vcd → gowin/OldBit3-ledTest/bit3.vcd
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0
bit3-ledTest/bit3Tb.v → gowin/OldBit3-ledTest/bit3Tb.v
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0
bit3-ledTest/fulladder.v → gowin/OldBit3-ledTest/fulladder.v
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0
bit3-ledTest/halfadder.v → gowin/OldBit3-ledTest/halfadder.v
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0
bit3-ledTest/led1 → gowin/OldBit3-ledTest/led1
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0
bit3-ledTest/ledTest.v → gowin/OldBit3-ledTest/ledTest.v
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0
bit3-ledTest/ledTest2.v → gowin/OldBit3-ledTest/ledTest2.v
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0
bit3-ledTest/sub1 → gowin/OldBit3-ledTest/sub1
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47
iverilog/nand2tetris/nands/andGate
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@ -7,46 +7,47 @@
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55a27af99200 .scope module, "andGateTB" "andGateTB" 2 1;
S_0x563ba96be200 .scope module, "andGateTB" "andGateTB" 2 1;
.timescale 0 0;
v0x55a27afaa010_0 .var "A", 0 0;
v0x55a27afaa0e0_0 .var "B", 0 0;
v0x55a27afaa1b0_0 .net "Y", 0 0, L_0x55a27afaa3f0; 1 drivers
S_0x55a27af99390 .scope module, "uut" "andGate" 2 5, 3 1 0, S_0x55a27af99200;
v0x563ba96cf140_0 .var "A_i", 0 0;
v0x563ba96cf210_0 .var "B_i", 0 0;
v0x563ba96cf2e0_0 .net "Y_o", 0 0, L_0x563ba96cf520; 1 drivers
S_0x563ba96be390 .scope module, "uut" "andGate" 2 5, 3 1 0, S_0x563ba96be200;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Y";
L_0x55a27afaa2b0 .functor NAND 1, v0x55a27afaa010_0, v0x55a27afaa0e0_0, C4<1>, C4<1>;
L_0x55a27afaa3f0 .functor NAND 1, L_0x55a27afaa2b0, L_0x55a27afaa2b0, C4<1>, C4<1>;
v0x55a27af61c00_0 .net "A", 0 0, v0x55a27afaa010_0; 1 drivers
v0x55a27afa9d70_0 .net "B", 0 0, v0x55a27afaa0e0_0; 1 drivers
v0x55a27afa9e30_0 .net "Y", 0 0, L_0x55a27afaa3f0; alias, 1 drivers
v0x55a27afa9ed0_0 .net "tempOut", 0 0, L_0x55a27afaa2b0; 1 drivers
.scope S_0x55a27af99200;
.port_info 0 /INPUT 1 "A_i";
.port_info 1 /INPUT 1 "B_i";
.port_info 2 /OUTPUT 1 "Y_o";
L_0x563ba96cf3e0 .functor NAND 1, v0x563ba96cf140_0, v0x563ba96cf210_0, C4<1>, C4<1>;
L_0x563ba96cf520 .functor NAND 1, L_0x563ba96cf3e0, L_0x563ba96cf3e0, C4<1>, C4<1>;
v0x563ba9686c00_0 .net "A_i", 0 0, v0x563ba96cf140_0; 1 drivers
v0x563ba96ceea0_0 .net "B_i", 0 0, v0x563ba96cf210_0; 1 drivers
v0x563ba96cef60_0 .net "Y_o", 0 0, L_0x563ba96cf520; alias, 1 drivers
v0x563ba96cf000_0 .net "nand_out", 0 0, L_0x563ba96cf3e0; 1 drivers
.scope S_0x563ba96be200;
T_0 ;
%vpi_call 2 12 "$dumpfile", "andGate.vcd" {0 0 0};
%vpi_call 2 13 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a27afaa010_0, 0, 1;
%store/vec4 v0x563ba96cf140_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a27afaa0e0_0, 0, 1;
%store/vec4 v0x563ba96cf210_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a27afaa010_0, 0, 1;
%store/vec4 v0x563ba96cf140_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a27afaa0e0_0, 0, 1;
%store/vec4 v0x563ba96cf210_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a27afaa010_0, 0, 1;
%store/vec4 v0x563ba96cf140_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a27afaa0e0_0, 0, 1;
%store/vec4 v0x563ba96cf210_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a27afaa010_0, 0, 1;
%store/vec4 v0x563ba96cf140_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a27afaa0e0_0, 0, 1;
%store/vec4 v0x563ba96cf210_0, 0, 1;
%delay 10, 0;
%vpi_call 2 26 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.

13
iverilog/nand2tetris/nands/andGate.v.orig
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@ -1,13 +0,0 @@
module andGate (
input wire A_i,
input wire B_i,
output wire Y_o
);
wire nand_out;
nand nand1 ( nand_out, A_i, B_i );
nand nand2 ( Y_o, nand_out, nand_out );
endmodule

16
iverilog/nand2tetris/nands/andGate.vcd
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@ -1,5 +1,5 @@
$date
Sun Dec 1 02:41:57 2024
Mon Dec 9 22:41:40 2024
$end
$version
Icarus Verilog
@ -8,14 +8,14 @@ $timescale
1s
$end
$scope module andGateTB $end
$var wire 1 ! Y $end
$var reg 1 " A $end
$var reg 1 # B $end
$var wire 1 ! Y_o $end
$var reg 1 " A_i $end
$var reg 1 # B_i $end
$scope module uut $end
$var wire 1 " A $end
$var wire 1 # B $end
$var wire 1 ! Y $end
$var wire 1 $ tempOut $end
$var wire 1 " A_i $end
$var wire 1 # B_i $end
$var wire 1 ! Y_o $end
$var wire 1 $ nand_out $end
$upscope $end
$upscope $end
$enddefinitions $end

26
iverilog/nand2tetris/nands/andGateTB.v
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@ -1,27 +1,27 @@
module andGateTB ();
reg A, B;
wire Y;
reg A_i, B_i;
wire Y_o;
andGate uut (
.A(A),
.B(B),
.Y(Y)
.A_i(A_i),
.B_i(B_i),
.Y_o(Y_o)
);
initial begin
$dumpfile("andGate.vcd");
$dumpvars;
A = 1'b0;
B = 1'b0;
A_i = 1'b0;
B_i = 1'b0;
#10;
A = 1'b0;
B = 1'b1;
A_i = 1'b0;
B_i = 1'b1;
#10;
A = 1'b1;
B = 1'b0;
A_i = 1'b1;
B_i = 1'b0;
#10;
A = 1'b1;
B = 1'b1;
A_i = 1'b1;
B_i = 1'b1;
#10;
$finish;
end

24
iverilog/nand2tetris/nands/notGate
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@ -7,26 +7,26 @@
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x5628fffa0b60 .scope module, "notGateTB" "notGateTB" 2 1;
S_0x56057d7feb60 .scope module, "notGateTB" "notGateTB" 2 1;
.timescale 0 0;
v0x5628fffafdd0_0 .var "A", 0 0;
v0x5628fffafe70_0 .net "B", 0 0, L_0x5628fffaff40; 1 drivers
S_0x5628fffa0cf0 .scope module, "uut" "notGate" 2 6, 3 1 0, S_0x5628fffa0b60;
v0x56057d80ddd0_0 .var "A_i", 0 0;
v0x56057d80de70_0 .net "B_o", 0 0, L_0x56057d80df40; 1 drivers
S_0x56057d7fecf0 .scope module, "uut" "notGate" 2 6, 3 1 0, S_0x56057d7feb60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /OUTPUT 1 "B";
L_0x5628fffaff40 .functor NAND 1, v0x5628fffafdd0_0, v0x5628fffafdd0_0, C4<1>, C4<1>;
v0x5628fff697f0_0 .net "A", 0 0, v0x5628fffafdd0_0; 1 drivers
v0x5628fff69c00_0 .net "B", 0 0, L_0x5628fffaff40; alias, 1 drivers
.scope S_0x5628fffa0b60;
.port_info 0 /INPUT 1 "A_i";
.port_info 1 /OUTPUT 1 "B_o";
L_0x56057d80df40 .functor NAND 1, v0x56057d80ddd0_0, v0x56057d80ddd0_0, C4<1>, C4<1>;
v0x56057d7c77f0_0 .net "A_i", 0 0, v0x56057d80ddd0_0; 1 drivers
v0x56057d7c7c00_0 .net "B_o", 0 0, L_0x56057d80df40; alias, 1 drivers
.scope S_0x56057d7feb60;
T_0 ;
%vpi_call 2 12 "$dumpfile", "notGate.vcd" {0 0 0};
%vpi_call 2 13 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5628fffafdd0_0, 0, 1;
%store/vec4 v0x56057d80ddd0_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5628fffafdd0_0, 0, 1;
%store/vec4 v0x56057d80ddd0_0, 0, 1;
%delay 10, 0;
%vpi_call 2 18 "$finish" {0 0 0};
%end;

6
iverilog/nand2tetris/nands/notGate.v
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@ -1,7 +1,7 @@
module notGate (
input A,
output B
input A_i,
output B_o
);
nand nand1 (B, A, A);
nand nand1 (B_o, A_i, A_i);
endmodule

10
iverilog/nand2tetris/nands/notGate.vcd
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@ -1,5 +1,5 @@
$date
Sun Dec 1 02:50:52 2024
Mon Dec 9 22:38:49 2024
$end
$version
Icarus Verilog
@ -8,11 +8,11 @@ $timescale
1s
$end
$scope module notGateTB $end
$var wire 1 ! B $end
$var reg 1 " A $end
$var wire 1 ! B_o $end
$var reg 1 " A_i $end
$scope module uut $end
$var wire 1 " A $end
$var wire 1 ! B $end
$var wire 1 " A_i $end
$var wire 1 ! B_o $end
$upscope $end
$upscope $end
$enddefinitions $end

32
iverilog/nand2tetris/nands/notGateTB.v
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@ -1,20 +1,20 @@
module notGateTB ();
module notGateTB;
reg A;
wire B;
reg A_i;
wire B_o;
notGate uut (
.A(A),
.B(B)
);
notGate uut (
.A_i(A_i),
.B_o(B_o)
);
initial begin
$dumpfile("notGate.vcd");
$dumpvars;
A = 1'b0;
#10;
A = 1'b1;
#10;
$finish;
end
initial begin
$dumpfile("notGate.vcd");
$dumpvars;
A_i = 1'b0;
#10;
A_i = 1'b1;
#10;
$finish;
end
endmodule

60
iverilog/nand2tetris/nands/orGate Normal file
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@ -0,0 +1,60 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55778f5946b0 .scope module, "orGateTB" "orGateTB" 2 1;
.timescale 0 0;
v0x55778f5a58d0_0 .var "A_i", 0 0;
v0x55778f5a5970_0 .var "B_i", 0 0;
v0x55778f5a5a40_0 .net "F_o", 0 0, L_0x55778f5a5cf0; 1 drivers
S_0x55778f594840 .scope module, "uut" "orGate" 2 5, 3 1 0, S_0x55778f5946b0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A_i";
.port_info 1 /INPUT 1 "B_i";
.port_info 2 /OUTPUT 1 "F_o";
L_0x55778f5a5b40 .functor NAND 1, v0x55778f5a58d0_0, v0x55778f5a58d0_0, C4<1>, C4<1>;
L_0x55778f5a5c30 .functor NAND 1, v0x55778f5a5970_0, v0x55778f5a5970_0, C4<1>, C4<1>;
L_0x55778f5a5cf0 .functor NAND 1, L_0x55778f5a5b40, L_0x55778f5a5c30, C4<1>, C4<1>;
v0x55778f581720_0 .net "A_i", 0 0, v0x55778f5a58d0_0; 1 drivers
v0x55778f5a5520_0 .net "B_i", 0 0, v0x55778f5a5970_0; 1 drivers
v0x55778f5a55e0_0 .net "F_o", 0 0, L_0x55778f5a5cf0; alias, 1 drivers
v0x55778f5a5680_0 .net "nand1_out", 0 0, L_0x55778f5a5b40; 1 drivers
v0x55778f5a5740_0 .net "nand2_out", 0 0, L_0x55778f5a5c30; 1 drivers
.scope S_0x55778f5946b0;
T_0 ;
%vpi_call 2 12 "$dumpfile", "orGate.vcd" {0 0 0};
%vpi_call 2 13 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55778f5a58d0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55778f5a5970_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55778f5a58d0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55778f5a5970_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55778f5a58d0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55778f5a5970_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55778f5a58d0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55778f5a5970_0, 0, 1;
%delay 10, 0;
%vpi_call 2 18 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"orGateTB.v";
"orGate.v";

43
iverilog/nand2tetris/nands/orGate.vcd Normal file
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@ -0,0 +1,43 @@
$date
Mon Dec 9 22:45:31 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module orGateTB $end
$var wire 1 ! F_o $end
$var reg 1 " A_i $end
$var reg 1 # B_i $end
$scope module uut $end
$var wire 1 " A_i $end
$var wire 1 # B_i $end
$var wire 1 ! F_o $end
$var wire 1 $ nand1_out $end
$var wire 1 % nand2_out $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1%
1$
0#
0"
0!
$end
#10
1!
0%
1#
#20
1%
0$
0#
1"
#30
0%
1#
#40

21
iverilog/nand2tetris/nands/orGateTB.v
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@ -0,0 +1,21 @@
module orGateTB();
reg A_i, B_i;
wire F_o;
orGate uut(
.A_i(A_i),
.B_i(B_i),
.F_o(F_o)
);
initial begin
$dumpfile("orGate.vcd");
$dumpvars;
A_i = 1'b0; B_i = 1'b0; #10;
A_i = 1'b0; B_i = 1'b1; #10;
A_i = 1'b1; B_i = 1'b0; #10;
A_i = 1'b1; B_i = 1'b1; #10;
$finish;
end
endmodule

62
iverilog/nand2tetris/nands/xorGate Normal file
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@ -0,0 +1,62 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55594b700b30 .scope module, "xorGateTB" "xorGateTB" 2 1;
.timescale 0 0;
v0x55594b712090_0 .var "A_i", 0 0;
v0x55594b712130_0 .var "B_i", 0 0;
v0x55594b712200_0 .net "F_o", 0 0, L_0x55594b712570; 1 drivers
S_0x55594b700cc0 .scope module, "uut" "xorGate" 2 5, 3 1 0, S_0x55594b700b30;
.timescale 0 0;
.port_info 0 /INPUT 1 "A_i";
.port_info 1 /INPUT 1 "B_i";
.port_info 2 /OUTPUT 1 "F_o";
L_0x55594b712300 .functor NAND 1, v0x55594b712090_0, v0x55594b712130_0, C4<1>, C4<1>;
L_0x55594b712440 .functor NAND 1, v0x55594b712090_0, L_0x55594b712300, C4<1>, C4<1>;
L_0x55594b712500 .functor NAND 1, v0x55594b712130_0, L_0x55594b712300, C4<1>, C4<1>;
L_0x55594b712570 .functor NAND 1, L_0x55594b712500, L_0x55594b712440, C4<1>, C4<1>;
v0x55594b6eda80_0 .net "A_i", 0 0, v0x55594b712090_0; 1 drivers
v0x55594b711c20_0 .net "B_i", 0 0, v0x55594b712130_0; 1 drivers
v0x55594b711ce0_0 .net "F_o", 0 0, L_0x55594b712570; alias, 1 drivers
v0x55594b711d80_0 .net "nand1_out", 0 0, L_0x55594b712300; 1 drivers
v0x55594b711e40_0 .net "nand2_out", 0 0, L_0x55594b712440; 1 drivers
v0x55594b711f50_0 .net "nand3_out", 0 0, L_0x55594b712500; 1 drivers
.scope S_0x55594b700b30;
T_0 ;
%vpi_call 2 12 "$dumpfile", "xorGate.vcd" {0 0 0};
%vpi_call 2 13 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55594b712090_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55594b712130_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55594b712090_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55594b712130_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55594b712090_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55594b712130_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55594b712090_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55594b712130_0, 0, 1;
%delay 10, 0;
%vpi_call 2 18 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"xorGateTB.v";
"xorGate.v";

14
iverilog/nand2tetris/nands/xorGate.v Normal file
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@ -0,0 +1,14 @@
module xorGate (
input A_i,
input B_i,
output F_o
);
wire nand1_out, nand2_out, nand3_out;
nand nand1(nand1_out, A_i, B_i);
nand nand2(nand2_out, A_i, nand1_out);
nand nand3(nand3_out, B_i, nand1_out);
nand nand4(F_o, nand3_out, nand2_out);
endmodule

48
iverilog/nand2tetris/nands/xorGate.vcd Normal file
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@ -0,0 +1,48 @@
$date
Mon Dec 9 22:56:38 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module xorGateTB $end
$var wire 1 ! F_o $end
$var reg 1 " A_i $end
$var reg 1 # B_i $end
$scope module uut $end
$var wire 1 " A_i $end
$var wire 1 # B_i $end
$var wire 1 ! F_o $end
$var wire 1 $ nand1_out $end
$var wire 1 % nand2_out $end
$var wire 1 & nand3_out $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1&
1%
1$
0#
0"
0!
$end
#10
1!
0&
1#
#20
1&
0%
0#
1"
#30
0!
1%
0$
1&
1#
#40

21
iverilog/nand2tetris/nands/xorGateTB.v Normal file
View File

@ -0,0 +1,21 @@
module xorGateTB();
reg A_i, B_i;
wire F_o;
xorGate uut(
.A_i(A_i),
.B_i(B_i),
.F_o(F_o)
);
initial begin
$dumpfile("xorGate.vcd");
$dumpvars;
A_i = 1'b0; B_i = 1'b0; #10;
A_i = 1'b0; B_i = 1'b1; #10;
A_i = 1'b1; B_i = 1'b0; #10;
A_i = 1'b1; B_i = 1'b1; #10;
$finish;
end
endmodule

26
iverilog/tobb/lab2/Fulladder.v
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@ -1,26 +0,0 @@
module Fulladder (
input A,
input B,
input Cin,
output S,
output Cout
);
wire AxB, AnB1, AnB2;
halfadder h1 (
.A(A),
.B(B),
.Sum(AxB),
.Carry(AnB2)
);
halfadder h2 (
.A(AxB),
.B(Cin),
.Sum(S),
.Carry(AnB1)
);
or o1 (.Y(Cout), .A(AnB1), .B(AnB2));
endmodule

2
iverilog/tobb/lab2/fdmp.vcd
View File

@ -1,5 +1,5 @@
$date
Tue Oct 8 14:05:40 2024
Sun Dec 8 20:51:56 2024
$end
$version
Icarus Verilog

114
iverilog/tobb/lab2/fulladder
View File

@ -7,115 +7,115 @@
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x557fe3a27ae0 .scope module, "fulladdertb" "fulladdertb" 2 1;
S_0x56122b07fae0 .scope module, "fulladdertb" "fulladdertb" 2 1;
.timescale 0 0;
v0x557fe3a3b940_0 .var "r1", 0 0;
v0x557fe3a3ba30_0 .var "r2", 0 0;
v0x557fe3a3bb40_0 .var "r3", 0 0;
v0x557fe3a3bc30_0 .net "w1", 0 0, L_0x557fe3a3bf40; 1 drivers
v0x557fe3a3bd20_0 .net "w2", 0 0, L_0x557fe3a3c1a0; 1 drivers
S_0x557fe3a27c70 .scope module, "uut" "fullAdder" 2 6, 3 1 0, S_0x557fe3a27ae0;
v0x56122b093940_0 .var "r1", 0 0;
v0x56122b093a30_0 .var "r2", 0 0;
v0x56122b093b40_0 .var "r3", 0 0;
v0x56122b093c30_0 .net "w1", 0 0, L_0x56122b093f40; 1 drivers
v0x56122b093d20_0 .net "w2", 0 0, L_0x56122b0941a0; 1 drivers
S_0x56122b07fc70 .scope module, "uut" "fulladder" 2 6, 3 1 0, S_0x56122b07fae0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Cin";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "Cout";
L_0x557fe3a3c1a0 .functor OR 1, L_0x557fe3a3c080, L_0x557fe3a3be80, C4<0>, C4<0>;
v0x557fe3a3b290_0 .net "A", 0 0, v0x557fe3a3b940_0; 1 drivers
v0x557fe3a3b350_0 .net "AnB1", 0 0, L_0x557fe3a3c080; 1 drivers
v0x557fe3a3b420_0 .net "AnB2", 0 0, L_0x557fe3a3be80; 1 drivers
v0x557fe3a3b520_0 .net "AxB", 0 0, L_0x557fe3a3be10; 1 drivers
v0x557fe3a3b610_0 .net "B", 0 0, v0x557fe3a3ba30_0; 1 drivers
v0x557fe3a3b700_0 .net "Cin", 0 0, v0x557fe3a3bb40_0; 1 drivers
v0x557fe3a3b7a0_0 .net "Cout", 0 0, L_0x557fe3a3c1a0; alias, 1 drivers
v0x557fe3a3b840_0 .net "S", 0 0, L_0x557fe3a3bf40; alias, 1 drivers
S_0x557fe3a22df0 .scope module, "h1" "halfadder" 3 9, 4 1 0, S_0x557fe3a27c70;
L_0x56122b0941a0 .functor OR 1, L_0x56122b094080, L_0x56122b093e80, C4<0>, C4<0>;
v0x56122b093290_0 .net "A", 0 0, v0x56122b093940_0; 1 drivers
v0x56122b093350_0 .net "AnB1", 0 0, L_0x56122b094080; 1 drivers
v0x56122b093420_0 .net "AnB2", 0 0, L_0x56122b093e80; 1 drivers
v0x56122b093520_0 .net "AxB", 0 0, L_0x56122b093e10; 1 drivers
v0x56122b093610_0 .net "B", 0 0, v0x56122b093a30_0; 1 drivers
v0x56122b093700_0 .net "Cin", 0 0, v0x56122b093b40_0; 1 drivers
v0x56122b0937a0_0 .net "Cout", 0 0, L_0x56122b0941a0; alias, 1 drivers
v0x56122b093840_0 .net "S", 0 0, L_0x56122b093f40; alias, 1 drivers
S_0x56122b07adf0 .scope module, "h1" "halfadder" 3 11, 4 1 0, S_0x56122b07fc70;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x557fe3a3be10 .functor XOR 1, v0x557fe3a3b940_0, v0x557fe3a3ba30_0, C4<0>, C4<0>;
L_0x557fe3a3be80 .functor AND 1, v0x557fe3a3b940_0, v0x557fe3a3ba30_0, C4<1>, C4<1>;
v0x557fe3a23070_0 .net "A", 0 0, v0x557fe3a3b940_0; alias, 1 drivers
v0x557fe3a3a970_0 .net "B", 0 0, v0x557fe3a3ba30_0; alias, 1 drivers
v0x557fe3a3aa30_0 .net "C", 0 0, L_0x557fe3a3be80; alias, 1 drivers
v0x557fe3a3ab00_0 .net "S", 0 0, L_0x557fe3a3be10; alias, 1 drivers
S_0x557fe3a3ac70 .scope module, "h2" "halfadder" 3 10, 4 1 0, S_0x557fe3a27c70;
L_0x56122b093e10 .functor XOR 1, v0x56122b093940_0, v0x56122b093a30_0, C4<0>, C4<0>;
L_0x56122b093e80 .functor AND 1, v0x56122b093940_0, v0x56122b093a30_0, C4<1>, C4<1>;
v0x56122b07b070_0 .net "A", 0 0, v0x56122b093940_0; alias, 1 drivers
v0x56122b092970_0 .net "B", 0 0, v0x56122b093a30_0; alias, 1 drivers
v0x56122b092a30_0 .net "C", 0 0, L_0x56122b093e80; alias, 1 drivers
v0x56122b092b00_0 .net "S", 0 0, L_0x56122b093e10; alias, 1 drivers
S_0x56122b092c70 .scope module, "h2" "halfadder" 3 13, 4 1 0, S_0x56122b07fc70;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x557fe3a3bf40 .functor XOR 1, L_0x557fe3a3be10, v0x557fe3a3bb40_0, C4<0>, C4<0>;
L_0x557fe3a3c080 .functor AND 1, L_0x557fe3a3be10, v0x557fe3a3bb40_0, C4<1>, C4<1>;
v0x557fe3a3aee0_0 .net "A", 0 0, L_0x557fe3a3be10; alias, 1 drivers
v0x557fe3a3afb0_0 .net "B", 0 0, v0x557fe3a3bb40_0; alias, 1 drivers
v0x557fe3a3b050_0 .net "C", 0 0, L_0x557fe3a3c080; alias, 1 drivers
v0x557fe3a3b120_0 .net "S", 0 0, L_0x557fe3a3bf40; alias, 1 drivers
.scope S_0x557fe3a27ae0;
L_0x56122b093f40 .functor XOR 1, L_0x56122b093e10, v0x56122b093b40_0, C4<0>, C4<0>;
L_0x56122b094080 .functor AND 1, L_0x56122b093e10, v0x56122b093b40_0, C4<1>, C4<1>;
v0x56122b092ee0_0 .net "A", 0 0, L_0x56122b093e10; alias, 1 drivers
v0x56122b092fb0_0 .net "B", 0 0, v0x56122b093b40_0; alias, 1 drivers
v0x56122b093050_0 .net "C", 0 0, L_0x56122b094080; alias, 1 drivers
v0x56122b093120_0 .net "S", 0 0, L_0x56122b093f40; alias, 1 drivers
.scope S_0x56122b07fae0;
T_0 ;
%vpi_call 2 15 "$dumpfile", "fdmp.vcd" {0 0 0};
%vpi_call 2 16 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%vpi_call 2 25 "$display", v0x557fe3a3bc30_0 {0 0 0};
%vpi_call 2 26 "$display", v0x557fe3a3bd20_0 {0 0 0};
%vpi_call 2 25 "$display", v0x56122b093c30_0 {0 0 0};
%vpi_call 2 26 "$display", v0x56122b093d20_0 {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.

16
iverilog/tobb/lab2/fulladder.v Normal file
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@ -0,0 +1,16 @@
module fulladder (
input A,
input B,
input Cin,
output S,
output Cout
);
wire AxB, AnB1, AnB2;
halfadder h1 (A,B,AxB,AnB2);
halfadder h2 (AxB,Cin,S,AnB1);
or o1 (Cout,AnB1,AnB2);
endmodule

2
iverilog/tobb/lab2/fulladdertb.v
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@ -3,7 +3,7 @@ module fulladdertb ();
reg r1, r2, r3;
wire w1, w2;
FullAdder uut(
fulladder uut(
.A(r1),
.B(r2),
.Cin(r3),