30 lines
416 B
Verilog
30 lines
416 B
Verilog
module andGateTB ();
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reg A_i, B_i;
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wire Y_o;
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andGate uut (
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.A_i(A_i),
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.B_i(B_i),
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.Y_o(Y_o)
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);
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initial begin
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$dumpfile("andGate.vcd");
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$dumpvars;
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A_i = 1'b0;
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B_i = 1'b0;
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#10;
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A_i = 1'b0;
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B_i = 1'b1;
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#10;
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A_i = 1'b1;
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B_i = 1'b0;
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#10;
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A_i = 1'b1;
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B_i = 1'b1;
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#10;
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$finish;
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end
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endmodule
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