33 lines
476 B
Verilog
33 lines
476 B
Verilog
module ledTest (
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input[1:0] v1, v2,
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output [5:0] L14
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);
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wire[3:0] sum;
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bit3adder adder(
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.A({1'b0, v1}),
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.B({1'b0, v2}),
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.C(sum)
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);
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always @(*) begin
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L14 = 6'b000_000;
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if(sum == 4'd0) begin
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L14 = 6'b000_000;
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end
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else if(sum == 4'd1)
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L14 = 6'b000_001;
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else if(sum == 4'd2)
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L14 = 6'b000_011;
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else if(sum == 4'd3)
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L14 = 6'b000_111;
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else if(sum == 4'd4)
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L14 = 6'b001_111;
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end
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endmodule |