27 lines
344 B
Verilog
27 lines
344 B
Verilog
module Fulladder (
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input A,
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input B,
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input Cin,
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output S,
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output Cout
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);
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wire AxB, AnB1, AnB2;
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halfadder h1 (
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.A(A),
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.B(B),
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.Sum(AxB),
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.Carry(AnB2)
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);
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halfadder h2 (
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.A(AxB),
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.B(Cin),
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.Sum(S),
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.Carry(AnB1)
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);
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or o1 (.Y(Cout), .A(AnB1), .B(AnB2));
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endmodule
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