44 lines
457 B
Plaintext
44 lines
457 B
Plaintext
$date
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Mon Dec 9 22:45:31 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module orGateTB $end
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$var wire 1 ! F_o $end
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$var reg 1 " A_i $end
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$var reg 1 # B_i $end
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$scope module uut $end
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$var wire 1 " A_i $end
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$var wire 1 # B_i $end
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$var wire 1 ! F_o $end
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$var wire 1 $ nand1_out $end
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$var wire 1 % nand2_out $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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1%
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1$
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0#
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0"
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0!
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$end
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#10
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1!
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0%
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1#
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#20
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1%
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0$
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0#
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1"
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#30
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0%
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1#
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#40
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