kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

formatter test

Browse Source
This commit is contained in:
k0rrluna 2024-12-07 05:46:58 +03:00
parent f0551ce34f
commit 6f6f491135
2 changed files with 16 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
iverilog/nand2tetris/nands/andGate.v
View File

@ -1,7 +1,7 @@
module andGate (
input wire A_i,
input wire B_i,
output wire Y_o
input wire A_i,
input wire B_i,
output wire Y_o
);
wire nand_out;

13
iverilog/nand2tetris/nands/andGate.v.orig Normal file
View File

@ -0,0 +1,13 @@
module andGate (
input wire A_i,
input wire B_i,
output wire Y_o
);
wire nand_out;
nand nand1 ( nand_out, A_i, B_i );
nand nand2 ( Y_o, nand_out, nand_out );
endmodule