lab7

gowin/bttn/bttn.gprj

@@ -9,7 +9,6 @@
         <File path="src/BinaryToBCD.v" type="file.verilog" enable="1"/>
         <File path="src/addition.v" type="file.verilog" enable="1"/>
         <File path="src/arithmeticUnit.v" type="file.verilog" enable="1"/>
-        <File path="src/bttn.v" type="file.verilog" enable="1"/>
         <File path="src/dabble.v" type="file.verilog" enable="1"/>
         <File path="src/fulladder.v" type="file.verilog" enable="1"/>
         <File path="src/fullsubtraction.v" type="file.verilog" enable="1"/>
@@ -20,6 +19,7 @@
         <File path="src/opCode.v" type="file.verilog" enable="1"/>
         <File path="src/selector.v" type="file.verilog" enable="1"/>
         <File path="src/subtraction.v" type="file.verilog" enable="1"/>
-        <File path="src/bttn.cst" type="file.cst" enable="1"/>
+        <File path="src/top.v" type="file.verilog" enable="1"/>
+        <File path="src/top.cst" type="file.cst" enable="1"/>
     </FileList>
 </Project>

gowin/bttn/bttn.gprj.user

@@ -7,6 +7,8 @@
         <Process ID="Pnr" State="2"/>
         <Process ID="Gao" State="2"/>
         <Process ID="Rtl_Gao" State="2"/>
+        <Process ID="Gvio" State="2"/>
+        <Process ID="Place" State="2"/>
     </FlowState>
     <ResultFileList>
         <ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/bttn.vg"/>
@@ -20,5 +22,6 @@
         <ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/bttn_syn.rpt.html"/>
         <ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/bttn_syn_rsc.xml"/>
     </ResultFileList>
-    <Ui>000000ff00000001fd00000002000000000000018e0000051efc0200000001fc000000630000051e0000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff00000000000000000000000300000ab000000145fc0100000001fc0000000000000ab0000000e700fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000009e00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000e700ffffff0000091a0000051e00000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000bdffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c007301000001a5ffffffff0000000000000000</Ui>
+    <Ui>000000ff00000001fd00000002000000000000018e0000025dfc0200000001fc000000370000025d0000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000078000000145fc0100000001fc0000000000000780000000a100fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100ffffff000005ee0000025d00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000000000280043006f00720065002e0054006f006f006c006200610072002e00500072006f00630065007300730100000245ffffffff0000000000000000</Ui>
+    <FpUi></FpUi>
 </UserConfig>

gowin/bttn/bttn.gprj.userZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/bttn.gprjZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/bttn_process_config.json

@@ -1,88 +0,0 @@
-{
- "BACKGROUND_PROGRAMMING" : "off",
- "COMPRESS" : false,
- "CPU" : false,
- "CRC_CHECK" : true,
- "Clock_Route_Order" : 0,
- "Correct_Hold_Violation" : true,
- "DONE" : false,
- "DOWNLOAD_SPEED" : "default",
- "Disable_Insert_Pad" : false,
- "ENABLE_CTP" : false,
- "ENABLE_MERGE_MODE" : false,
- "ENCRYPTION_KEY" : false,
- "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
- "ERROR_DECTION_AND_CORRECTION" : false,
- "ERROR_DECTION_ONLY" : false,
- "ERROR_INJECTION" : false,
- "EXTERNAL_MASTER_CONFIG_CLOCK" : false,
- "Enable_DSRM" : false,
- "FORMAT" : "binary",
- "FREQUENCY_DIVIDER" : "",
- "Generate_Constraint_File_of_Ports" : false,
- "Generate_IBIS_File" : false,
- "Generate_Plain_Text_Timing_Report" : false,
- "Generate_Post_PNR_Simulation_Model_File" : false,
- "Generate_Post_Place_File" : false,
- "Generate_SDF_File" : false,
- "Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
- "Global_Freq" : "default",
- "GwSyn_Loop_Limit" : 2000,
- "HOTBOOT" : false,
- "I2C" : false,
- "I2C_SLAVE_ADDR" : "00",
- "IncludePath" : [
-
- ],
- "Incremental_Compile" : "",
- "Initialize_Primitives" : false,
- "JTAG" : false,
- "MODE_IO" : false,
- "MSPI" : false,
- "MSPI_JUMP" : false,
- "MULTIBOOT_ADDRESS_WIDTH" : "24",
- "MULTIBOOT_MODE" : "Normal",
- "MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
- "MULTIJUMP_ADDRESS_WIDTH" : "24",
- "MULTIJUMP_MODE" : "Normal",
- "MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
- "Multi_Boot" : true,
- "OUTPUT_BASE_NAME" : "bttn",
- "POWER_ON_RESET_MONITOR" : true,
- "PRINT_BSRAM_VALUE" : true,
- "PROGRAM_DONE_BYPASS" : false,
- "PlaceInRegToIob" : true,
- "PlaceIoRegToIob" : true,
- "PlaceOutRegToIob" : true,
- "Place_Option" : "0",
- "Process_Configuration_Verion" : "1.0",
- "Promote_Physical_Constraint_Warning_to_Error" : true,
- "READY" : false,
- "RECONFIG_N" : false,
- "Ram_RW_Check" : false,
- "Replicate_Resources" : false,
- "Report_Auto-Placed_Io_Information" : false,
- "Route_Maxfan" : 23,
- "Route_Option" : "0",
- "Run_Timing_Driven" : true,
- "SECURE_MODE" : false,
- "SECURITY_BIT" : true,
- "SEU_HANDLER" : false,
- "SEU_HANDLER_CHECKSUM" : false,
- "SEU_HANDLER_MODE" : "auto",
- "SSPI" : false,
- "STOP_SEU_HANDLER" : false,
- "Show_All_Warnings" : false,
- "Synthesize_tool" : "GowinSyn",
- "TclPre" : "",
- "TopModule" : "",
- "USERCODE" : "default",
- "Unused_Pin" : "As_input_tri_stated_with_pull_up",
- "VCCAUX" : 3.3,
- "VCCX" : "3.3",
- "VHDL_Standard" : "VHDL_Std_1993",
- "Verilog_Standard" : "Vlg_Std_2001",
- "WAKE_UP" : "0",
- "show_all_warnings" : false,
- "turn_off_bg" : false
-}

gowin/bttn/impl/bttn_process_config.jsonZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/gwsynthesis/bttn.log

@@ -1,130 +0,0 @@
-GowinSynthesis start
-Running parser ...
-Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v'
-Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v'
-Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v'
-Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v'
-Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v'
-Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v'
-Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v'
-Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v'
-Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v'
-Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v'
-Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v'
-Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v'
-Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v'
-Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v'
-Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v'
-Compiling module 'bttn'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v":1)
-Compiling module 'ALU'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":1)
-Compiling module 'opCode'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v":1)
-Compiling module 'arithmeticUnit'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v":1)
-Compiling module 'addition'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":1)
-Compiling module 'fulladder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":1)
-Compiling module 'halfadder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v":1)
-Compiling module 'subtraction'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":1)
-Compiling module 'fullsubtraction'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":1)
-Compiling module 'halfsubtraction'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v":1)
-Compiling module 'logicUnit'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v":1)
-Compiling module 'multiplier'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":1)
-Compiling module 'BinaryToBCD'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":1)
-Compiling module 'dabble'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v":1)
-Compiling module 'selector'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v":1)
-NOTE  (EX0101) : Current top module is "bttn"
-[5%] Running netlist conversion ...
-Running device independent optimization ...
-[10%] Optimizing Phase 0 completed
-[15%] Optimizing Phase 1 completed
-[25%] Optimizing Phase 2 completed
-Running inference ...
-[30%] Inferring Phase 0 completed
-[40%] Inferring Phase 1 completed
-[50%] Inferring Phase 2 completed
-[55%] Inferring Phase 3 completed
-Running technical mapping ...
-[60%] Tech-Mapping Phase 0 completed
-[65%] Tech-Mapping Phase 1 completed
-[75%] Tech-Mapping Phase 2 completed
-[80%] Tech-Mapping Phase 3 completed
-[90%] Tech-Mapping Phase 4 completed
-WARN  (NL0002) : The module "ALU" instantiated to "a1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v":13)
-WARN  (NL0002) : The module "arithmeticUnit" instantiated to "aU" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":20)
-WARN  (NL0002) : The module "addition" instantiated to "a1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v":13)
-WARN  (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
-WARN  (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
-WARN  (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
-WARN  (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
-WARN  (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
-WARN  (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
-WARN  (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
-WARN  (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
-WARN  (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
-WARN  (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
-WARN  (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
-WARN  (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
-WARN  (NL0002) : The module "subtraction" instantiated to "s1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v":14)
-WARN  (NL0002) : The module "fullsubtraction" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":11)
-WARN  (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
-WARN  (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
-WARN  (NL0002) : The module "fullsubtraction" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":12)
-WARN  (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
-WARN  (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
-WARN  (NL0002) : The module "fullsubtraction" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":13)
-WARN  (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
-WARN  (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
-WARN  (NL0002) : The module "fullsubtraction" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":14)
-WARN  (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
-WARN  (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
-WARN  (NL0002) : The module "BinaryToBCD" instantiated to "btod1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":76)
-WARN  (NL0002) : The module "dabble" instantiated to "d1t" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":21)
-WARN  (NL0002) : The module "dabble" instantiated to "d2u" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":30)
-WARN  (NL0002) : The module "dabble" instantiated to "d3v" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":39)
-WARN  (NL0002) : The module "dabble" instantiated to "d4w" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":48)
-WARN  (NL0002) : The module "dabble" instantiated to "d5x" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":57)
-WARN  (NL0002) : The module "dabble" instantiated to "d6y" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":66)
-WARN  (NL0002) : The module "dabble" instantiated to "d7z" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":75)
-WARN  (NL0002) : The module "logicUnit" instantiated to "lU" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":21)
-WARN  (NL0002) : The module "multiplier" instantiated to "mU" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":22)
-WARN  (NL0002) : The module "addition" instantiated to "add0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":33)
-WARN  (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
-WARN  (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
-WARN  (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
-WARN  (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
-WARN  (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
-WARN  (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
-WARN  (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
-WARN  (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
-WARN  (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
-WARN  (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
-WARN  (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
-WARN  (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
-WARN  (NL0002) : The module "addition" instantiated to "add1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":49)
-WARN  (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
-WARN  (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
-WARN  (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
-WARN  (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
-WARN  (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
-WARN  (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
-WARN  (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
-WARN  (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
-WARN  (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
-WARN  (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
-WARN  (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
-WARN  (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
-WARN  (NL0002) : The module "addition" instantiated to "add2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":65)
-WARN  (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
-WARN  (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
-WARN  (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
-WARN  (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
-WARN  (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
-WARN  (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
-WARN  (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
-WARN  (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
-WARN  (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
-WARN  (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
-WARN  (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
-WARN  (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
-WARN  (NL0002) : The module "opCode" instantiated to "opCd" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":18)
-[95%] Generate netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg" completed
-[100%] Generate report file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn_syn.rpt.html" completed
-GowinSynthesis finish

gowin/bttn/impl/gwsynthesis/bttn.logZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/gwsynthesis/bttn.prj

@@ -1,33 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!DOCTYPE gowin-synthesis-project>
-<Project>
-    <Version>beta</Version>
-    <Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
-    <FileList>
-        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v" type="verilog"/>
-        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v" type="verilog"/>
-        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v" type="verilog"/>
-        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v" type="verilog"/>
-        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v" type="verilog"/>
-        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v" type="verilog"/>
-        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v" type="verilog"/>
-        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v" type="verilog"/>
-        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v" type="verilog"/>
-        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v" type="verilog"/>
-        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v" type="verilog"/>
-        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v" type="verilog"/>
-        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v" type="verilog"/>
-        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v" type="verilog"/>
-        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v" type="verilog"/>
-    </FileList>
-    <OptionList>
-        <Option type="disable_insert_pad" value="0"/>
-        <Option type="global_freq" value="100.000"/>
-        <Option type="looplimit" value="2000"/>
-        <Option type="output_file" value="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg"/>
-        <Option type="print_all_synthesis_warning" value="0"/>
-        <Option type="ram_rw_check" value="0"/>
-        <Option type="verilog_language" value="verilog-2001"/>
-        <Option type="vhdl_language" value="vhdl-1993"/>
-    </OptionList>
-</Project>

gowin/bttn/impl/gwsynthesis/bttn.prjZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/gwsynthesis/bttn.vg

@@ -1,465 +0,0 @@
-//
-//Written by GowinSynthesis
-//Tool Version "V1.9.9.03 Education (64-bit)"
-//Mon Jan 20 18:30:58 2025
-
-//Source file index table:
-//file0 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v"
-//file1 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v"
-//file2 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v"
-//file3 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v"
-//file4 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v"
-//file5 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v"
-//file6 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v"
-//file7 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v"
-//file8 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v"
-//file9 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v"
-//file10 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/logicUnit.v"
-//file11 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v"
-//file12 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/opCode.v"
-//file13 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/selector.v"
-//file14 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v"
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-`pragma protect author="default"
-`pragma protect author_info="default"
-`pragma protect encrypt_agent="GOWIN"
-`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
-
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
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gowin/bttn/impl/gwsynthesis/bttn.vgZone.Identifier

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gowin/bttn/impl/gwsynthesis/bttn_syn.rpt.html

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-<title>synthesis Report</title>
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-<div id="catalog_wrapper">
-<div id="catalog">
-<ul>
-<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
-<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
-<li><a href="#resource" style=" font-size: 16px;">Resource</a>
-<ul>
-<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
-<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
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-<div id="content">
-<h1><a name="about">Synthesis Messages</a></h1>
-<table class="summary_table">
-<tr>
-<td class="label">Report Title</td>
-<td>GowinSynthesis Report</td>
-</tr>
-<tr>
-<td class="label">Design File</td>
-<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v<br>
-\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v<br>
-\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v<br>
-\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v<br>
-\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v<br>
-\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v<br>
-\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v<br>
-\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v<br>
-\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v<br>
-\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v<br>
-\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v<br>
-\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v<br>
-\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v<br>
-\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v<br>
-\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v<br>
-</td>
-</tr>
-<tr>
-<td class="label">GowinSynthesis Constraints File</td>
-<td>---</td>
-</tr>
-<tr>
-<td class="label">Tool Version</td>
-<td>V1.9.9.03 Education (64-bit)</td>
-</tr>
-<tr>
-<td class="label">Part Number</td>
-<td>GW2A-LV18PG256C8/I7</td>
-</tr>
-<tr>
-<td class="label">Device</td>
-<td>GW2A-18</td>
-</tr>
-<tr>
-<td class="label">Device Version</td>
-<td>C</td>
-</tr>
-<tr>
-<td class="label">Created Time</td>
-<td>Mon Jan 20 18:30:58 2025
-</td>
-</tr>
-<tr>
-<td class="label">Legal Announcement</td>
-<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
-</tr>
-</table>
-<h1><a name="summary">Synthesis Details</a></h1>
-<table class="summary_table">
-<tr>
-<td class="label">Top Level Module</td>
-<td>bttn</td>
-</tr>
-<tr>
-<td class="label">Synthesis Process</td>
-<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.315s, Peak memory usage = 175.059MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 175.059MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 175.059MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 175.059MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 175.059MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 175.059MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 175.059MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 175.059MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 175.059MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 175.059MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 175.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 3s, Peak memory usage = 206.203MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 206.203MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 206.203MB<br/></td>
-</tr>
-<tr>
-<td class="label">Total Time and Memory Usage</td>
-<td>CPU time = 0h 0m 2s, Elapsed time = 0h 0m 3s, Peak memory usage = 206.203MB</td>
-</tr>
-</table>
-<h1><a name="resource">Resource</a></h1>
-<h2><a name="usage">Resource Usage Summary</a></h2>
-<table class="summary_table">
-<tr>
-<td class="label"><b>Resource</b></td>
-<td><b>Usage</b></td>
-</tr>
-<tr>
-<td class="label"><b>I/O Port </b></td>
-<td>28</td>
-</tr>
-<tr>
-<td class="label"><b>I/O Buf </b></td>
-<td>28</td>
-</tr>
-<tr>
-<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
-<td>14</td>
-</tr>
-<tr>
-<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
-<td>14</td>
-</tr>
-<tr>
-<td class="label"><b>LUT </b></td>
-<td>141</td>
-</tr>
-<tr>
-<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
-<td>16</td>
-</tr>
-<tr>
-<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
-<td>36</td>
-</tr>
-<tr>
-<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
-<td>89</td>
-</tr>
-</table>
-<h2><a name="utilization">Resource Utilization Summary</a></h2>
-<table class="summary_table">
-<tr>
-<td class="label"><b>Resource</b></td>
-<td><b>Usage</b></td>
-<td><b>Utilization</b></td>
-</tr>
-<tr>
-<td class="label">Logic</td>
-<td>141(141 LUT, 0 ALU) / 20736</td>
-<td><1%</td>
-</tr>
-<tr>
-<td class="label">Register</td>
-<td>0 / 16173</td>
-<td>0%</td>
-</tr>
-<tr>
-<td class="label">&nbsp&nbsp--Register as Latch</td>
-<td>0 / 16173</td>
-<td>0%</td>
-</tr>
-<tr>
-<td class="label">&nbsp&nbsp--Register as FF</td>
-<td>0 / 16173</td>
-<td>0%</td>
-</tr>
-<tr>
-<td class="label">BSRAM</td>
-<td>0 / 46</td>
-<td>0%</td>
-</tr>
-</table>
-</div><!-- content -->
-</div><!-- main_wrapper -->
-</body>
-</html>

gowin/bttn/impl/gwsynthesis/bttn_syn.rpt.htmlZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/gwsynthesis/bttn_syn_resource.html

@@ -1,56 +0,0 @@
-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
-<html>
-<head>
-<title>Hierarchy Module Resource</title>
-<style type="text/css">
-body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
-div#main_wrapper{ width: 100%; }
-h1 {text-align: center; }
-h1 {margin-top: 36px; }
-table, th, td { border: 1px solid #aaa; }
-table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
-th, td { align = "center"; padding: 5px 2px 5px 5px; }
-th { color: #fff; font-weight: bold; background-color: #0084ff; }
-table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
-</style>
-</head>
-<body>
-<div id="main_wrapper">
-<div id="content">
-<h1>Hierarchy Module Resource</h1>
-<table>
-<tr>
-<th class="label">MODULE NAME</th>
-<th class="label">REG NUMBER</th>
-<th class="label">ALU NUMBER</th>
-<th class="label">LUT NUMBER</th>
-<th class="label">DSP NUMBER</th>
-<th class="label">BSRAM NUMBER</th>
-<th class="label">SSRAM NUMBER</th>
-<th class="label">ROM16 NUMBER</th>
-</tr>
-<tr>
-<td class="label">bttn (//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v)</td>
-<td align = "center">-</td>
-<td align = "center">-</td>
-<td align = "center">13</td>
-<td align = "center">-</td>
-<td align = "center">-</td>
-<td align = "center">-</td>
-<td align = "center">-</td>
-</tr>
-<td class="label">&nbsp&nbsp&nbsp&nbsp|--s1
- (//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v)</td>
-<td align = "center">-</td>
-<td align = "center">-</td>
-<td align = "center">128</td>
-<td align = "center">-</td>
-<td align = "center">-</td>
-<td align = "center">-</td>
-<td align = "center">-</td>
-</tr>
-</table>
-</div><!-- content -->
-</div><!-- main_wrapper -->
-</body>
-</html>

gowin/bttn/impl/gwsynthesis/bttn_syn_resource.htmlZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/gwsynthesis/bttn_syn_rsc.xml

@@ -1,4 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Module name="bttn" Lut="13" T_Lut="141(13)">
-    <SubModule name="s1" Lut="128" T_Lut="128(128)"/>
-</Module>

gowin/bttn/impl/gwsynthesis/bttn_syn_rsc.xmlZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/pnr/bttn.binxZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/pnr/bttn.binZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/pnr/bttn.dbZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/pnr/bttn.fsZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/pnr/bttn.log

@@ -1,29 +0,0 @@
-Reading netlist file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg"
-Parsing netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg" completed
-Processing netlist completed
-Reading constraint file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst"
-Physical Constraint parsed completed
-Running placement......
-[10%] Placement Phase 0 completed
-[20%] Placement Phase 1 completed
-[30%] Placement Phase 2 completed
-[50%] Placement Phase 3 completed
-Running routing......
-[60%] Routing Phase 0 completed
-[70%] Routing Phase 1 completed
-[80%] Routing Phase 2 completed
-[90%] Routing Phase 3 completed
-Running timing analysis......
-[95%] Timing analysis completed
-Placement and routing completed
-Bitstream generation in progress......
-Bitstream generation completed
-Running power analysis......
-[100%] Power analysis completed
-Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.power.html" completed
-Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.pin.html" completed
-Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.rpt.html" completed
-Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.rpt.txt" completed
-Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.tr.html" completed
-Mon Jan 20 18:31:08 2025
-

gowin/bttn/impl/pnr/bttn.logZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/pnr/bttn.pin.htmlZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/pnr/bttn.power.html

@@ -1,269 +0,0 @@
-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//ENhttp://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
-<html>
-<head>
-<title>Power Analysis Report</title>
-<style type="text/css">
-body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
-div#main_wrapper { width: 100%; }
-div#content { margin-left: 350px; margin-right: 30px; }
-div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
-div#catalog ul { list-style-type: none; }
-div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
-div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
-div#catalog a:visited { color: #0084ff; }
-div#catalog a:hover { color: #fff; background: #0084ff; }
-hr { margin-top: 30px; margin-bottom: 30px; }
-h1, h3 { text-align: center; }
-h1 {margin-top: 50px; }
-table, th, td {white-space:pre;  border: 1px solid #aaa; }
-table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
-th, td { padding: 5px 5px 5px 5px; }
-th { color: #fff; font-weight: bold; background-color: #0084ff; }
-table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
-table.thermal_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
-table.Configure_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
-table.detail_table th.label {  min-width: 8%; width: 8%; }
-</style>
-</head>
-<body>
-<div id="main_wrapper">
-<div id="catalog_wrapper">
-<div id="catalog">
-<ul>
-<li><a href="#Message" style=" font-size: 16px;">Power Messages</a>
-<ul>
-<li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li>
-</ul>
-</li>
-<li><a href="#Summary" style=" font-size: 16px;">Power Summary</a>
-<ul>
-<li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li>
-<li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li>
-<li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li>
-</ul>
-</li>
-<li><a href="#Detail" style=" font-size: 16px;">Power Details</a>
-<ul>
-<li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li>
-<li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li>
-<li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li>
-</ul>
-</li>
-</ul>
-</div><!-- catalog -->
-</div><!-- catalog_wrapper -->
-<div id="content">
-<h1><a name="Message">Power Messages</a></h1>
-<table class="summary_table">
-<tr>
-<td class="label">Report Title</td>
-<td>Power Analysis Report</td>
-</tr>
-<tr>
-<td class="label">Design File</td>
-<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg</td>
-</tr>
-<tr>
-<td class="label">Physical Constraints File</td>
-<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst</td>
-</tr>
-<tr>
-<td class="label">Timing Constraints File</td>
-<td>---</td>
-</tr>
-<tr>
-<td class="label">Tool Version</td>
-<td>V1.9.9.03 Education (64-bit)</td>
-</tr>
-<tr>
-<td class="label">Part Number</td>
-<td>GW2A-LV18PG256C8/I7</td>
-</tr>
-<tr>
-<td class="label">Device</td>
-<td>GW2A-18</td>
-</tr>
-<tr>
-<td class="label">Device Version</td>
-<td>C</td>
-</tr>
-<tr>
-<td class="label">Created Time</td>
-<td>Mon Jan 20 18:31:05 2025
-</td>
-</tr>
-<tr>
-<td class="label">Legal Announcement</td>
-<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
-</tr>
-</table>
-<h2><a name="Configure_Info">Configure Information:</a></h2>
-<table class="summary_table">
-<tr>
-<td class="label">Grade</td>
-<td>Commercial</td>
-</tr>
-<tr>
-<td class="label">Process</td>
-<td>Typical</td>
-</tr>
-<tr>
-<td class="label">Ambient Temperature</td>
-<td>25.000
-</tr>
-<tr>
-<td class="label">Use Custom Theta JA</td>
-<td>false</td>
-</tr>
-<tr>
-<td class="label">Heat Sink</td>
-<td>None</td>
-</tr>
-<tr>
-<td class="label">Air Flow</td>
-<td>LFM_0</td>
-</tr>
-<tr>
-<td class="label">Use Custom Theta SA</td>
-<td>false</td>
-</tr>
-<tr>
-<td class="label">Board Thermal Model</td>
-<td>None</td>
-</tr>
-<tr>
-<td class="label">Use Custom Theta JB</td>
-<td>false</td>
-</tr>
-<tr>
-<td class="label">Related Vcd File</td>
-<td></td>
-</tr>
-<tr>
-<td class="label">Related Saif File</td>
-<td></td>
-</tr>
-<tr>
-<td class="label">Filter Glitches</td>
-<td>false</td>
-</tr>
-<tr>
-<td class="label">Default IO Toggle Rate</td>
-<td>0.125</td>
-</tr>
-<tr>
-<td class="label">Default Remain Toggle Rate</td>
-<td>0.125</td>
-</tr>
-</table>
-<h1><a name="Summary">Power Summary</a></h1>
-<h2><a name="Power_Info">Power Information:</a></h2>
-<table class="summary_table">
-<tr>
-<td class="label">Total Power (mW)</td>
-<td>124.522</td>
-</tr>
-<tr>
-<td class="label">Quiescent Power (mW)</td>
-<td>121.169</td>
-</tr>
-<tr>
-<td class="label">Dynamic Power (mW)</td>
-<td>3.353</td>
-</tr>
-</table>
-<h2><a name="Thermal_Info">Thermal Information:</a></h2>
-<table class="summary_table">
-<tr>
-<td class="label">Junction Temperature</td>
-<td>28.987</td>
-</tr>
-<tr>
-<td class="label">Theta JA</td>
-<td>32.020</td>
-</tr>
-<tr>
-<td class="label">Max Allowed Ambient Temperature</td>
-<td>81.013</td>
-</tr>
-</table>
-<h2><a name="Supply_Summary">Supply Information:</a></h2>
-<table class="summary_table">
-<tr>
-<th class="label">Voltage Source</th>
-<th class="label">Voltage</th>
-<th class="label">Dynamic Current(mA)</th>
-<th class="label">Quiescent Current(mA)</th>
-<th class="label">Power(mW)</th>
-</tr>
-<tr>
-<td>VCC</td>
-<td>1.000</td>
-<td>0.552</td>
-<td>69.981</td>
-<td>70.533</td>
-</tr>
-<tr>
-<td>VCCX</td>
-<td>3.300</td>
-<td>0.552</td>
-<td>15.000</td>
-<td>51.322</td>
-</tr>
-<tr>
-<td>VCCIO18</td>
-<td>1.800</td>
-<td>0.544</td>
-<td>0.938</td>
-<td>2.668</td>
-</tr>
-</table>
-<h1><a name="Detail">Power Details</a></h1>
-<h2><a name="By_Block_Type">Power By Block Type:</a></h2>
-<table class="detail_table">
-<tr>
-<th class="label">Block Type</th>
-<th class="label">Total Power(mW)</th>
-<th class="label">Static Power(mW)</th>
-<th class="label">Average Toggle Rate(millions of transitions/sec)</th>
-</tr>
-<tr>
-<td>IO</td>
-<td>8.544
-<td>5.191
-<td>6.250
-</tr>
-</table>
-<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
-<table class="detail_table">
-<tr>
-<th class="label">Hierarchy Entity</th>
-<th class="label">Total Power(mW)</th>
-<th class="label">Block Dynamic Power(mW)</th>
-</tr>
-<tr>
-<td>bttn</td>
-<td>0.000</td>
-<td>0.000(0.000)</td>
-<tr>
-<td>bttn/s1/</td>
-<td>0.000</td>
-<td>0.000(0.000)</td>
-</table>
-<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
-<table class="detail_table">
-<tr>
-<th class="label">Clock Domain</th>
-<th class="label">Clock Frequency(Mhz)</th>
-<th class="label">Total Dynamic Power(mW)</th>
-</tr>
-<tr>
-<td>NO CLOCK DOMAIN</td>
-<td>0.000</td>
-<td>0.000</td>
-</tr>
-</table>
-</div><!-- content -->
-</div><!-- main_wrapper -->
-</body>
-</html>

gowin/bttn/impl/pnr/bttn.power.htmlZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/pnr/bttn.rpt.htmlZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/pnr/bttn.rpt.txt

@@ -1,366 +0,0 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
-//All rights reserved.
-
-
-1. PnR Messages
-
-  <Report Title>: PnR Report
-  <Design File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg
-  <Physical Constraints File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst
-  <Timing Constraints File>: ---
-  <Tool Version>: V1.9.9.03 Education (64-bit)
-  <Part Number>: GW2A-LV18PG256C8/I7
-  <Device>: GW2A-18
-  <Device Version>: C
-  <Created Time>:Mon Jan 20 18:31:08 2025
-
-
-2. PnR Details
-
-  Running placement:
-    Placement Phase 0: CPU time = 0h 0m 0.025s, Elapsed time = 0h 0m 0.025s
-    Placement Phase 1: CPU time = 0h 0m 0.346s, Elapsed time = 0h 0m 0.345s
-    Placement Phase 2: CPU time = 0h 0m 0.008s, Elapsed time = 0h 0m 0.008s
-    Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
-    Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
- Running routing:
-    Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
-    Routing Phase 1: CPU time = 0h 0m 0.178s, Elapsed time = 0h 0m 0.177s
-    Routing Phase 2: CPU time = 0h 0m 0.228s, Elapsed time = 0h 0m 0.228s
-    Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
-    Total Routing: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.405s
- Generate output files:
-    CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s
-
- Total Time and Memory Usage: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 433MB
-
-
-3. Resource Usage Summary
-
-  ----------------------------------------------------------
-  Resources                   | Usage
-  ----------------------------------------------------------
-  Logic                       | 141/20736  <1%
-    --LUT,ALU,ROM16           | 141(141 LUT, 0 ALU, 0 ROM16)
-    --SSRAM(RAM16)            | 0
-  Register                    | 0/16173  0%
-    --Logic Register as Latch | 0/15552  0%
-    --Logic Register as FF    | 0/15552  0%
-    --I/O Register as Latch   | 0/621  0%
-    --I/O Register as FF      | 0/621  0%
-  CLS                         | 75/10368  <1%
-  I/O Port                    | 28
-  I/O Buf                     | 28
-    --Input Buf               | 14
-    --Output Buf              | 14
-    --Inout Buf               | 0
-  IOLOGIC                     | 0%
-  BSRAM                       | 0%
-  DSP                         | 0%
-  PLL                         | 0/4  0%
-  DCS                         | 0/8  0%
-  DQCE                        | 0/24  0%
-  OSC                         | 0/1  0%
-  CLKDIV                      | 0/8  0%
-  DLLDLY                      | 0/8  0%
-  DQS                         | 0/9  0%
-  DHCEN                       | 0/16  0%
-  ==========================================================
-
-
-
-4. I/O Bank Usage Summary
-
-  -----------------------
-  I/O Bank  | Usage       
-  -----------------------
-  bank 0   | 1/29(3%)    
-  bank 1   | 5/20(25%)   
-  bank 2   | 2/20(10%)   
-  bank 3   | 8/32(25%)   
-  bank 4   | 2/36(5%)    
-  bank 5   | 0/36(0%)    
-  bank 6   | 2/18(11%)   
-  bank 7   | 8/16(50%)   
-  =======================
-
-
-5. Global Clock Usage Summary
-
-  -------------------------------
-  Global Clock  | Usage       
-  -------------------------------
-  PRIMARY       | 0/8(0%)
-  LW            | 0/8(0%)
-  GCLK_PIN      | 1/8(13%)
-  PLL           | 0/4(0%)
-  CLKDIV        | 0/8(0%)
-  DLLDLY        | 0/8(0%)
-  ===============================
-
-
-6. Global Clock Signals
-
-  -------------------------------------------
-  Signal         | Global Clock   | Location
-  -------------------------------------------
-  ===========================================
-
-
-7. Pinout by Port Name
-
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Port Name   | Diff Pair | Loc./Bank     | Constraint | Dir.  | Site     | IO Type    | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref       | Single Resistor | Diff Resistor | BankVccio 
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-A[0]        |           | A11/7         | Y          | in    | IOL15[A] | LVCMOS18   | NA    | NONE      | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8       
-A[1]        |           | N6/3          | Y          | in    | IOR51[A] | LVCMOS18   | NA    | NONE      | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8       
-A[2]        |           | E15/1         | Y          | in    | IOT44[B] | LVCMOS18   | NA    | NONE      | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8       
-A[3]        |           | L9/3          | Y          | in    | IOR40[B] | LVCMOS18   | NA    | NONE      | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8       
-B[0]        |           | B11/7         | Y          | in    | IOL13[A] | LVCMOS18   | NA    | NONE      | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8       
-B[1]        |           | D11/7         | Y          | in    | IOL22[A] | LVCMOS18   | NA    | NONE      | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8       
-B[2]        |           | N7/3          | Y          | in    | IOR47[B] | LVCMOS18   | NA    | NONE      | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8       
-B[3]        |           | N8/3          | Y          | in    | IOR40[A] | LVCMOS18   | NA    | NONE      | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8       
-opCodeA[0]  |           | T5/4          | Y          | in    | IOB54[B] | LVCMOS18   | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8       
-opCodeA[1]  |           | T4/4          | Y          | in    | IOB45[B] | LVCMOS18   | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8       
-opCodeA[2]  |           | E8/6          | Y          | in    | IOL45[B] | LVCMOS18   | NA    | UP        | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8       
-select[0]   |           | A15/7         | Y          | in    | IOL2[B]  | LVCMOS18   | NA    | UP        | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8       
-select[1]   |           | A14/7         | Y          | in    | IOL8[B]  | LVCMOS18   | NA    | UP        | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8       
-Cin         |           | E9/6          | Y          | in    | IOL38[B] | LVCMOS18   | NA    | UP        | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8       
-leds[0]     |           | L16/1         | Y          | out   | IOT34[A] | LVCMOS18   | 8     | NONE      | NA        | NA         | OFF        | NA         | NA              | NA            | 1.8       
-leds[1]     |           | L14/1         | Y          | out   | IOT34[B] | LVCMOS18   | 8     | NONE      | NA        | NA         | OFF        | NA         | NA              | NA            | 1.8       
-Y[0]        |           | P6/3          | Y          | out   | IOR53[A] | LVCMOS18   | 8     | NONE      | NA        | NA         | OFF        | NA         | OFF             | NA            | 1.8       
-Y[1]        |           | T7/3          | Y          | out   | IOR29[A] | LVCMOS18   | 8     | NONE      | NA        | NA         | OFF        | NA         | OFF             | NA            | 1.8       
-Y[2]        |           | P8/3          | Y          | out   | IOR42[A] | LVCMOS18   | 8     | NONE      | NA        | NA         | OFF        | NA         | OFF             | NA            | 1.8       
-Y[3]        |           | P9/3          | Y          | out   | IOR38[B] | LVCMOS18   | 8     | NONE      | NA        | NA         | OFF        | NA         | OFF             | NA            | 1.8       
-Y[4]        |           | T11/2         | Y          | out   | IOR24[A] | LVCMOS18   | 8     | NONE      | NA        | NA         | OFF        | NA         | OFF             | NA            | 1.8       
-Y[5]        |           | T12/2         | Y          | out   | IOR17[B] | LVCMOS18   | 8     | NONE      | NA        | NA         | OFF        | NA         | OFF             | NA            | 1.8       
-Y[6]        |           | M14/1         | Y          | out   | IOT40[A] | LVCMOS18   | 8     | NONE      | NA        | NA         | OFF        | NA         | NA              | NA            | 1.8       
-Y[7]        |           | J14/0         | Y          | out   | IOT22[B] | LVCMOS18   | 8     | NONE      | NA        | NA         | OFF        | NA         | NA              | NA            | 1.8       
-Y[8]        |           | D14/1         | Y          | out   | IOT44[A] | LVCMOS18   | 8     | NONE      | NA        | NA         | OFF        | NA         | NA              | NA            | 1.8       
-Y[9]        |           | B14/7         | Y          | out   | IOL2[A]  | LVCMOS18   | 8     | NONE      | NA        | NA         | OFF        | NA         | OFF             | NA            | 1.8       
-Y[10]       |           | B13/7         | Y          | out   | IOL8[A]  | LVCMOS18   | 8     | NONE      | NA        | NA         | OFF        | NA         | OFF             | NA            | 1.8       
-Y[11]       |           | B12/7         | Y          | out   | IOL7[B]  | LVCMOS18   | 8     | NONE      | NA        | NA         | OFF        | NA         | OFF             | NA            | 1.8       
-===================================================================================================================================================================================================================
-
-
-
-
-8. All Package Pins
-
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Loc./Bank| Signal      | Dir.  | Site     | IO Type  | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref       | Single Resistor | Diff Resistor | Bank Vccio
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-L15/0    | -           | in    | IOT2[A]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-D16/0    | -           | in    | IOT4[A]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-E14/0    | -           | in    | IOT4[B]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-C16/0    | -           | in    | IOT5[A]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-D15/0    | -           | in    | IOT5[B]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-E16/0    | -           | in    | IOT6[A]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-F15/0    | -           | in    | IOT6[B]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-F13/0    | -           | in    | IOT8[A]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-G12/0    | -           | in    | IOT8[B]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-F14/0    | -           | in    | IOT9[A]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-F16/0    | -           | in    | IOT9[B]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-F12/0    | -           | in    | IOT12[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-G13/0    | -           | in    | IOT12[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-G15/0    | -           | in    | IOT13[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-G14/0    | -           | in    | IOT13[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-G11/0    | -           | in    | IOT14[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-H12/0    | -           | in    | IOT14[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-G16/0    | -           | in    | IOT16[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-H15/0    | -           | in    | IOT16[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-H13/0    | -           | in    | IOT18[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-J12/0    | -           | in    | IOT18[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-H14/0    | -           | in    | IOT20[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-H16/0    | -           | in    | IOT20[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-J16/0    | -           | in    | IOT22[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-J14/0    | Y[7]        | out   | IOT22[B] | LVCMOS18 | 8     | NONE      | NA        | NA         | OFF        | NA         | NA              | NA            | 1.8  
-J15/0    | -           | in    | IOT24[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-K16/0    | -           | in    | IOT24[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-H11/0    | -           | in    | IOT27[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-J13/0    | -           | in    | IOT27[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-K14/1    | -           | in    | IOT30[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-K15/1    | -           | in    | IOT30[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-J11/1    | -           | in    | IOT32[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-L12/1    | -           | in    | IOT32[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-L16/1    | leds[0]     | out   | IOT34[A] | LVCMOS18 | 8     | NONE      | NA        | NA         | OFF        | NA         | NA              | NA            | 1.8  
-L14/1    | leds[1]     | out   | IOT34[B] | LVCMOS18 | 8     | NONE      | NA        | NA         | OFF        | NA         | NA              | NA            | 1.8  
-K13/1    | -           | in    | IOT36[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-K12/1    | -           | in    | IOT36[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-K11/1    | -           | in    | IOT38[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-L13/1    | -           | in    | IOT38[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-M14/1    | Y[6]        | out   | IOT40[A] | LVCMOS18 | 8     | NONE      | NA        | NA         | OFF        | NA         | NA              | NA            | 1.8  
-M15/1    | -           | in    | IOT40[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-D14/1    | Y[8]        | out   | IOT44[A] | LVCMOS18 | 8     | NONE      | NA        | NA         | OFF        | NA         | NA              | NA            | 1.8  
-E15/1    | A[2]        | in    | IOT44[B] | LVCMOS18 | NA    | NONE      | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-N15/1    | -           | in    | IOT48[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-P16/1    | -           | in    | IOT48[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-N16/1    | -           | in    | IOT52[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-N14/1    | -           | in    | IOT52[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-P15/1    | -           | in    | IOT54[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-R16/1    | -           | in    | IOT54[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-A4/5     | -           | in    | IOB2[A]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-C5/5     | -           | in    | IOB2[B]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-D6/5     | -           | in    | IOB3[A]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-E7/5     | -           | in    | IOB3[B]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-A3/5     | -           | in    | IOB4[A]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-B4/5     | -           | in    | IOB4[B]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-A5/5     | -           | in    | IOB7[A]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-B6/5     | -           | in    | IOB7[B]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-B1/5     | -           | in    | IOB8[A]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-C2/5     | -           | in    | IOB8[B]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-D3/5     | -           | in    | IOB9[A]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-D1/5     | -           | in    | IOB9[B]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-E2/5     | -           | in    | IOB12[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-E3/5     | -           | in    | IOB12[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-B3/5     | -           | in    | IOB13[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-A2/5     | -           | in    | IOB13[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-C1/5     | -           | in    | IOB14[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-D2/5     | -           | in    | IOB14[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-E1/5     | -           | in    | IOB16[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-F2/5     | -           | in    | IOB16[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-F4/5     | -           | in    | IOB18[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-G6/5     | -           | in    | IOB18[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-F3/5     | -           | in    | IOB19[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-F1/5     | -           | in    | IOB19[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-G5/5     | -           | in    | IOB20[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-G4/5     | -           | in    | IOB20[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-G2/5     | -           | in    | IOB21[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-G3/5     | -           | in    | IOB21[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-F5/5     | -           | in    | IOB22[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-H6/5     | -           | in    | IOB22[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-G1/5     | -           | in    | IOB24[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-H2/5     | -           | in    | IOB24[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-H4/5     | -           | in    | IOB26[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-J6/5     | -           | in    | IOB26[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-J1/5     | -           | in    | IOB27[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-J3/5     | -           | in    | IOB27[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-L2/4     | -           | in    | IOB30[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-M1/4     | -           | in    | IOB30[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-H3/4     | -           | in    | IOB32[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-H1/4     | -           | in    | IOB32[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-J2/4     | -           | in    | IOB34[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-K1/4     | -           | in    | IOB34[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-H5/4     | -           | in    | IOB35[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-J4/4     | -           | in    | IOB35[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-K3/4     | -           | in    | IOB36[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-K2/4     | -           | in    | IOB36[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-J5/4     | -           | in    | IOB37[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-K6/4     | -           | in    | IOB37[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-L1/4     | -           | in    | IOB38[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-L3/4     | -           | in    | IOB38[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-K4/4     | -           | in    | IOB39[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-L5/4     | -           | in    | IOB39[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-K5/4     | -           | in    | IOB40[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-L4/4     | -           | in    | IOB40[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-N2/4     | -           | in    | IOB41[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-P1/4     | -           | in    | IOB41[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-M3/4     | -           | in    | IOB42[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-N1/4     | -           | in    | IOB42[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-M2/4     | -           | in    | IOB43[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-N3/4     | -           | in    | IOB43[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-R1/4     | -           | in    | IOB44[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-P2/4     | -           | in    | IOB44[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-P4/4     | -           | in    | IOB45[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-T4/4     | opCodeA[1]  | in    | IOB45[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-R3/4     | -           | in    | IOB48[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-T2/4     | -           | in    | IOB48[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-P5/4     | -           | in    | IOB50[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-R5/4     | -           | in    | IOB50[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-R4/4     | -           | in    | IOB52[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-T3/4     | -           | in    | IOB52[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-R6/4     | -           | in    | IOB54[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-T5/4     | opCodeA[0]  | in    | IOB54[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-B14/7    | Y[9]        | out   | IOL2[A]  | LVCMOS18 | 8     | NONE      | NA        | NA         | OFF        | NA         | OFF             | NA            | 1.8  
-A15/7    | select[0]   | in    | IOL2[B]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8  
-C12/7    | -           | in    | IOL7[A]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-B12/7    | Y[11]       | out   | IOL7[B]  | LVCMOS18 | 8     | NONE      | NA        | NA         | OFF        | NA         | OFF             | NA            | 1.8  
-B13/7    | Y[10]       | out   | IOL8[A]  | LVCMOS18 | 8     | NONE      | NA        | NA         | OFF        | NA         | OFF             | NA            | 1.8  
-A14/7    | select[1]   | in    | IOL8[B]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8  
-F10/7    | -           | in    | IOL11[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-B11/7    | B[0]        | in    | IOL13[A] | LVCMOS18 | NA    | NONE      | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8  
-A12/7    | -           | in    | IOL13[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-A11/7    | A[0]        | in    | IOL15[A] | LVCMOS18 | NA    | NONE      | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8  
-C11/7    | -           | in    | IOL15[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-D10/7    | -           | in    | IOL17[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-E10/7    | -           | in    | IOL17[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-D11/7    | B[1]        | in    | IOL22[A] | LVCMOS18 | NA    | NONE      | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8  
-A9/7     | -           | in    | IOL27[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-C9/7     | -           | in    | IOL27[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-C8/6     | -           | in    | IOL29[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-A8/6     | -           | in    | IOL29[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-F9/6     | -           | in    | IOL31[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-E11/6    | -           | in    | IOL31[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-B9/6     | -           | in    | IOL33[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-A10/6    | -           | in    | IOL33[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-F8/6     | -           | in    | IOL35[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-D9/6     | -           | in    | IOL35[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-D8/6     | -           | in    | IOL38[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-E9/6     | Cin         | in    | IOL38[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8  
-B7/6     | -           | in    | IOL40[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-C7/6     | -           | in    | IOL40[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-F7/6     | -           | in    | IOL45[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-E8/6     | opCodeA[2]  | in    | IOL45[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8  
-C4/6     | -           | in    | IOL47[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-B5/6     | -           | in    | IOL47[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-E6/6     | -           | in    | IOL53[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-D7/6     | -           | in    | IOL53[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-T15/2    | -           | in    | IOR7[A]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-R14/2    | -           | in    | IOR7[B]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-P12/2    | -           | in    | IOR8[A]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-T13/2    | -           | in    | IOR8[B]  | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-R12/2    | -           | in    | IOR11[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-P13/2    | -           | in    | IOR11[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-R11/2    | -           | in    | IOR17[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-T12/2    | Y[5]        | out   | IOR17[B] | LVCMOS18 | 8     | NONE      | NA        | NA         | OFF        | NA         | OFF             | NA            | 1.8  
-R13/2    | -           | in    | IOR20[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-T14/2    | -           | in    | IOR20[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-M10/2    | -           | in    | IOR22[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-N11/2    | -           | in    | IOR22[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-T11/2    | Y[4]        | out   | IOR24[A] | LVCMOS18 | 8     | NONE      | NA        | NA         | OFF        | NA         | OFF             | NA            | 1.8  
-P11/2    | -           | in    | IOR24[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-C6/2     | -           | out   | IOR25[A] | LVCMOS18 | 8     | UP        | NA        | NA         | OFF        | NA         | NA              | NA            | 1.8  
-B8/2     | -           | in    | IOR25[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-A7/2     | -           | in    | IOR26[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-A6/2     | -           | in    | IOR26[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-N10/2    | -           | in    | IOR27[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-M11/2    | -           | in    | IOR27[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-T7/3     | Y[1]        | out   | IOR29[A] | LVCMOS18 | 8     | NONE      | NA        | NA         | OFF        | NA         | OFF             | NA            | 1.8  
-R8/3     | -           | in    | IOR29[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-M16/3    | -           | in    | IOR30[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-B16/3    | -           | in    | IOR30[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-C15/3    | -           | in    | IOR31[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-B10/3    | -           | in    | IOR31[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-A13/3    | -           | in    | IOR32[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-C13/3    | -           | in    | IOR32[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-P10/3    | -           | in    | IOR33[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-R10/3    | -           | in    | IOR33[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-M9/3     | -           | in    | IOR34[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-L10/3    | -           | in    | IOR34[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-R9/3     | -           | in    | IOR35[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-T10/3    | -           | in    | IOR35[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-M8/3     | -           | in    | IOR36[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-N9/3     | -           | in    | IOR36[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-T9/3     | -           | in    | IOR38[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-P9/3     | Y[3]        | out   | IOR38[B] | LVCMOS18 | 8     | NONE      | NA        | NA         | OFF        | NA         | OFF             | NA            | 1.8  
-C10/3    | -           | in    | IOR39[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-N8/3     | B[3]        | in    | IOR40[A] | LVCMOS18 | NA    | NONE      | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8  
-L9/3     | A[3]        | in    | IOR40[B] | LVCMOS18 | NA    | NONE      | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8  
-P8/3     | Y[2]        | out   | IOR42[A] | LVCMOS18 | 8     | NONE      | NA        | NA         | OFF        | NA         | OFF             | NA            | 1.8  
-T8/3     | -           | in    | IOR42[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-M6/3     | -           | in    | IOR44[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-L8/3     | -           | in    | IOR44[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-M7/3     | -           | in    | IOR47[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-N7/3     | B[2]        | in    | IOR47[B] | LVCMOS18 | NA    | NONE      | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8  
-R7/3     | -           | in    | IOR49[A] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-P7/3     | -           | in    | IOR49[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-N6/3     | A[1]        | in    | IOR51[A] | LVCMOS18 | NA    | NONE      | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8  
-P6/3     | Y[0]        | out   | IOR53[A] | LVCMOS18 | 8     | NONE      | NA        | NA         | OFF        | NA         | OFF             | NA            | 1.8  
-T6/3     | -           | in    | IOR53[B] | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-========================================================================================================================================================================================
-
-

gowin/bttn/impl/pnr/bttn.rpt.txtZone.Identifier

@@ -1,2 +0,0 @@
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gowin/bttn/impl/pnr/bttn.timing_pathsZone.Identifier

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-<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#High_Fanout_Nets_Report" style=" font-size: 14px;" target="mainFrame">High Fanout Nets Report</a></li>
-<!--High_Fanout_Nets_Report end-->
-<!--Route_Congestions_Report begin-->
-<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Route_Congestions_Report" style=" font-size: 14px;" target="mainFrame">Route Congestions Report</a></li>
-<!--Route_Congestions_Report end-->
-<!--Timing_Exceptions_Report begin-->
-<li><div class="triangle" onclick="onClick(this)"></div><a href="bttn_tr_content.html#Timing_Exceptions_Report" style=" font-size: 14px;" target="mainFrame">Timing Exceptions Report</a>
-<ul>
-<!--Setup_Analysis_Exceptions begin-->
-<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Setup_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Setup Analysis Report</a>
-</li>
-<!--Setup_Analysis_Exceptions end-->
-<!--Hold_Analysis_Exceptions begin-->
-<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Hold_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Hold Analysis Report</a>
-</li>
-<!--Hold_Analysis_Exceptions end-->
-<!--Recovery_Analysis_Exceptions begin-->
-<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Recovery_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Recovery Analysis Report</a>
-</li>
-<!--Recovery_Analysis_Exceptions end-->
-<!--Removal_Analysis_Exceptions begin-->
-<li><div class="triangle_fake" onclick="onClick(this)"></div><a href="bttn_tr_content.html#Removal_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Removal Analysis Report</a>
-</li>
-<!--Removal_Analysis_Exceptions end-->
-</ul>
-</li>
-<!--Timing_Exceptions_Report end-->
-<!--SDC_Report begin-->
-<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#SDC_Report" style=" font-size: 14px;" target="mainFrame">Timing Constraints Report</a></li>
-<!--SDC_Report end-->
-</ul>
-</li>
-<!-- details end-->
-</ul>
-</div><!-- catalog -->
-</div><!-- catalog_wrapper -->
-</body>
-</html>

gowin/bttn/impl/pnr/bttn_tr_cata.htmlZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/pnr/bttn_tr_content.html

@@ -1,257 +0,0 @@
-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
-<html>
-<head>
-<title>Timing Analysis Report</title>
-<style type="text/css">
-@import url(../temp/style.css);
-body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
-div#content { width: 100%; margin: }
-hr { margin-top: 30px; margin-bottom: 30px; }
-h1, h3 { text-align: center; }
-h1 {margin-top: 50px; }
-table, th, td {white-space:pre; border: 1px solid #aaa; }
-table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
-th, td { padding: 5px 5px 5px 5px; }
-th { color: #fff; font-weight: bold; background-color: #0084ff; }
-table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
-table.detail_table th.label {  min-width: 8%; width: 8%; }
-</style>
-</head>
-<body>
-<div id="content">
-<h1><a name="Message">Timing Messages</a></h1>
-<table class="summary_table">
-<tr>
-<td class="label">Report Title</td>
-<td>Timing Analysis Report</td>
-</tr>
-<tr>
-<td class="label">Design File</td>
-<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg</td>
-</tr>
-<tr>
-<td class="label">Physical Constraints File</td>
-<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst</td>
-</tr>
-<tr>
-<td class="label">Timing Constraint File</td>
-<td>---</td>
-</tr>
-<tr>
-<td class="label">Tool Version</td>
-<td>V1.9.9.03 Education (64-bit)</td>
-</tr>
-<tr>
-<td class="label">Part Number</td>
-<td>GW2A-LV18PG256C8/I7</td>
-</tr>
-<tr>
-<td class="label">Device</td>
-<td>GW2A-18</td>
-</tr>
-<tr>
-<td class="label">Device Version</td>
-<td>C</td>
-</tr>
-<tr>
-<td class="label">Created Time</td>
-<td>Mon Jan 20 18:31:08 2025
-</td>
-</tr>
-<tr>
-<td class="label">Legal Announcement</td>
-<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
-</tr>
-</table>
-<h1><a name="Summary">Timing Summaries</a></h1>
-<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
-<table class="summary_table">
-<tr>
-<td class="label">Setup Delay Model</td>
-<td>Slow 0.95V 85C C8/I7</td>
-</tr>
-<tr>
-<td class="label">Hold Delay Model</td>
-<td>Fast 1.05V 0C C8/I7</td>
-</tr>
-<tr>
-<td class="label">Numbers of Paths Analyzed</td>
-<td>158</td>
-</tr>
-<tr>
-<td class="label">Numbers of Endpoints Analyzed</td>
-<td>14</td>
-</tr>
-<tr>
-<td class="label">Numbers of Falling Endpoints</td>
-<td>0</td>
-</tr>
-<tr>
-<td class="label">Numbers of Setup Violated Endpoints</td>
-<td>0</td>
-</tr>
-<tr>
-<td class="label">Numbers of Hold Violated Endpoints</td>
-<td>0</td>
-</tr>
-</table>
-<h2><a name="Clock_Report">Clock Summary:</a></h2>
-<table class="detail_table">
-<tr>
-<th class="label">Clock Name</th>
-<th class="label">Type</th>
-<th class="label">Period</th>
-<th class="label">Frequency(MHz)</th>
-<th class="label">Rise</th>
-<th class="label">Fall</th>
-<th class="label">Source</th>
-<th class="label">Master</th>
-<th class="label">Objects</th>
-</tr>
-</table>
-<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
-<table>
-<tr>
-<th>NO.</th>
-<th>Clock Name</th>
-<th>Constraint</th>
-<th>Actual Fmax</th>
-<th>Logic Level</th>
-<th>Entity</th>
-</tr>
-</table>
-<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
-<table class="detail_table">
-<tr>
-<th class="label">Clock Name</th>
-<th class="label">Analysis Type</th>
-<th class="label">Endpoints TNS</th>
-<th class="label">Number of Endpoints</th>
-</tr>
-</table>
-<h1><a name="Detail">Timing Details</a></h1>
-<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
-<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
-<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
-<h4>Nothing to report!</h4>
-<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
-<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
-<h4>Nothing to report!</h4>
-<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
-<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
-<h4>Nothing to report!</h4>
-<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
-<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
-<h4>Nothing to report!</h4>
-<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
-<table class="detail_table">
-<tr>
-<th class="label">Number</th>
-<th class="label">Slack</th>
-<th class="label">Actual Width</th>
-<th class="label">Required Width</th>
-<th class="label">Type</th>
-<th class="label">Clock</th>
-<th class="label">Objects</th>
-</tr>
-<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
-<h4>Nothing to report!</h4>
-</table>
-<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
-<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
-<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
-<h4>No setup paths to report!</h4>
-<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
-<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
-<h4>No hold paths to report!</h4>
-<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
-<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
-<h4>No recovery paths to report!</h4>
-<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
-<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
-<h4>No removal paths to report!</h4>
-<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
-<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
-<h4>Nothing to report!</h4>
-<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
-<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
-<table class="detail_table">
-<tr>
-<th class="label">FANOUT</th>
-<th class="label">NET NAME</th>
-<th class="label">WORST SLACK</th>
-<th class="label">MAX DELAY</th>
-</tr>
-</table>
-<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
-<h4>Report Command:report_route_congestion -max_grids 10</h4>
-<table class="detail_table">
-<tr>
-<th class="label">GRID LOC</th>
-<th class="label">ROUTE CONGESTIONS</th>
-</tr>
-<tr>
-<td>R27C30</td>
-<td>43.06%</td>
-</tr>
-<tr>
-<td>R29C29</td>
-<td>43.06%</td>
-</tr>
-<tr>
-<td>R27C29</td>
-<td>40.28%</td>
-</tr>
-<tr>
-<td>R26C29</td>
-<td>33.33%</td>
-</tr>
-<tr>
-<td>R26C30</td>
-<td>31.94%</td>
-</tr>
-<tr>
-<td>R29C28</td>
-<td>30.56%</td>
-</tr>
-<tr>
-<td>R29C30</td>
-<td>29.17%</td>
-</tr>
-<tr>
-<td>R27C28</td>
-<td>26.39%</td>
-</tr>
-<tr>
-<td>R27C31</td>
-<td>25.00%</td>
-</tr>
-<tr>
-<td>R26C28</td>
-<td>25.00%</td>
-</tr>
-</table>
-<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
-<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
-<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
-<h4>No timing exceptions to report!</h4>
-<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
-<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
-<h4>No timing exceptions to report!</h4>
-<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
-<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
-<h4>No timing exceptions to report!</h4>
-<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
-<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
-<h4>No timing exceptions to report!</h4>
-<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
-<table class="detail_table">
-<tr>
-<th class="label">SDC Command Type</th>
-<th class="label">State</th>
-<th class="label">Detail Command</th>
-</tr>
-</table>
-</div><!-- content -->
-</body>
-</html>

gowin/bttn/impl/pnr/bttn_tr_content.htmlZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/pnr/cmd.do

@@ -1,13 +0,0 @@
--d \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg
--p GW2A-18C-PBGA256-8
--pn GW2A-LV18PG256C8/I7
--cst \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst
--cfg \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\device.cfg
--bit
--tr
--ph
--timing
--cst_error
--correct_hold 1
--route_maxfan 23
--global_freq 100.000

gowin/bttn/impl/pnr/cmd.doZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/pnr/device.cfg

@@ -1,21 +0,0 @@
-set JTAG regular_io = false
-set SSPI regular_io = false
-set MSPI regular_io = false
-set READY regular_io = false
-set DONE regular_io = false
-set I2C regular_io = false
-set RECONFIG_N regular_io = false
-set CRC_check = true
-set compress = false
-set encryption = false
-set security_bit_enable = true
-set bsram_init_fuse_print = true
-set background_programming = off
-set secure_mode = false
-set program_done_bypass = false
-set wake_up = 0
-set format = binary
-set power_on_reset_monitor = true
-set multiboot_spi_flash_address = 0x00000000
-set vccx = 3.3
-set unused_pin = default

gowin/bttn/impl/pnr/device.cfgZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/temp/rtl_parser.result

@@ -1,702 +0,0 @@
-[
- {
-  "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
-  "InstLine" : 1,
-  "InstName" : "bttn",
-  "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
-  "ModuleLine" : 1,
-  "ModuleName" : "bttn",
-  "SubInsts" : [
-   {
-    "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
-    "InstLine" : 13,
-    "InstName" : "a1",
-    "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
-    "ModuleLine" : 1,
-    "ModuleName" : "ALU",
-    "SubInsts" : [
-     {
-      "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
-      "InstLine" : 18,
-      "InstName" : "opCd",
-      "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/opCode.v",
-      "ModuleLine" : 1,
-      "ModuleName" : "opCode"
-     },
-     {
-      "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
-      "InstLine" : 20,
-      "InstName" : "aU",
-      "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
-      "ModuleLine" : 1,
-      "ModuleName" : "arithmeticUnit",
-      "SubInsts" : [
-       {
-        "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
-        "InstLine" : 13,
-        "InstName" : "a1",
-        "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
-        "ModuleLine" : 1,
-        "ModuleName" : "addition",
-        "SubInsts" : [
-         {
-          "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
-          "InstLine" : 11,
-          "InstName" : "f0",
-          "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
-          "ModuleLine" : 1,
-          "ModuleName" : "fulladder",
-          "SubInsts" : [
-           {
-            "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
-            "InstLine" : 8,
-            "InstName" : "h1",
-            "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
-            "ModuleLine" : 1,
-            "ModuleName" : "halfadder"
-           },
-           {
-            "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
-            "InstLine" : 9,
-            "InstName" : "h2",
-            "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
-            "ModuleLine" : 1,
-            "ModuleName" : "halfadder"
-           }
-          ]
-         },
-         {
-          "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
-          "InstLine" : 12,
-          "InstName" : "f1",
-          "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
-          "ModuleLine" : 1,
-          "ModuleName" : "fulladder",
-          "SubInsts" : [
-           {
-            "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
-            "InstLine" : 8,
-            "InstName" : "h1",
-            "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
-            "ModuleLine" : 1,
-            "ModuleName" : "halfadder"
-           },
-           {
-            "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
-            "InstLine" : 9,
-            "InstName" : "h2",
-            "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
-            "ModuleLine" : 1,
-            "ModuleName" : "halfadder"
-           }
-          ]
-         },
-         {
-          "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
-          "InstLine" : 13,
-          "InstName" : "f2",
-          "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
-          "ModuleLine" : 1,
-          "ModuleName" : "fulladder",
-          "SubInsts" : [
-           {
-            "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
-            "InstLine" : 8,
-            "InstName" : "h1",
-            "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
-            "ModuleLine" : 1,
-            "ModuleName" : "halfadder"
-           },
-           {
-            "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
-            "InstLine" : 9,
-            "InstName" : "h2",
-            "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
-            "ModuleLine" : 1,
-            "ModuleName" : "halfadder"
-           }
-          ]
-         },
-         {
-          "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
-          "InstLine" : 14,
-          "InstName" : "f3",
-          "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
-          "ModuleLine" : 1,
-          "ModuleName" : "fulladder",
-          "SubInsts" : [
-           {
-            "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
-            "InstLine" : 8,
-            "InstName" : "h1",
-            "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
-            "ModuleLine" : 1,
-            "ModuleName" : "halfadder"
-           },
-           {
-            "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
-            "InstLine" : 9,
-            "InstName" : "h2",
-            "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
-            "ModuleLine" : 1,
-            "ModuleName" : "halfadder"
-           }
-          ]
-         }
-        ]
-       },
-       {
-        "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
-        "InstLine" : 14,
-        "InstName" : "s1",
-        "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
-        "ModuleLine" : 1,
-        "ModuleName" : "subtraction",
-        "SubInsts" : [
-         {
-          "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
-          "InstLine" : 11,
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-      "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
-      "InstLine" : 76,
-      "InstName" : "btod1",
-      "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
-      "ModuleLine" : 1,
-      "ModuleName" : "BinaryToBCD",
-      "SubInsts" : [
-       {
-        "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
-        "InstLine" : 14,
-        "InstName" : "d1t",
-        "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
-        "ModuleLine" : 1,
-        "ModuleName" : "dabble"
-       },
-       {
-        "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
-        "InstLine" : 23,
-        "InstName" : "d2u",
-        "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
-        "ModuleLine" : 1,
-        "ModuleName" : "dabble"
-       },
-       {
-        "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
-        "InstLine" : 32,
-        "InstName" : "d3v",
-        "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
-        "ModuleLine" : 1,
-        "ModuleName" : "dabble"
-       },
-       {
-        "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
-        "InstLine" : 41,
-        "InstName" : "d4w",
-        "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
-        "ModuleLine" : 1,
-        "ModuleName" : "dabble"
-       },
-       {
-        "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
-        "InstLine" : 50,
-        "InstName" : "d5x",
-        "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
-        "ModuleLine" : 1,
-        "ModuleName" : "dabble"
-       },
-       {
-        "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
-        "InstLine" : 59,
-        "InstName" : "d6y",
-        "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
-        "ModuleLine" : 1,
-        "ModuleName" : "dabble"
-       },
-       {
-        "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
-        "InstLine" : 68,
-        "InstName" : "d7z",
-        "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
-        "ModuleLine" : 1,
-        "ModuleName" : "dabble"
-       }
-      ]
-     }
-    ]
-   },
-   {
-    "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
-    "InstLine" : 14,
-    "InstName" : "s1",
-    "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/selector.v",
-    "ModuleLine" : 1,
-    "ModuleName" : "selector"
-   }
-  ]
- }
-]

gowin/bttn/impl/temp/rtl_parser.resultZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/temp/rtl_parser_arg.json

@@ -1,73 +0,0 @@
-{
- "Device" : "GW2A-18C",
- "Files" : [
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
-   "Type" : "verilog"
-  },
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
-   "Type" : "verilog"
-  },
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
-   "Type" : "verilog"
-  },
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
-   "Type" : "verilog"
-  },
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
-   "Type" : "verilog"
-  },
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
-   "Type" : "verilog"
-  },
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
-   "Type" : "verilog"
-  },
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
-   "Type" : "verilog"
-  },
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
-   "Type" : "verilog"
-  },
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
-   "Type" : "verilog"
-  },
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/logicUnit.v",
-   "Type" : "verilog"
-  },
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v",
-   "Type" : "verilog"
-  },
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/opCode.v",
-   "Type" : "verilog"
-  },
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/selector.v",
-   "Type" : "verilog"
-  },
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
-   "Type" : "verilog"
-  }
- ],
- "IncludePath" : [
-
- ],
- "LoopLimit" : 2000,
- "ResultFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/impl/temp/rtl_parser.result",
- "Top" : "",
- "VerilogStd" : "verilog_2001",
- "VhdlStd" : "vhdl_93"
-}

gowin/bttn/impl/temp/rtl_parser_arg.jsonZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/impl/temp/style.cssZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/ALU.vZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/BinaryToBCD.vZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/addition.vZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/arithmeticUnit.vZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/bttn.cstZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/bttn.vcdZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/bttn.vZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/bttnTB.vZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/bttnZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/dabble.vZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/fulladder.vZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/fullsubtraction.vZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/halfadder.vZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/halfsubtraction.vZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/logicUnit.vZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/multiplier.vZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/opCode.vZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/selector.vZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/subtraction.vZone.Identifier

@@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3

gowin/bttn/src/top.v

@@ -1,4 +1,4 @@
-module bttn (
+module top (
     input [3:0] A, B,
     input [2:0] opCodeA,
     input [1:0] select,
@@ -10,10 +10,10 @@ module bttn (
 
 wire wire1, wire2;
 wire [11:0] selectY;
-ALU a1(.A(A), .B(B), .opCodeA(opCodeA), .CarryIN(Cin), .bcd(selectY), .CarryOUT(wire2), .overflow(wire1));
-selector s1(.A(A), .B(B), .opCodeA(opCodeA), .select(select), .ALUY(selectY), .Y(Y));
+ALU a1(.A(A), .B(B), .opCodeA(opCodeA), .CarryIN(Cin), .bcd(selectY), .CarryOUT(wire2), .overflow(wire1)); //ALU module
+selector s1(.A(A), .B(B), .opCodeA(opCodeA), .select(select), .ALUY(selectY), .Y(Y));   // selector for 7 segment
 
-assign leds[0] = ~wire1;
-assign leds[1] = ~wire2;
+assign leds[0] = ~wire1; //overflow led
+assign leds[1] = ~wire2; //CarryOut/BorrowOut led
 
 endmodule

gowin/bttn/src/topTB.v

@@ -1,11 +1,11 @@
-module bttnTB();
+module topTB();
 
 reg [3:0] A,B;
 reg [2:0] opCodeA;
 reg [1:0] select;
 wire [11:0] Y;
 
-bttn uut (
+top uut (
     .A(A),
     .B(B),
     .opCodeA(opCodeA),
@@ -14,7 +14,7 @@ bttn uut (
 );
 
 initial begin
-    $dumpfile("bttn.vcd");
+    $dumpfile("top.vcd");
     $dumpvars;
     A = 4'b0001; B = 4'b0110; opCodeA = 3'b000; select = 2'b01; #5;
     $finish;

iverilog/tobb/lab4/bib3

@@ -0,0 +1,291 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x55ec90657360 .scope module, "bib3TB" "bib3TB" 2 1;
+ .timescale 0 0;
+v0x55ec9066dea0_0 .var "A", 8 0;
+v0x55ec9066df60_0 .net "Y", 3 0, v0x55ec9066dd60_0;  1 drivers
+S_0x55ec906574f0 .scope module, "uut" "bib3" 2 6, 3 1 0, S_0x55ec90657360;
+ .timescale 0 0;
+    .port_info 0 /INPUT 9 "buyruk";
+    .port_info 1 /OUTPUT 4 "sonuc";
+v0x55ec90618c00_0 .var/i "a", 31 0;
+v0x55ec9066d8d0_0 .var/i "b", 31 0;
+v0x55ec9066d9b0_0 .net "buyruk", 8 0, v0x55ec9066dea0_0;  1 drivers
+v0x55ec9066da70_0 .var/i "c", 31 0;
+v0x55ec9066db50_0 .var/i "count", 31 0;
+v0x55ec9066dc80_0 .var/i "i", 31 0;
+v0x55ec9066dd60_0 .var "sonuc", 3 0;
+E_0x55ec9064fc40 .event edge, v0x55ec9066d9b0_0;
+    .scope S_0x55ec906574f0;
+T_0 ;
+    %wait E_0x55ec9064fc40;
+    %load/vec4 v0x55ec9066d9b0_0;
+    %parti/s 3, 6, 4;
+    %dup/vec4;
+    %pushi/vec4 0, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.1, 6;
+    %dup/vec4;
+    %pushi/vec4 1, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.2, 6;
+    %dup/vec4;
+    %pushi/vec4 2, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.3, 6;
+    %dup/vec4;
+    %pushi/vec4 3, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.4, 6;
+    %dup/vec4;
+    %pushi/vec4 4, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.5, 6;
+    %dup/vec4;
+    %pushi/vec4 5, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.6, 6;
+    %dup/vec4;
+    %pushi/vec4 6, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.7, 6;
+    %dup/vec4;
+    %pushi/vec4 7, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.8, 6;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x55ec9066dd60_0, 0, 4;
+    %jmp T_0.9;
+T_0.1 ;
+    %load/vec4 v0x55ec9066d9b0_0;
+    %parti/s 3, 3, 3;
+    %pad/u 4;
+    %load/vec4 v0x55ec9066d9b0_0;
+    %parti/s 3, 0, 2;
+    %pad/u 4;
+    %add;
+    %store/vec4 v0x55ec9066dd60_0, 0, 4;
+    %jmp T_0.9;
+T_0.2 ;
+    %load/vec4 v0x55ec9066d9b0_0;
+    %parti/s 3, 3, 3;
+    %pad/u 4;
+    %load/vec4 v0x55ec9066d9b0_0;
+    %parti/s 3, 0, 2;
+    %pad/u 4;
+    %sub;
+    %store/vec4 v0x55ec9066dd60_0, 0, 4;
+    %jmp T_0.9;
+T_0.3 ;
+    %load/vec4 v0x55ec9066d9b0_0;
+    %parti/s 3, 3, 3;
+    %pad/u 4;
+    %load/vec4 v0x55ec9066d9b0_0;
+    %parti/s 3, 0, 2;
+    %pad/u 4;
+    %and;
+    %store/vec4 v0x55ec9066dd60_0, 0, 4;
+    %jmp T_0.9;
+T_0.4 ;
+    %load/vec4 v0x55ec9066d9b0_0;
+    %parti/s 3, 3, 3;
+    %pad/u 4;
+    %load/vec4 v0x55ec9066d9b0_0;
+    %parti/s 3, 0, 2;
+    %pad/u 4;
+    %or;
+    %store/vec4 v0x55ec9066dd60_0, 0, 4;
+    %jmp T_0.9;
+T_0.5 ;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x55ec9066dc80_0, 0, 32;
+T_0.10 ;
+    %load/vec4 v0x55ec9066dc80_0;
+    %cmpi/s 4, 0, 32;
+    %flag_or 5, 4;
+    %jmp/0xz T_0.11, 5;
+    %load/vec4 v0x55ec9066d9b0_0;
+    %load/vec4 v0x55ec9066dc80_0;
+    %part/s 1;
+    %load/vec4 v0x55ec9066d9b0_0;
+    %load/vec4 v0x55ec9066dc80_0;
+    %addi 1, 0, 32;
+    %part/s 1;
+    %cmp/e;
+    %jmp/0xz  T_0.12, 4;
+    %pushi/vec4 15, 0, 4;
+    %store/vec4 v0x55ec9066dd60_0, 0, 4;
+    %jmp T_0.13;
+T_0.12 ;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x55ec9066dd60_0, 0, 4;
+T_0.13 ;
+    ; show_stmt_assign_vector: Get l-value for compressed += operand
+    %load/vec4 v0x55ec9066dc80_0;
+    %pushi/vec4 1, 0, 32;
+    %add;
+    %store/vec4 v0x55ec9066dc80_0, 0, 32;
+    %jmp T_0.10;
+T_0.11 ;
+    %jmp T_0.9;
+T_0.6 ;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x55ec90618c00_0, 0, 32;
+T_0.14 ;
+    %load/vec4 v0x55ec90618c00_0;
+    %cmpi/s 5, 0, 32;
+    %flag_or 5, 4;
+    %jmp/0xz T_0.15, 5;
+    %load/vec4 v0x55ec9066d9b0_0;
+    %load/vec4 v0x55ec90618c00_0;
+    %part/s 1;
+    %pad/u 32;
+    %cmpi/e 1, 0, 32;
+    %jmp/0xz  T_0.16, 4;
+    %pushi/vec4 15, 0, 4;
+    %store/vec4 v0x55ec9066dd60_0, 0, 4;
+    %jmp T_0.17;
+T_0.16 ;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x55ec9066dd60_0, 0, 4;
+T_0.17 ;
+    ; show_stmt_assign_vector: Get l-value for compressed += operand
+    %load/vec4 v0x55ec90618c00_0;
+    %pushi/vec4 1, 0, 32;
+    %add;
+    %store/vec4 v0x55ec90618c00_0, 0, 32;
+    %jmp T_0.14;
+T_0.15 ;
+    %jmp T_0.9;
+T_0.7 ;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x55ec9066db50_0, 0, 32;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x55ec9066d8d0_0, 0, 32;
+T_0.18 ;
+    %load/vec4 v0x55ec9066d8d0_0;
+    %cmpi/s 5, 0, 32;
+    %flag_or 5, 4;
+    %jmp/0xz T_0.19, 5;
+    %load/vec4 v0x55ec9066d9b0_0;
+    %load/vec4 v0x55ec9066d8d0_0;
+    %part/s 1;
+    %pad/u 32;
+    %cmpi/e 1, 0, 32;
+    %jmp/0xz  T_0.20, 4;
+    %load/vec4 v0x55ec9066db50_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0x55ec9066db50_0, 0, 32;
+T_0.20 ;
+    ; show_stmt_assign_vector: Get l-value for compressed += operand
+    %load/vec4 v0x55ec9066d8d0_0;
+    %pushi/vec4 1, 0, 32;
+    %add;
+    %store/vec4 v0x55ec9066d8d0_0, 0, 32;
+    %jmp T_0.18;
+T_0.19 ;
+    %load/vec4 v0x55ec9066db50_0;
+    %pushi/vec4 2, 0, 32;
+    %mod/s;
+    %cmpi/e 0, 0, 32;
+    %jmp/0xz  T_0.22, 4;
+    %pushi/vec4 15, 0, 4;
+    %store/vec4 v0x55ec9066dd60_0, 0, 4;
+    %jmp T_0.23;
+T_0.22 ;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x55ec9066dd60_0, 0, 4;
+T_0.23 ;
+    %jmp T_0.9;
+T_0.8 ;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x55ec9066db50_0, 0, 32;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x55ec9066da70_0, 0, 32;
+T_0.24 ;
+    %load/vec4 v0x55ec9066da70_0;
+    %cmpi/s 5, 0, 32;
+    %flag_or 5, 4;
+    %jmp/0xz T_0.25, 5;
+    %load/vec4 v0x55ec9066d9b0_0;
+    %load/vec4 v0x55ec9066da70_0;
+    %part/s 1;
+    %pad/u 32;
+    %cmpi/e 1, 0, 32;
+    %jmp/0xz  T_0.26, 4;
+    ; show_stmt_assign_vector: Get l-value for compressed += operand
+    %load/vec4 v0x55ec9066db50_0;
+    %pushi/vec4 1, 0, 32;
+    %add;
+    %store/vec4 v0x55ec9066db50_0, 0, 32;
+T_0.26 ;
+    ; show_stmt_assign_vector: Get l-value for compressed += operand
+    %load/vec4 v0x55ec9066da70_0;
+    %pushi/vec4 1, 0, 32;
+    %add;
+    %store/vec4 v0x55ec9066da70_0, 0, 32;
+    %jmp T_0.24;
+T_0.25 ;
+    %load/vec4 v0x55ec9066db50_0;
+    %pushi/vec4 2, 0, 32;
+    %mod/s;
+    %cmpi/e 0, 0, 32;
+    %jmp/0xz  T_0.28, 4;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x55ec9066dd60_0, 0, 4;
+    %jmp T_0.29;
+T_0.28 ;
+    %pushi/vec4 15, 0, 4;
+    %store/vec4 v0x55ec9066dd60_0, 0, 4;
+T_0.29 ;
+    %jmp T_0.9;
+T_0.9 ;
+    %pop/vec4 1;
+    %jmp T_0;
+    .thread T_0, $push;
+    .scope S_0x55ec90657360;
+T_1 ;
+    %vpi_call 2 12 "$dumpfile", "bib3.vcd" {0 0 0};
+    %vpi_call 2 13 "$dumpvars" {0 0 0};
+    %pushi/vec4 9, 0, 9;
+    %store/vec4 v0x55ec9066dea0_0, 0, 9;
+    %delay 5, 0;
+    %pushi/vec4 97, 0, 9;
+    %store/vec4 v0x55ec9066dea0_0, 0, 9;
+    %delay 5, 0;
+    %pushi/vec4 165, 0, 9;
+    %store/vec4 v0x55ec9066dea0_0, 0, 9;
+    %delay 5, 0;
+    %pushi/vec4 227, 0, 9;
+    %store/vec4 v0x55ec9066dea0_0, 0, 9;
+    %delay 5, 0;
+    %pushi/vec4 319, 0, 9;
+    %store/vec4 v0x55ec9066dea0_0, 0, 9;
+    %delay 5, 0;
+    %pushi/vec4 289, 0, 9;
+    %store/vec4 v0x55ec9066dea0_0, 0, 9;
+    %delay 5, 0;
+    %pushi/vec4 353, 0, 9;
+    %store/vec4 v0x55ec9066dea0_0, 0, 9;
+    %delay 5, 0;
+    %pushi/vec4 417, 0, 9;
+    %store/vec4 v0x55ec9066dea0_0, 0, 9;
+    %delay 5, 0;
+    %pushi/vec4 481, 0, 9;
+    %store/vec4 v0x55ec9066dea0_0, 0, 9;
+    %delay 5, 0;
+    %end;
+    .thread T_1;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "bib3TB.v";
+    "bib3.v";

iverilog/tobb/lab4/bib3.v

@@ -0,0 +1,49 @@
+module  bib3 (
+    input [8:0] buyruk,
+    output reg [3:0] sonuc
+);
+    integer i, a, b, c, count;
+    always@(buyruk) begin
+        case (buyruk[8:6])
+        default: sonuc = 4'b0000;
+        3'b000: sonuc = buyruk[5:3] + buyruk[2:0];
+        3'b001: sonuc = buyruk[5:3] - buyruk[2:0];
+        3'b010: sonuc = buyruk[5:3] & buyruk[2:0];
+        3'b011: sonuc = buyruk[5:3] | buyruk[2:0];
+        3'b100: begin
+            for (i = 0; i <= 4; i++)
+                if (buyruk[i] == buyruk[i+1])
+                    sonuc = 4'b1111;
+                else
+                    sonuc = 4'b0000;
+        end
+        3'b101: for (a = 0; a <= 5; a++) begin
+                            if (buyruk[a] == 1)
+                                sonuc = 4'b1111;
+                            else
+                            sonuc = 4'b0000;
+        end
+        3'b110: begin
+             count = 0;
+            for (b = 0; b <= 5; b++) begin
+                if (buyruk[b] == 1)
+                    count = count + 1;
+            end
+            if (count % 2 == 0)
+                sonuc = 4'b1111;
+            else
+                sonuc = 4'b0000;
+        end
+        3'b111: begin
+             count = 0;
+            for (c = 0; c <= 5; c++)
+                if (buyruk[c] == 1)
+                count++;
+                if (count % 2 == 0)
+                    sonuc = 4'b0000;
+                else
+                    sonuc = 4'b1111;
+        end
+        endcase
+    end
+endmodule

iverilog/tobb/lab4/bib3.vcd

@@ -0,0 +1,81 @@
+$date
+	Sat Jan 25 01:26:43 2025
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module bib3TB $end
+$var wire 4 ! Y [3:0] $end
+$var reg 9 " A [8:0] $end
+$scope module uut $end
+$var wire 9 # buyruk [8:0] $end
+$var reg 4 $ sonuc [3:0] $end
+$var integer 32 % a [31:0] $end
+$var integer 32 & b [31:0] $end
+$var integer 32 ' c [31:0] $end
+$var integer 32 ( count [31:0] $end
+$var integer 32 ) i [31:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+bx )
+bx (
+bx '
+bx &
+bx %
+b10 $
+b1001 #
+b1001 "
+b10 !
+$end
+#5
+b11 !
+b11 $
+b1100001 "
+b1100001 #
+#10
+b100 !
+b100 $
+b10100101 "
+b10100101 #
+#15
+b111 !
+b111 $
+b11100011 "
+b11100011 #
+#20
+b1111 !
+b1111 $
+b101 )
+b100111111 "
+b100111111 #
+#25
+b0 !
+b0 $
+b101 )
+b100100001 "
+b100100001 #
+#30
+b1111 !
+b1111 $
+b110 %
+b101100001 "
+b101100001 #
+#35
+b110 &
+b10 (
+b110100001 "
+b110100001 #
+#40
+b0 !
+b0 $
+b110 '
+b10 (
+b111100001 "
+b111100001 #
+#45

iverilog/tobb/lab4/bib3TB.v

@@ -0,0 +1,25 @@
+module bib3TB();
+
+reg [8:0] A;
+wire [3:0] Y;
+
+bib3 uut (
+    .buyruk(A),
+    .sonuc(Y)
+);
+
+initial begin
+    $dumpfile("bib3.vcd");
+    $dumpvars;
+    A = 9'b000_001_001; #5;
+    A = 9'b001_100_001; #5;
+    A = 9'b010_100_101; #5;
+    A = 9'b011_100_011; #5;
+    A = 9'b100_111_111; #5;
+    A = 9'b100_100_001; #5;
+    A = 9'b101_100_001; #5;
+    A = 9'b110_100_001; #5;
+    A = 9'b111_100_001; #5;
+end
+
+endmodule

iverilog/tobb/lab4/sube3soru2

@@ -0,0 +1,117 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x55a0b73b0f40 .scope module, "sube3soru2TB" "sube3soru2TB" 2 1;
+ .timescale 0 0;
+v0x55a0b73c4170_0 .var "A", 9 0;
+v0x55a0b73c4250_0 .var "B", 5 0;
+v0x55a0b73c4320_0 .net "D", 4 0, v0x55a0b73c3b30_0;  1 drivers
+v0x55a0b73c4420_0 .net "l1", 4 0, v0x55a0b73c3d00_0;  1 drivers
+v0x55a0b73c44f0_0 .net "l2", 4 0, v0x55a0b73c3e30_0;  1 drivers
+S_0x55a0b73b10d0 .scope module, "uut" "sube3soru2" 2 7, 3 1 0, S_0x55a0b73b0f40;
+ .timescale 0 0;
+    .port_info 0 /INPUT 10 "A";
+    .port_info 1 /INPUT 6 "B";
+    .port_info 2 /OUTPUT 5 "D";
+    .port_info 3 /OUTPUT 5 "l1";
+    .port_info 4 /OUTPUT 5 "l2";
+v0x55a0b7376c00_0 .net "A", 9 0, v0x55a0b73c4170_0;  1 drivers
+v0x55a0b73c3a50_0 .net "B", 5 0, v0x55a0b73c4250_0;  1 drivers
+v0x55a0b73c3b30_0 .var "D", 4 0;
+v0x55a0b73c3c20_0 .var/i "hunderedR", 31 0;
+v0x55a0b73c3d00_0 .var "l1", 4 0;
+v0x55a0b73c3e30_0 .var "l2", 4 0;
+v0x55a0b73c3f10_0 .var/i "tempD", 31 0;
+v0x55a0b73c3ff0_0 .var/i "tempO", 31 0;
+E_0x55a0b73ae360 .event edge, v0x55a0b73c3a50_0, v0x55a0b7376c00_0;
+    .scope S_0x55a0b73b10d0;
+T_0 ;
+    %wait E_0x55a0b73ae360;
+    %load/vec4 v0x55a0b7376c00_0;
+    %parti/s 8, 2, 3;
+    %pad/u 32;
+    %muli 100, 0, 32;
+    %store/vec4 v0x55a0b73c3c20_0, 0, 32;
+    %load/vec4 v0x55a0b7376c00_0;
+    %parti/s 2, 0, 2;
+    %dup/vec4;
+    %pushi/vec4 1, 0, 2;
+    %cmp/u;
+    %jmp/1 T_0.0, 6;
+    %dup/vec4;
+    %pushi/vec4 2, 0, 2;
+    %cmp/u;
+    %jmp/1 T_0.1, 6;
+    %dup/vec4;
+    %pushi/vec4 3, 0, 2;
+    %cmp/u;
+    %jmp/1 T_0.2, 6;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x55a0b73c3f10_0, 0, 32;
+    %jmp T_0.4;
+T_0.0 ;
+    %pushi/vec4 25, 0, 32;
+    %store/vec4 v0x55a0b73c3f10_0, 0, 32;
+    %jmp T_0.4;
+T_0.1 ;
+    %pushi/vec4 50, 0, 32;
+    %store/vec4 v0x55a0b73c3f10_0, 0, 32;
+    %jmp T_0.4;
+T_0.2 ;
+    %pushi/vec4 75, 0, 32;
+    %store/vec4 v0x55a0b73c3f10_0, 0, 32;
+    %jmp T_0.4;
+T_0.4 ;
+    %pop/vec4 1;
+    %load/vec4 v0x55a0b73c3c20_0;
+    %load/vec4 v0x55a0b73c3f10_0;
+    %add;
+    %store/vec4 v0x55a0b73c3ff0_0, 0, 32;
+    %load/vec4 v0x55a0b73c3ff0_0;
+    %load/vec4 v0x55a0b73c3a50_0;
+    %pad/u 32;
+    %div;
+    %store/vec4 v0x55a0b73c3ff0_0, 0, 32;
+    %load/vec4 v0x55a0b73c3ff0_0;
+    %pushi/vec4 100, 0, 32;
+    %div/s;
+    %pad/s 5;
+    %store/vec4 v0x55a0b73c3b30_0, 0, 5;
+    %load/vec4 v0x55a0b73c3ff0_0;
+    %pushi/vec4 100, 0, 32;
+    %mod/s;
+    %pushi/vec4 10, 0, 32;
+    %div/s;
+    %pad/s 5;
+    %store/vec4 v0x55a0b73c3d00_0, 0, 5;
+    %load/vec4 v0x55a0b73c3ff0_0;
+    %pushi/vec4 10, 0, 32;
+    %mod/s;
+    %pad/s 5;
+    %store/vec4 v0x55a0b73c3e30_0, 0, 5;
+    %jmp T_0;
+    .thread T_0, $push;
+    .scope S_0x55a0b73b0f40;
+T_1 ;
+    %vpi_call 2 16 "$dumpfile", "sube3soru2.vcd" {0 0 0};
+    %vpi_call 2 17 "$dumpvars" {0 0 0};
+    %pushi/vec4 25, 0, 10;
+    %store/vec4 v0x55a0b73c4170_0, 0, 10;
+    %pushi/vec4 3, 0, 6;
+    %store/vec4 v0x55a0b73c4250_0, 0, 6;
+    %delay 5, 0;
+    %vpi_call 2 19 "$finish" {0 0 0};
+    %end;
+    .thread T_1;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "sube3soru2TB.v";
+    "sube3soru2.v";

iverilog/tobb/lab4/sube3soru2.v

@@ -0,0 +1,24 @@
+module sube3soru2 (
+    input [9:0] A,
+    input [5:0] B,
+    output reg [4:0] D,l1,l2
+);
+
+integer tempD, tempO, hunderedR;
+
+always@(A or B) begin
+    hunderedR = A[9:2] * 100;
+    case(A[1:0])
+    2'b01: tempD = 25;
+    2'b10: tempD = 50;
+    2'b11: tempD = 75;
+    default: tempD = 00;
+    endcase
+    tempO = hunderedR + tempD;
+    tempO = tempO / B;
+    D = tempO / 100;
+    l1 = (tempO%100)/10;
+    l2 = tempO%10;
+end
+
+endmodule

iverilog/tobb/lab4/sube3soru2.vcd

@@ -0,0 +1,44 @@
+$date
+	Sat Jan 25 03:14:14 2025
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module sube3soru2TB $end
+$var wire 5 ! l2 [4:0] $end
+$var wire 5 " l1 [4:0] $end
+$var wire 5 # D [4:0] $end
+$var reg 10 $ A [9:0] $end
+$var reg 6 % B [5:0] $end
+$scope module uut $end
+$var wire 10 & A [9:0] $end
+$var wire 6 ' B [5:0] $end
+$var reg 5 ( D [4:0] $end
+$var reg 5 ) l1 [4:0] $end
+$var reg 5 * l2 [4:0] $end
+$var integer 32 + hunderedR [31:0] $end
+$var integer 32 , tempD [31:0] $end
+$var integer 32 - tempO [31:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b11010000 -
+b11001 ,
+b1001011000 +
+b1000 *
+b0 )
+b10 (
+b11 '
+b11001 &
+b11 %
+b11001 $
+b10 #
+b0 "
+b1000 !
+$end
+#5

iverilog/tobb/lab4/sube3soru2TB.v

@@ -0,0 +1,22 @@
+module sube3soru2TB();
+
+reg [9:0] A;
+reg [5:0] B;
+wire [4:0] D,l1,l2;
+
+sube3soru2 uut (
+    .A(A),
+    .B(B),
+    .D(D),
+    .l1(l1),
+    .l2(l2)
+);
+
+initial begin
+    $dumpfile("sube3soru2.vcd");
+    $dumpvars;
+    A = 10'b0000011001; B = 6'b000011; #5;
+    $finish;
+end
+
+endmodule

iverilog/tobb/lab5/ayarliSayac

@@ -0,0 +1,193 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x55b4b9d0fd50 .scope module, "ayarliSayacTB" "ayarliSayacTB" 2 1;
+ .timescale 0 0;
+v0x55b4b9d66830_0 .var "clk", 0 0;
+v0x55b4b9d668f0_0 .var "en", 0 0;
+v0x55b4b9d669c0_0 .var "rst", 0 0;
+v0x55b4b9d66ac0_0 .net "sayac", 5 0, v0x55b4b9d664f0_0;  1 drivers
+v0x55b4b9d66b90_0 .var "sayma_miktari", 2 0;
+v0x55b4b9d66c80_0 .var "sayma_yonu", 0 0;
+S_0x55b4b9d0fee0 .scope module, "uut" "sayac" 2 8, 3 1 0, S_0x55b4b9d0fd50;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "en";
+    .port_info 3 /INPUT 3 "sayma_miktari";
+    .port_info 4 /INPUT 1 "sayma_yonu";
+    .port_info 5 /OUTPUT 6 "sayac";
+v0x55b4b9d4e5b0_0 .net "clk", 0 0, v0x55b4b9d66830_0;  1 drivers
+v0x55b4b9d66180_0 .var "clk_divider", 1 0;
+v0x55b4b9d66260_0 .net "en", 0 0, v0x55b4b9d668f0_0;  1 drivers
+v0x55b4b9d66300_0 .var "miktar", 2 0;
+v0x55b4b9d663e0_0 .net "rst", 0 0, v0x55b4b9d669c0_0;  1 drivers
+v0x55b4b9d664f0_0 .var "sayac", 5 0;
+v0x55b4b9d665d0_0 .net "sayma_miktari", 2 0, v0x55b4b9d66b90_0;  1 drivers
+v0x55b4b9d666b0_0 .net "sayma_yonu", 0 0, v0x55b4b9d66c80_0;  1 drivers
+E_0x55b4b9d4f1d0/0 .event negedge, v0x55b4b9d4e5b0_0;
+E_0x55b4b9d4f1d0/1 .event posedge, v0x55b4b9d663e0_0;
+E_0x55b4b9d4f1d0 .event/or E_0x55b4b9d4f1d0/0, E_0x55b4b9d4f1d0/1;
+    .scope S_0x55b4b9d0fee0;
+T_0 ;
+    %pushi/vec4 0, 0, 6;
+    %store/vec4 v0x55b4b9d664f0_0, 0, 6;
+    %pushi/vec4 0, 0, 2;
+    %store/vec4 v0x55b4b9d66180_0, 0, 2;
+    %pushi/vec4 0, 0, 3;
+    %store/vec4 v0x55b4b9d66300_0, 0, 3;
+    %end;
+    .thread T_0;
+    .scope S_0x55b4b9d0fee0;
+T_1 ;
+    %wait E_0x55b4b9d4f1d0;
+    %load/vec4 v0x55b4b9d663e0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.0, 8;
+    %pushi/vec4 0, 0, 6;
+    %assign/vec4 v0x55b4b9d664f0_0, 0;
+    %pushi/vec4 0, 0, 2;
+    %assign/vec4 v0x55b4b9d66180_0, 0;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0x55b4b9d66300_0, 0;
+    %jmp T_1.1;
+T_1.0 ;
+    %load/vec4 v0x55b4b9d66180_0;
+    %addi 1, 0, 2;
+    %assign/vec4 v0x55b4b9d66180_0, 0;
+    %load/vec4 v0x55b4b9d66180_0;
+    %cmpi/e 3, 0, 2;
+    %jmp/0xz  T_1.2, 4;
+    %pushi/vec4 0, 0, 2;
+    %assign/vec4 v0x55b4b9d66180_0, 0;
+    %load/vec4 v0x55b4b9d66260_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.4, 8;
+    %load/vec4 v0x55b4b9d665d0_0;
+    %assign/vec4 v0x55b4b9d66300_0, 0;
+T_1.4 ;
+    %load/vec4 v0x55b4b9d666b0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.6, 8;
+    %load/vec4 v0x55b4b9d664f0_0;
+    %load/vec4 v0x55b4b9d66300_0;
+    %pad/u 6;
+    %add;
+    %cmpi/u 63, 0, 6;
+    %flag_inv 5; GE is !LT
+    %jmp/0xz  T_1.8, 5;
+    %pushi/vec4 63, 0, 6;
+    %assign/vec4 v0x55b4b9d664f0_0, 0;
+    %jmp T_1.9;
+T_1.8 ;
+    %load/vec4 v0x55b4b9d664f0_0;
+    %load/vec4 v0x55b4b9d66300_0;
+    %pad/u 6;
+    %add;
+    %assign/vec4 v0x55b4b9d664f0_0, 0;
+T_1.9 ;
+    %jmp T_1.7;
+T_1.6 ;
+    %load/vec4 v0x55b4b9d664f0_0;
+    %load/vec4 v0x55b4b9d66300_0;
+    %pad/u 6;
+    %cmp/u;
+    %flag_or 5, 4;
+    %jmp/0xz  T_1.10, 5;
+    %pushi/vec4 0, 0, 6;
+    %assign/vec4 v0x55b4b9d664f0_0, 0;
+    %jmp T_1.11;
+T_1.10 ;
+    %load/vec4 v0x55b4b9d664f0_0;
+    %load/vec4 v0x55b4b9d66300_0;
+    %pad/u 6;
+    %sub;
+    %assign/vec4 v0x55b4b9d664f0_0, 0;
+T_1.11 ;
+T_1.7 ;
+T_1.2 ;
+T_1.1 ;
+    %jmp T_1;
+    .thread T_1;
+    .scope S_0x55b4b9d0fd50;
+T_2 ;
+    %load/vec4 v0x55b4b9d66830_0;
+    %inv;
+    %store/vec4 v0x55b4b9d66830_0, 0, 1;
+    %delay 1, 0;
+    %jmp T_2;
+    .thread T_2;
+    .scope S_0x55b4b9d0fd50;
+T_3 ;
+    %vpi_call 2 22 "$dumpfile", "ayarliSayac.vcd" {0 0 0};
+    %vpi_call 2 23 "$dumpvars" {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55b4b9d66830_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55b4b9d669c0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55b4b9d668f0_0, 0, 1;
+    %pushi/vec4 7, 0, 3;
+    %store/vec4 v0x55b4b9d66b90_0, 0, 3;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55b4b9d66c80_0, 0, 1;
+    %delay 32, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55b4b9d66830_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55b4b9d669c0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55b4b9d668f0_0, 0, 1;
+    %pushi/vec4 7, 0, 3;
+    %store/vec4 v0x55b4b9d66b90_0, 0, 3;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55b4b9d66c80_0, 0, 1;
+    %delay 8, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55b4b9d66830_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55b4b9d669c0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55b4b9d668f0_0, 0, 1;
+    %pushi/vec4 7, 0, 3;
+    %store/vec4 v0x55b4b9d66b90_0, 0, 3;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55b4b9d66c80_0, 0, 1;
+    %delay 64, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55b4b9d66830_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55b4b9d669c0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55b4b9d668f0_0, 0, 1;
+    %pushi/vec4 7, 0, 3;
+    %store/vec4 v0x55b4b9d66b90_0, 0, 3;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55b4b9d66c80_0, 0, 1;
+    %delay 16, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55b4b9d66830_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55b4b9d669c0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55b4b9d668f0_0, 0, 1;
+    %pushi/vec4 2, 0, 3;
+    %store/vec4 v0x55b4b9d66b90_0, 0, 3;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55b4b9d66c80_0, 0, 1;
+    %delay 8, 0;
+    %vpi_call 2 29 "$finish" {0 0 0};
+    %end;
+    .thread T_3;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "ayarliSayacTB.v";
+    "sayac.v";

iverilog/tobb/lab5/ayarliSayac.v

@@ -0,0 +1,43 @@
+module ayarliSayac (
+    input clk, rst, en,
+    input [2:0] sayma_miktari,
+    input sayma_yonu,
+    output reg [5:0] sayac
+);
+
+    reg [2:0] miktar;
+    reg [1:0] clk_divider;
+
+    initial begin
+        sayac = 6'b0000_00;
+        miktar = 3'b001;
+        clk_divider = 2'b00;
+    end
+
+    always @(negedge clk or posedge rst) begin
+        if (rst) begin
+            sayac <= 6'b0000_00;
+            clk_divider <= 2'b00;
+        end else begin
+            clk_divider <= clk_divider + 1;
+        end
+        if (clk_divider == 2'b11) begin
+            if (en) begin
+            miktar = sayma_miktari;
+            if (sayma_yonu == 1) begin
+                if (sayac + miktar >= 6'b1111_11) begin
+                    sayac <= 6'b1111_11;
+                end else begin
+                    sayac <= miktar + sayac;
+                end
+            end else begin
+                if (sayac - miktar <= 6'b0000_00) begin
+                    sayac <= 6'b0000_00;
+                end else begin
+                    sayac <= sayac - miktar;
+                end
+            end
+        end
+    end
+end
+endmodule

iverilog/tobb/lab5/ayarliSayac.vcd

@@ -0,0 +1,393 @@
+$date
+	Sun Jan 26 04:55:11 2025
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module ayarliSayacTB $end
+$var wire 6 ! sayac [5:0] $end
+$var reg 1 " clk $end
+$var reg 1 # en $end
+$var reg 1 $ rst $end
+$var reg 3 % sayma_miktari [2:0] $end
+$var reg 1 & sayma_yonu $end
+$scope module uut $end
+$var wire 1 " clk $end
+$var wire 1 # en $end
+$var wire 1 $ rst $end
+$var wire 3 ' sayma_miktari [2:0] $end
+$var wire 1 & sayma_yonu $end
+$var reg 2 ( clk_divider [1:0] $end
+$var reg 3 ) miktar [2:0] $end
+$var reg 6 * sayac [5:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b0 *
+b0 )
+b0 (
+b111 '
+1&
+b111 %
+0$
+1#
+1"
+b0 !
+$end
+#1
+b1 (
+0"
+#2
+1"
+#3
+b10 (
+0"
+#4
+1"
+#5
+b11 (
+0"
+#6
+1"
+#7
+b111 )
+b0 (
+0"
+#8
+1"
+#9
+b1 (
+0"
+#10
+1"
+#11
+b10 (
+0"
+#12
+1"
+#13
+b11 (
+0"
+#14
+1"
+#15
+b111 !
+b111 *
+b0 (
+0"
+#16
+1"
+#17
+b1 (
+0"
+#18
+1"
+#19
+b10 (
+0"
+#20
+1"
+#21
+b11 (
+0"
+#22
+1"
+#23
+b1110 !
+b1110 *
+b0 (
+0"
+#24
+1"
+#25
+b1 (
+0"
+#26
+1"
+#27
+b10 (
+0"
+#28
+1"
+#29
+b11 (
+0"
+#30
+1"
+#31
+b10101 !
+b10101 *
+b0 (
+0"
+#32
+b1 (
+0"
+#33
+1"
+#34
+b10 (
+0"
+#35
+1"
+#36
+b11 (
+0"
+#37
+1"
+#38
+b11100 !
+b11100 *
+b0 (
+0"
+#39
+1"
+#40
+b1 (
+0"
+#41
+1"
+#42
+b10 (
+0"
+#43
+1"
+#44
+b11 (
+0"
+#45
+1"
+#46
+b100011 !
+b100011 *
+b0 (
+0"
+#47
+1"
+#48
+b1 (
+0"
+#49
+1"
+#50
+b10 (
+0"
+#51
+1"
+#52
+b11 (
+0"
+#53
+1"
+#54
+b101010 !
+b101010 *
+b0 (
+0"
+#55
+1"
+#56
+b1 (
+0"
+#57
+1"
+#58
+b10 (
+0"
+#59
+1"
+#60
+b11 (
+0"
+#61
+1"
+#62
+b110001 !
+b110001 *
+b0 (
+0"
+#63
+1"
+#64
+b1 (
+0"
+#65
+1"
+#66
+b10 (
+0"
+#67
+1"
+#68
+b11 (
+0"
+#69
+1"
+#70
+b111000 !
+b#70
+00 *
+b0 (
+0"
+#71
+1"
+#72
+b1 (
+0"
+#73
+1"
+#74
+b10 (
+0"
+#75
+1"
+#76
+b11 (
+0"
+#77
+1"
+#78
+b111111 !
+b111111 *
+b0 (
+0"
+#79
+1"
+#80
+b1 (
+0"
+#81
+1"
+#82
+b10 (
+0"
+#83
+1"
+#84
+b11 (
+0"
+#85
+1"
+#86
+b110 !
+b110 *
+b0 (
+0"
+#87
+1"
+#88
+b1 (
+0"
+#89
+1"
+#90
+b10 (
+0"
+#91
+1"
+#92
+b11 (
+0"
+#93
+1"
+#94
+b1101 !
+b1101 *
+b0 (
+0"
+#95
+1"
+#96
+b1 (
+0"
+#97
+1"
+#98
+b10 (
+0"
+#99
+1"
+#100
+b11 (
+0"
+#101
+1"
+#102
+b10100 !
+b10100 *
+b0 (
+0"
+#103
+1"
+#104
+b1 (
+0"
+#105
+1"
+#106
+b10 (
+0"
+#107
+1"
+#108
+b11 (
+0"
+#109
+1"
+#110
+b11011 !
+b11011 *
+b0 (
+0"
+#111
+1"
+#112
+b1 (
+0"
+#113
+1"
+#114
+b10 (
+0"
+#115
+1"
+#116
+b11 (
+0"
+#117
+1"
+#118
+b100010 !
+b100010 *
+b0 (
+0"
+#119
+1"
+#120
+b0 )
+b0 !
+b0 *
+0"
+b10 %
+b10 '
+1$
+#121
+1"
+#122
+0"
+#123
+1"
+#124
+0"
+#125
+1"
+#126
+0"
+#127
+1"
+#128
+0"

iverilog/tobb/lab5/ayarliSayacTB.v

@@ -0,0 +1,32 @@
+module ayarliSayacTB();
+
+    reg clk, rst, en;
+    reg [2:0] sayma_miktari;
+    reg sayma_yonu;
+    wire [5:0] sayac;
+
+sayac uut (
+    .clk(clk),
+    .rst(rst),
+    .en(en),
+    .sayma_miktari(sayma_miktari),
+    .sayma_yonu(sayma_yonu),
+    .sayac(sayac)
+);
+
+always begin
+    clk = ~clk; #1;
+end
+
+initial begin
+    $dumpfile("ayarliSayac.vcd");
+    $dumpvars;
+    clk = 1; rst = 0; en = 1; sayma_miktari = 3'b111; sayma_yonu = 1'b1; #32;
+    clk = 1; rst = 0; en = 1; sayma_miktari = 3'b111; sayma_yonu = 1'b1; #8;
+    clk = 1; rst = 0; en = 1; sayma_miktari = 3'b111; sayma_yonu = 1'b1; #64;
+    clk = 1; rst = 0; en = 1; sayma_miktari = 3'b111; sayma_yonu = 1'b1; #16;
+    clk = 1; rst = 1; en = 1; sayma_miktari = 3'b010; sayma_yonu = 1'b1; #8;
+    $finish;
+end
+
+endmodule

iverilog/tobb/lab5/knightRider

@@ -0,0 +1,101 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x55c07fb12c40 .scope module, "knightRiderTB" "knightRiderTB" 2 1;
+ .timescale 0 0;
+v0x55c07fb24010_0 .var "clk", 0 0;
+v0x55c07fb240e0_0 .net "leds", 7 0, v0x55c07fb23ef0_0;  1 drivers
+S_0x55c07fb12dd0 .scope module, "uut" "knightRider" 2 6, 3 1 0, S_0x55c07fb12c40;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /OUTPUT 8 "leds";
+v0x55c07fad87f0_0 .net "clk", 0 0, v0x55c07fb24010_0;  1 drivers
+v0x55c07fad8c00_0 .var "direction", 0 0;
+v0x55c07fb23ef0_0 .var "leds", 7 0;
+E_0x55c07fad7810 .event posedge, v0x55c07fad87f0_0;
+    .scope S_0x55c07fb12dd0;
+T_0 ;
+    %pushi/vec4 7, 0, 8;
+    %store/vec4 v0x55c07fb23ef0_0, 0, 8;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55c07fad8c00_0, 0, 1;
+    %end;
+    .thread T_0;
+    .scope S_0x55c07fb12dd0;
+T_1 ;
+    %wait E_0x55c07fad7810;
+    %load/vec4 v0x55c07fad8c00_0;
+    %pad/u 32;
+    %cmpi/e 0, 0, 32;
+    %jmp/0xz  T_1.0, 4;
+    %load/vec4 v0x55c07fb23ef0_0;
+    %cmpi/e 224, 0, 8;
+    %jmp/0xz  T_1.2, 4;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0x55c07fad8c00_0, 0;
+    %load/vec4 v0x55c07fb23ef0_0;
+    %ix/load 4, 1, 0;
+    %flag_set/imm 4, 0;
+    %shiftr 4;
+    %assign/vec4 v0x55c07fb23ef0_0, 0;
+    %jmp T_1.3;
+T_1.2 ;
+    %load/vec4 v0x55c07fb23ef0_0;
+    %ix/load 4, 1, 0;
+    %flag_set/imm 4, 0;
+    %shiftl 4;
+    %assign/vec4 v0x55c07fb23ef0_0, 0;
+T_1.3 ;
+    %jmp T_1.1;
+T_1.0 ;
+    %load/vec4 v0x55c07fb23ef0_0;
+    %cmpi/e 7, 0, 8;
+    %jmp/0xz  T_1.4, 4;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x55c07fad8c00_0, 0;
+    %load/vec4 v0x55c07fb23ef0_0;
+    %ix/load 4, 1, 0;
+    %flag_set/imm 4, 0;
+    %shiftl 4;
+    %assign/vec4 v0x55c07fb23ef0_0, 0;
+    %jmp T_1.5;
+T_1.4 ;
+    %load/vec4 v0x55c07fb23ef0_0;
+    %ix/load 4, 1, 0;
+    %flag_set/imm 4, 0;
+    %shiftr 4;
+    %assign/vec4 v0x55c07fb23ef0_0, 0;
+T_1.5 ;
+T_1.1 ;
+    %jmp T_1;
+    .thread T_1;
+    .scope S_0x55c07fb12c40;
+T_2 ;
+    %load/vec4 v0x55c07fb24010_0;
+    %inv;
+    %store/vec4 v0x55c07fb24010_0, 0, 1;
+    %delay 2, 0;
+    %jmp T_2;
+    .thread T_2;
+    .scope S_0x55c07fb12c40;
+T_3 ;
+    %vpi_call 2 16 "$dumpfile", "knightRider.vcd" {0 0 0};
+    %vpi_call 2 17 "$dumpvars" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55c07fb24010_0, 0, 1;
+    %delay 50, 0;
+    %vpi_call 2 19 "$finish" {0 0 0};
+    %end;
+    .thread T_3;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "knightRiderTB.v";
+    "knightRider.v";

iverilog/tobb/lab5/knightRider.v

@@ -0,0 +1,31 @@
+module knightRider (
+    input clk,
+    output reg [7:0] leds
+);
+
+reg direction;
+
+initial begin
+    leds = 8'b0000_0111;
+    direction = 1'b0; // 0 left to right
+end
+
+always@(posedge clk) begin
+if (direction == 0) begin
+    if (leds == 8'b1110_0000) begin
+        direction <= 1;
+        leds <= leds >> 1;
+    end else begin
+        leds <= leds << 1;
+    end
+end else begin
+        if (leds == 8'b0000_0111) begin
+            direction <= 0;
+            leds <= leds << 1;
+        end else begin
+            leds <= leds >> 1;
+        end
+    end
+end
+
+endmodule

iverilog/tobb/lab5/knightRider.vcd

@@ -0,0 +1,104 @@
+$date
+	Sat Jan 25 05:37:22 2025
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module knightRiderTB $end
+$var wire 8 ! leds [7:0] $end
+$var reg 1 " clk $end
+$scope module uut $end
+$var wire 1 " clk $end
+$var reg 1 # direction $end
+$var reg 8 $ leds [7:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b111 $
+0#
+0"
+b111 !
+$end
+#2
+b1110 !
+b1110 $
+1"
+#4
+0"
+#6
+b11100 !
+b11100 $
+1"
+#8
+0"
+#10
+b111000 !
+b111000 $
+1"
+#12
+0"
+#14
+b1110000 !
+b1110000 $
+1"
+#16
+0"
+#18
+b11100000 !
+b11100000 $
+1"
+#20
+0"
+#22
+b1110000 !
+b1110000 $
+1#
+1"
+#24
+0"
+#26
+b111000 !
+b111000 $
+1"
+#28
+0"
+#30
+b11100 !
+b11100 $
+1"
+#32
+0"
+#34
+b1110 !
+b1110 $
+1"
+#36
+0"
+#38
+b111 !
+b111 $
+1"
+#40
+0"
+#42
+b1110 !
+b1110 $
+0#
+1"
+#44
+0"
+#46
+b11100 !
+b11100 $
+1"
+#48
+0"
+#50
+b111000 !
+b111000 $
+1"

iverilog/tobb/lab5/knightRiderTB.v

@@ -0,0 +1,22 @@
+module knightRiderTB();
+
+reg clk;
+wire [7:0] leds;
+
+knightRider uut (
+    .clk(clk),
+    .leds(leds)
+);
+
+always begin
+    clk = ~clk; #2;
+end
+
+initial begin
+    $dumpfile("knightRider.vcd");
+    $dumpvars;
+    clk = 0; #50;
+    $finish;
+end
+
+endmodule

iverilog/tobb/lab5/sayac.v

@@ -0,0 +1,48 @@
+module sayac (
+    input clk, rst, en,
+    input [2:0] sayma_miktari,
+    input sayma_yonu,
+    output reg [5:0] sayac
+);
+
+    reg [1:0] clk_divider;
+    reg [2:0] miktar;
+
+    initial begin
+        sayac = 6'b0000_00;
+        miktar = 3'b001;
+        clk_divider = 2'b00;
+    end
+
+    always@(*) begin
+    miktar = sayma_miktari;
+    end
+
+    always@(negedge clk or posedge rst) begin
+        if (rst) begin
+            sayac <= 6'b0000_00;
+            clk_divider <= 2'b00;
+        end else begin
+            clk_divider <= clk_divider + 1;
+        end
+
+        if (clk_divider == 2'b11) begin
+            clk_divider <= 2'b00;
+            if (en) begin
+                if (sayma_miktari) begin
+                    if (sayac + miktar >= 6'b1111_11) begin
+                        sayac <= 6'b1111_11;
+                    end else begin
+                        sayac <= sayac + miktar;
+                    end
+                end else begin
+                    if (miktar >= sayac) begin
+                        sayac <= 6'b0000_00;
+                    end else begin
+                        sayac <= sayac - miktar;
+                    end
+                end
+            end
+        end
+    end
+endmodule

iverilog/tobb/lab5/tetris

@@ -0,0 +1,177 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x56335d23e170 .scope module, "tetrisTB" "tetrisTB" 2 1;
+ .timescale 0 0;
+v0x56335d253500_0 .net "bitti_mi", 0 0, v0x56335d200370_0;  1 drivers
+v0x56335d2535c0_0 .net "cevrim", 3 0, v0x56335d200c00_0;  1 drivers
+v0x56335d253690_0 .var "clk", 0 0;
+v0x56335d253790_0 .var "p", 2 0;
+v0x56335d253860_0 .net "yukseklik", 3 0, v0x56335d253090_0;  1 drivers
+S_0x56335d23e300 .scope module, "uut" "tetris" 2 9, 3 1 0, S_0x56335d23e170;
+ .timescale 0 0;
+    .port_info 0 /INPUT 3 "parca";
+    .port_info 1 /INPUT 1 "clk";
+    .port_info 2 /OUTPUT 4 "yukseklik";
+    .port_info 3 /OUTPUT 1 "bitti_mi";
+    .port_info 4 /OUTPUT 4 "cevrim";
+v0x56335d200370_0 .var "bitti_mi", 0 0;
+v0x56335d200c00_0 .var "cevrim", 3 0;
+v0x56335d252ee0_0 .net "clk", 0 0, v0x56335d253690_0;  1 drivers
+v0x56335d252fb0_0 .net "parca", 2 0, v0x56335d253790_0;  1 drivers
+v0x56335d253090_0 .var "yukseklik", 3 0;
+v0x56335d2531c0_0 .var "yukseklik1", 3 0;
+v0x56335d2532a0_0 .var "yukseklik2", 3 0;
+v0x56335d253380_0 .var "yukseklik3", 3 0;
+E_0x56335d238670 .event posedge, v0x56335d252ee0_0;
+    .scope S_0x56335d23e300;
+T_0 ;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x56335d200c00_0, 0, 4;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x56335d200370_0, 0, 1;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x56335d253090_0, 0, 4;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x56335d2531c0_0, 0, 4;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x56335d2532a0_0, 0, 4;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x56335d253380_0, 0, 4;
+    %end;
+    .thread T_0;
+    .scope S_0x56335d23e300;
+T_1 ;
+    %wait E_0x56335d238670;
+    %load/vec4 v0x56335d200370_0;
+    %nor/r;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.0, 8;
+    %load/vec4 v0x56335d252fb0_0;
+    %parti/s 1, 0, 2;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.2, 8;
+    %load/vec4 v0x56335d2531c0_0;
+    %addi 1, 0, 4;
+    %assign/vec4 v0x56335d2531c0_0, 0;
+T_1.2 ;
+    %load/vec4 v0x56335d252fb0_0;
+    %parti/s 1, 1, 2;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.4, 8;
+    %load/vec4 v0x56335d2532a0_0;
+    %addi 1, 0, 4;
+    %assign/vec4 v0x56335d2532a0_0, 0;
+T_1.4 ;
+    %load/vec4 v0x56335d252fb0_0;
+    %parti/s 1, 2, 3;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.6, 8;
+    %load/vec4 v0x56335d253380_0;
+    %addi 1, 0, 4;
+    %assign/vec4 v0x56335d253380_0, 0;
+T_1.6 ;
+    %load/vec4 v0x56335d200c00_0;
+    %addi 1, 0, 4;
+    %assign/vec4 v0x56335d200c00_0, 0;
+    %load/vec4 v0x56335d200c00_0;
+    %cmpi/e 15, 0, 4;
+    %jmp/0xz  T_1.8, 4;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0x56335d200370_0, 0;
+T_1.8 ;
+T_1.0 ;
+    %jmp T_1;
+    .thread T_1;
+    .scope S_0x56335d23e300;
+T_2 ;
+    %wait E_0x56335d238670;
+    %load/vec4 v0x56335d200370_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_2.0, 8;
+    %load/vec4 v0x56335d2532a0_0;
+    %load/vec4 v0x56335d2531c0_0;
+    %cmp/u;
+    %flag_get/vec4 4;
+    %flag_get/vec4 5;
+    %or;
+    %load/vec4 v0x56335d253380_0;
+    %load/vec4 v0x56335d2531c0_0;
+    %cmp/u;
+    %flag_get/vec4 4;
+    %flag_get/vec4 5;
+    %or;
+    %and;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_2.2, 8;
+    %load/vec4 v0x56335d2531c0_0;
+    %assign/vec4 v0x56335d253090_0, 0;
+    %jmp T_2.3;
+T_2.2 ;
+    %load/vec4 v0x56335d2531c0_0;
+    %load/vec4 v0x56335d2532a0_0;
+    %cmp/u;
+    %flag_get/vec4 4;
+    %flag_get/vec4 5;
+    %or;
+    %load/vec4 v0x56335d253380_0;
+    %load/vec4 v0x56335d2532a0_0;
+    %cmp/u;
+    %flag_get/vec4 4;
+    %flag_get/vec4 5;
+    %or;
+    %and;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_2.4, 8;
+    %load/vec4 v0x56335d2532a0_0;
+    %assign/vec4 v0x56335d253090_0, 0;
+    %jmp T_2.5;
+T_2.4 ;
+    %load/vec4 v0x56335d253380_0;
+    %assign/vec4 v0x56335d253090_0, 0;
+T_2.5 ;
+T_2.3 ;
+T_2.0 ;
+    %jmp T_2;
+    .thread T_2;
+    .scope S_0x56335d23e170;
+T_3 ;
+    %load/vec4 v0x56335d253690_0;
+    %inv;
+    %store/vec4 v0x56335d253690_0, 0, 1;
+    %delay 1, 0;
+    %jmp T_3;
+    .thread T_3;
+    .scope S_0x56335d23e170;
+T_4 ;
+    %vpi_call 2 22 "$dumpfile", "tetris.vcd" {0 0 0};
+    %vpi_call 2 23 "$dumpvars" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x56335d253690_0, 0, 1;
+    %pushi/vec4 2, 0, 3;
+    %store/vec4 v0x56335d253790_0, 0, 3;
+    %delay 2, 0;
+    %pushi/vec4 3, 0, 3;
+    %store/vec4 v0x56335d253790_0, 0, 3;
+    %delay 2, 0;
+    %pushi/vec4 2, 0, 3;
+    %store/vec4 v0x56335d253790_0, 0, 3;
+    %delay 2, 0;
+    %pushi/vec4 0, 0, 3;
+    %store/vec4 v0x56335d253790_0, 0, 3;
+    %delay 30, 0;
+    %vpi_call 2 28 "$finish" {0 0 0};
+    %end;
+    .thread T_4;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "tetrisTB.v";
+    "tetris.v";

iverilog/tobb/lab5/tetris.v

@@ -0,0 +1,49 @@
+module tetris (
+    input [2:0] parca,
+    input clk,
+    output reg [3:0] yukseklik,
+    output reg bitti_mi,
+    output reg [3:0] cevrim
+);
+
+    reg [3:0] yukseklik1, yukseklik2, yukseklik3;
+    initial begin
+        cevrim = 4'd0;
+        bitti_mi = 1'b0;
+        yukseklik = 4'b0;
+        yukseklik1 = 4'd0;
+        yukseklik2 = 4'd0;
+        yukseklik3 = 4'd0;
+    end
+
+
+    always@(posedge clk) begin
+        if (!bitti_mi) begin
+            if (parca[0]) begin
+            yukseklik1 <= yukseklik1 + 1;
+            end if (parca[1]) begin
+                yukseklik2 <= yukseklik2 + 1;
+            end if (parca[2]) begin
+                yukseklik3 <= yukseklik3 + 1;
+            end
+         cevrim <= cevrim + 1;
+
+         if (cevrim == 4'd15) begin
+            bitti_mi <= 1'b1;
+         end
+    end
+end
+
+always@(posedge clk) begin //comperator
+    if (bitti_mi) begin
+        if (yukseklik1 >= yukseklik2 && yukseklik1 >= yukseklik3) begin
+            yukseklik <= yukseklik1;
+        end else if (yukseklik2 >= yukseklik1 && yukseklik2 >= yukseklik3) begin
+            yukseklik <= yukseklik2;
+        end else begin
+            yukseklik <= yukseklik3;
+        end
+    end
+end
+
+endmodule

iverilog/tobb/lab5/tetris.vcd

@@ -0,0 +1,158 @@
+$date
+	Sun Jan 26 06:03:11 2025
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module tetrisTB $end
+$var wire 4 ! yukseklik [3:0] $end
+$var wire 4 " cevrim [3:0] $end
+$var wire 1 # bitti_mi $end
+$var reg 1 $ clk $end
+$var reg 3 % p [2:0] $end
+$scope module uut $end
+$var wire 1 $ clk $end
+$var wire 3 & parca [2:0] $end
+$var reg 1 # bitti_mi $end
+$var reg 4 ' cevrim [3:0] $end
+$var reg 4 ( yukseklik [3:0] $end
+$var reg 4 ) yukseklik1 [3:0] $end
+$var reg 4 * yukseklik2 [3:0] $end
+$var reg 4 + yukseklik3 [3:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b0 +
+b0 *
+b0 )
+b0 (
+b0 '
+b10 &
+b10 %
+0$
+0#
+b0 "
+b0 !
+$end
+#1
+b1 "
+b1 '
+b1 *
+1$
+#2
+0$
+b11 %
+b11 &
+#3
+b10 "
+b10 '
+b10 *
+b1 )
+1$
+#4
+0$
+b10 %
+b10 &
+#5
+b11 "
+b11 '
+b11 *
+1$
+#6
+0$
+b0 %
+b0 &
+#7
+b100 "
+b100 '
+1$
+#8
+0$
+#9
+b101 "
+b101 '
+1$
+#10
+0$
+#11
+b110 "
+b110 '
+1$
+#12
+0$
+#13
+b111 "
+b111 '
+1$
+#14
+0$
+#15
+b1000 "
+b1000 '
+1$
+#16
+0$
+#17
+b1001 "
+b1001 '
+1$
+#18
+0$
+#19
+b1010 "
+b1010 '
+1$
+#20
+0$
+#21
+b1011 "
+b1011 '
+1$
+#22
+0$
+#23
+b1100 "
+b1100 '
+1$
+#24
+0$
+#25
+b1101 "
+b1101 '
+1$
+#26
+0$
+#27
+b1110 "
+b1110 '
+1$
+#28
+0$
+#29
+b1111 "
+b1111 '
+1$
+#30
+0$
+#31
+1#
+b0 "
+b0 '
+1$
+#32
+0$
+#33
+b11 !
+b11 (
+1$
+#34
+0$
+#35
+1$
+#36
+0$

iverilog/tobb/lab5/tetrisTB.v

@@ -0,0 +1,31 @@
+module tetrisTB();
+
+    reg [2:0] p;
+    reg clk;
+    wire [3:0] yukseklik;
+    wire bitti_mi;
+    wire [3:0] cevrim;
+
+tetris uut (
+    .parca(p),
+    .clk(clk),
+    .yukseklik(yukseklik),
+    .bitti_mi(bitti_mi),
+    .cevrim(cevrim)
+);
+
+    always begin
+        clk = ~clk; #1;
+    end
+
+initial begin
+    $dumpfile("tetris.vcd");
+    $dumpvars;
+    clk = 0; p = 3'b010; #2;
+    p = 3'b011; #2;
+    p = 3'b010; #2;
+    p = 3'b000; #30;
+    $finish;
+end
+
+endmodule

iverilog/tobb/lab6/bibp

@@ -0,0 +1,286 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x55e76f51ca80 .scope module, "bibpTB" "bibpTB" 2 1;
+ .timescale 0 0;
+P_0x55e76f51cc10 .param/l "N" 0 2 2, +C4<00000000000000000000000000000011>;
+v0x55e76f534860_0 .var "A", 8 0;
+v0x55e76f534920_0 .net "sonuc", 3 0, v0x55e76f534720_0;  1 drivers
+S_0x55e76f51ccb0 .scope module, "uut" "bibp" 2 6, 3 1 0, S_0x55e76f51ca80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 9 "buyruk";
+    .port_info 1 /OUTPUT 4 "sonuc";
+P_0x55e76f51d420 .param/l "N" 0 3 1, +C4<00000000000000000000000000000011>;
+v0x55e76f4d8cf0_0 .var/i "a", 31 0;
+v0x55e76f534290_0 .var/i "b", 31 0;
+v0x55e76f534370_0 .net "buyruk", 8 0, v0x55e76f534860_0;  1 drivers
+v0x55e76f534430_0 .var/i "c", 31 0;
+v0x55e76f534510_0 .var/i "count", 31 0;
+v0x55e76f534640_0 .var/i "i", 31 0;
+v0x55e76f534720_0 .var "sonuc", 3 0;
+E_0x55e76f511f90 .event edge, v0x55e76f534370_0;
+    .scope S_0x55e76f51ccb0;
+T_0 ;
+    %wait E_0x55e76f511f90;
+    %load/vec4 v0x55e76f534370_0;
+    %parti/s 3, 6, 4;
+    %dup/vec4;
+    %pushi/vec4 0, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.1, 6;
+    %dup/vec4;
+    %pushi/vec4 1, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.2, 6;
+    %dup/vec4;
+    %pushi/vec4 2, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.3, 6;
+    %dup/vec4;
+    %pushi/vec4 3, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.4, 6;
+    %dup/vec4;
+    %pushi/vec4 4, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.5, 6;
+    %dup/vec4;
+    %pushi/vec4 5, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.6, 6;
+    %dup/vec4;
+    %pushi/vec4 6, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.7, 6;
+    %dup/vec4;
+    %pushi/vec4 7, 0, 3;
+    %cmp/u;
+    %jmp/1 T_0.8, 6;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x55e76f534720_0, 0, 4;
+    %jmp T_0.9;
+T_0.1 ;
+    %load/vec4 v0x55e76f534370_0;
+    %parti/s 3, 3, 3;
+    %pad/u 4;
+    %load/vec4 v0x55e76f534370_0;
+    %parti/s 3, 0, 2;
+    %pad/u 4;
+    %add;
+    %store/vec4 v0x55e76f534720_0, 0, 4;
+    %jmp T_0.9;
+T_0.2 ;
+    %load/vec4 v0x55e76f534370_0;
+    %parti/s 3, 3, 3;
+    %pad/u 4;
+    %load/vec4 v0x55e76f534370_0;
+    %parti/s 3, 0, 2;
+    %pad/u 4;
+    %sub;
+    %store/vec4 v0x55e76f534720_0, 0, 4;
+    %jmp T_0.9;
+T_0.3 ;
+    %load/vec4 v0x55e76f534370_0;
+    %parti/s 3, 3, 3;
+    %pad/u 4;
+    %load/vec4 v0x55e76f534370_0;
+    %parti/s 3, 0, 2;
+    %pad/u 4;
+    %and;
+    %store/vec4 v0x55e76f534720_0, 0, 4;
+    %jmp T_0.9;
+T_0.4 ;
+    %load/vec4 v0x55e76f534370_0;
+    %parti/s 3, 3, 3;
+    %pad/u 4;
+    %load/vec4 v0x55e76f534370_0;
+    %parti/s 3, 0, 2;
+    %pad/u 4;
+    %or;
+    %store/vec4 v0x55e76f534720_0, 0, 4;
+    %jmp T_0.9;
+T_0.5 ;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x55e76f534640_0, 0, 32;
+T_0.10 ;
+    %load/vec4 v0x55e76f534640_0;
+    %cmpi/s 4, 0, 32;
+    %flag_or 5, 4;
+    %jmp/0xz T_0.11, 5;
+    %load/vec4 v0x55e76f534370_0;
+    %load/vec4 v0x55e76f534640_0;
+    %part/s 1;
+    %load/vec4 v0x55e76f534370_0;
+    %load/vec4 v0x55e76f534640_0;
+    %addi 1, 0, 32;
+    %part/s 1;
+    %cmp/e;
+    %jmp/0xz  T_0.12, 4;
+    %pushi/vec4 15, 0, 4;
+    %store/vec4 v0x55e76f534720_0, 0, 4;
+    %jmp T_0.13;
+T_0.12 ;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x55e76f534720_0, 0, 4;
+T_0.13 ;
+    ; show_stmt_assign_vector: Get l-value for compressed += operand
+    %load/vec4 v0x55e76f534640_0;
+    %pushi/vec4 1, 0, 32;
+    %add;
+    %store/vec4 v0x55e76f534640_0, 0, 32;
+    %jmp T_0.10;
+T_0.11 ;
+    %jmp T_0.9;
+T_0.6 ;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x55e76f534720_0, 0, 4;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x55e76f4d8cf0_0, 0, 32;
+T_0.14 ;
+    %load/vec4 v0x55e76f4d8cf0_0;
+    %cmpi/s 6, 0, 32;
+    %jmp/0xz T_0.15, 5;
+    %load/vec4 v0x55e76f534370_0;
+    %load/vec4 v0x55e76f4d8cf0_0;
+    %part/s 1;
+    %pad/u 32;
+    %cmpi/e 1, 0, 32;
+    %jmp/0xz  T_0.16, 4;
+    %pushi/vec4 15, 0, 4;
+    %store/vec4 v0x55e76f534720_0, 0, 4;
+T_0.16 ;
+    ; show_stmt_assign_vector: Get l-value for compressed += operand
+    %load/vec4 v0x55e76f4d8cf0_0;
+    %pushi/vec4 1, 0, 32;
+    %add;
+    %store/vec4 v0x55e76f4d8cf0_0, 0, 32;
+    %jmp T_0.14;
+T_0.15 ;
+    %jmp T_0.9;
+T_0.7 ;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x55e76f534510_0, 0, 32;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x55e76f534290_0, 0, 32;
+T_0.18 ;
+    %load/vec4 v0x55e76f534290_0;
+    %cmpi/s 6, 0, 32;
+    %jmp/0xz T_0.19, 5;
+    %load/vec4 v0x55e76f534370_0;
+    %load/vec4 v0x55e76f534290_0;
+    %part/s 1;
+    %pad/u 32;
+    %cmpi/e 1, 0, 32;
+    %jmp/0xz  T_0.20, 4;
+    %load/vec4 v0x55e76f534510_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0x55e76f534510_0, 0, 32;
+T_0.20 ;
+    ; show_stmt_assign_vector: Get l-value for compressed += operand
+    %load/vec4 v0x55e76f534290_0;
+    %pushi/vec4 1, 0, 32;
+    %add;
+    %store/vec4 v0x55e76f534290_0, 0, 32;
+    %jmp T_0.18;
+T_0.19 ;
+    %load/vec4 v0x55e76f534510_0;
+    %pushi/vec4 2, 0, 32;
+    %mod/s;
+    %cmpi/e 0, 0, 32;
+    %jmp/0xz  T_0.22, 4;
+    %pushi/vec4 15, 0, 4;
+    %store/vec4 v0x55e76f534720_0, 0, 4;
+    %jmp T_0.23;
+T_0.22 ;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x55e76f534720_0, 0, 4;
+T_0.23 ;
+    %jmp T_0.9;
+T_0.8 ;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x55e76f534510_0, 0, 32;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x55e76f534430_0, 0, 32;
+T_0.24 ;
+    %load/vec4 v0x55e76f534430_0;
+    %cmpi/s 6, 0, 32;
+    %jmp/0xz T_0.25, 5;
+    %load/vec4 v0x55e76f534370_0;
+    %load/vec4 v0x55e76f534430_0;
+    %part/s 1;
+    %pad/u 32;
+    %cmpi/e 1, 0, 32;
+    %jmp/0xz  T_0.26, 4;
+    %load/vec4 v0x55e76f534510_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0x55e76f534510_0, 0, 32;
+T_0.26 ;
+    ; show_stmt_assign_vector: Get l-value for compressed += operand
+    %load/vec4 v0x55e76f534430_0;
+    %pushi/vec4 1, 0, 32;
+    %add;
+    %store/vec4 v0x55e76f534430_0, 0, 32;
+    %jmp T_0.24;
+T_0.25 ;
+    %load/vec4 v0x55e76f534510_0;
+    %pushi/vec4 2, 0, 32;
+    %mod/s;
+    %cmpi/e 0, 0, 32;
+    %jmp/0xz  T_0.28, 4;
+    %pushi/vec4 0, 0, 4;
+    %store/vec4 v0x55e76f534720_0, 0, 4;
+    %jmp T_0.29;
+T_0.28 ;
+    %pushi/vec4 15, 0, 4;
+    %store/vec4 v0x55e76f534720_0, 0, 4;
+T_0.29 ;
+    %jmp T_0.9;
+T_0.9 ;
+    %pop/vec4 1;
+    %jmp T_0;
+    .thread T_0, $push;
+    .scope S_0x55e76f51ca80;
+T_1 ;
+    %vpi_call 2 12 "$dumpfile", "bibp.vcd" {0 0 0};
+    %vpi_call 2 13 "$dumpvars" {0 0 0};
+    %pushi/vec4 9, 0, 9;
+    %store/vec4 v0x55e76f534860_0, 0, 9;
+    %delay 5, 0;
+    %pushi/vec4 97, 0, 9;
+    %store/vec4 v0x55e76f534860_0, 0, 9;
+    %delay 5, 0;
+    %pushi/vec4 165, 0, 9;
+    %store/vec4 v0x55e76f534860_0, 0, 9;
+    %delay 5, 0;
+    %pushi/vec4 227, 0, 9;
+    %store/vec4 v0x55e76f534860_0, 0, 9;
+    %delay 5, 0;
+    %pushi/vec4 319, 0, 9;
+    %store/vec4 v0x55e76f534860_0, 0, 9;
+    %delay 5, 0;
+    %pushi/vec4 289, 0, 9;
+    %store/vec4 v0x55e76f534860_0, 0, 9;
+    %delay 5, 0;
+    %pushi/vec4 353, 0, 9;
+    %store/vec4 v0x55e76f534860_0, 0, 9;
+    %delay 5, 0;
+    %pushi/vec4 417, 0, 9;
+    %store/vec4 v0x55e76f534860_0, 0, 9;
+    %delay 5, 0;
+    %pushi/vec4 481, 0, 9;
+    %store/vec4 v0x55e76f534860_0, 0, 9;
+    %delay 5, 0;
+    %end;
+    .thread T_1;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "bibpTB.v";
+    "bibp.v";

iverilog/tobb/lab6/bibp.v

@@ -0,0 +1,56 @@
+module bibp #(parameter N = 3) (
+    input [(N*2)+2:0] buyruk,
+    output reg [N:0] sonuc
+);
+    integer i, a, b, c, count;
+
+    always @(buyruk) begin
+        case (buyruk[(N*2)+2:N*2])
+            default: sonuc = {(N+1){1'b0}};
+
+            3'b000: sonuc = buyruk[(N*2)-1:(N*2)-3] + buyruk[(N*2)-4:0];
+            3'b001: sonuc = buyruk[(N*2)-1:(N*2)-3] - buyruk[(N*2)-4:0];
+            3'b010: sonuc = buyruk[(N*2)-1:(N*2)-3] & buyruk[(N*2)-4:0];
+            3'b011: sonuc = buyruk[(N*2)-1:(N*2)-3] | buyruk[(N*2)-4:0];
+
+            3'b100: begin
+            for (i = 0; i <= (N*2)-2; i++)
+                if (buyruk[i] == buyruk[i+1])
+                    sonuc = {(N+1){1'b1}};
+                else
+                    sonuc = {(N+1){1'b0}};
+            end
+            3'b101: begin
+                sonuc = {(N+1){1'b0}};
+                for (a = 0; a < (N*2); a++) begin
+                    if (buyruk[a] == 1)
+                        sonuc =  {(N+1){1'b1}};
+                end
+            end
+
+            3'b110: begin
+                count = 0;
+                for (b = 0; b < (N*2); b++) begin
+                    if (buyruk[b] == 1)
+                        count = count + 1;
+                end
+                if (count % 2 == 0)
+                    sonuc = {(N+1){1'b1}};
+                else
+                    sonuc = {(N+1){1'b0}};
+            end
+
+            3'b111: begin
+                count = 0;
+                for (c = 0; c < (N*2); c++) begin
+                    if (buyruk[c] == 1)
+                        count = count + 1;
+                end
+                if (count % 2 == 0)
+                    sonuc = {(N+1){1'b0}};
+                else
+                    sonuc = {(N+1){1'b1}};
+            end
+        endcase
+    end
+endmodule