kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Compare commits

base: kaltinsoy:15916a2c534beff06a16239dd4912b40b7f837b6
Branches Tags
kaltinsoy:main
..
compare: kaltinsoy:main
Branches Tags
kaltinsoy:main

12 Commits
15916a2c53 ... main

Author SHA1 Message Date
k0rrluna
ee84dbe799 lab7 2025-02-03 22:46:58 +03:00
k0rrluna
1d5ff13ca1 labs 2025-02-01 06:35:32 +03:00
k0rrluna
57c2935e1c lab7 2025-01-30 07:23:51 +03:00
k0rrluna
85dbb22740 lab6 2025-01-30 06:50:00 +03:00
k0rrluna
1b0958962c lab5 2025-01-26 06:05:52 +03:00
k0rrluna
7605bbf473 lab5 2025-01-25 08:00:40 +03:00
k0rrluna
c5e6bb95a0 lab4 2025-01-25 03:15:10 +03:00
k0rrluna
0f359fa8a4 f# fix 2025-01-23 07:58:44 +03:00
k0rrluna
8003e7f253 fpga 2025-01-23 05:25:40 +03:00
k0rrluna
e91a8471ac final fpga 2025-01-21 05:12:57 +03:00
k0rrluna
6b83c0f2e7 merge 2025-01-21 05:12:02 +03:00
k0rrluna
8e613a767e tangFpga 2025-01-20 18:23:08 +03:00
80 changed files with 5240 additions and 19235 deletions
Expand all files Collapse all files

4
gowin/bttn/bttn.gprj
View File

@ -9,7 +9,6 @@
<File path="src/BinaryToBCD.v" type="file.verilog" enable="1"/> <File path="src/BinaryToBCD.v" type="file.verilog" enable="1"/>
<File path="src/addition.v" type="file.verilog" enable="1"/> <File path="src/addition.v" type="file.verilog" enable="1"/>
<File path="src/arithmeticUnit.v" type="file.verilog" enable="1"/> <File path="src/arithmeticUnit.v" type="file.verilog" enable="1"/>
<File path="src/bttn.v" type="file.verilog" enable="1"/>
<File path="src/dabble.v" type="file.verilog" enable="1"/> <File path="src/dabble.v" type="file.verilog" enable="1"/>
<File path="src/fulladder.v" type="file.verilog" enable="1"/> <File path="src/fulladder.v" type="file.verilog" enable="1"/>
<File path="src/fullsubtraction.v" type="file.verilog" enable="1"/> <File path="src/fullsubtraction.v" type="file.verilog" enable="1"/>
@ -20,6 +19,7 @@
<File path="src/opCode.v" type="file.verilog" enable="1"/> <File path="src/opCode.v" type="file.verilog" enable="1"/>
<File path="src/selector.v" type="file.verilog" enable="1"/> <File path="src/selector.v" type="file.verilog" enable="1"/>
<File path="src/subtraction.v" type="file.verilog" enable="1"/> <File path="src/subtraction.v" type="file.verilog" enable="1"/>
<File path="src/bttn.cst" type="file.cst" enable="1"/> <File path="src/top.v" type="file.verilog" enable="1"/>
<File path="src/top.cst" type="file.cst" enable="1"/>
</FileList> </FileList>
</Project> </Project>

2
gowin/bttn/bttn.gprj.user
View File

@ -22,6 +22,6 @@
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/bttn_syn.rpt.html"/> <ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/bttn_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/bttn_syn_rsc.xml"/> <ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/bttn_syn_rsc.xml"/>
</ResultFileList> </ResultFileList>
<Ui>000000ff00000001fd00000002000000000000018e0000025dfc0200000001fc000000370000025d0000000000fffffffaffffffff0200000004fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000000000030000078000000145fc0100000001fc00000000000007800000009b00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000009b00ffffff000005ee0000025d00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000000000280043006f00720065002e0054006f006f006c006200610072002e00500072006f00630065007300730100000245ffffffff0000000000000000</Ui> <Ui>000000ff00000001fd00000002000000000000018e0000025dfc0200000001fc000000370000025d0000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000078000000145fc0100000001fc0000000000000780000000a100fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100ffffff000005ee0000025d00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000000000280043006f00720065002e0054006f006f006c006200610072002e00500072006f00630065007300730100000245ffffffff0000000000000000</Ui>
<FpUi></FpUi> <FpUi></FpUi>
</UserConfig> </UserConfig>

92
gowin/bttn/impl/bttn_process_config.json
View File

@ -1,92 +0,0 @@
{
"BACKGROUND_PROGRAMMING" : "off",
"COMPRESS" : false,
"CPU" : false,
"CRC_CHECK" : true,
"Clock_Route_Order" : 0,
"Convert_SDP32_36_to_SDP16_18" : true,
"Correct_Hold_Violation" : true,
"DONE" : false,
"DOWNLOAD_SPEED" : "default",
"Disable_Insert_Pad" : false,
"ENABLE_CTP" : false,
"ENABLE_MERGE_MODE" : false,
"ENCRYPTION_KEY" : false,
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
"ERROR_DECTION_AND_CORRECTION" : false,
"ERROR_DECTION_ONLY" : false,
"ERROR_INJECTION" : false,
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
"Enable_DSRM" : false,
"FORMAT" : "binary",
"FREQUENCY_DIVIDER" : "1",
"Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false,
"Generate_Post_PNR_Simulation_Model_File" : false,
"Generate_Post_Place_File" : false,
"Generate_SDF_File" : false,
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
"Global_Freq" : "default",
"GwSyn_Loop_Limit" : 2000,
"HOTBOOT" : false,
"I2C" : false,
"I2C_SLAVE_ADDR" : "00",
"INCREMENTAL_PLACE_AND_ROUTING" : "0",
"INCREMENTAL_PLACE_ONLY" : "0",
"IncludePath" : [
],
"Incremental_Compile" : "",
"Initialize_Primitives" : false,
"JTAG" : false,
"MODE_IO" : false,
"MSPI" : false,
"MSPI_JUMP" : false,
"MULTIBOOT_ADDRESS_WIDTH" : "24",
"MULTIBOOT_MODE" : "Normal",
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
"MULTIJUMP_ADDRESS_WIDTH" : "24",
"MULTIJUMP_MODE" : "Normal",
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
"Multi_Boot" : true,
"OUTPUT_BASE_NAME" : "bttn",
"POWER_ON_RESET_MONITOR" : true,
"PRINT_BSRAM_VALUE" : true,
"PROGRAM_DONE_BYPASS" : false,
"PlaceInRegToIob" : true,
"PlaceIoRegToIob" : true,
"PlaceOutRegToIob" : true,
"Place_Option" : "0",
"Process_Configuration_Verion" : "1.0",
"Promote_Physical_Constraint_Warning_to_Error" : true,
"READY" : false,
"RECONFIG_N" : false,
"Ram_RW_Check" : false,
"Replicate_Resources" : false,
"Report_Auto-Placed_Io_Information" : false,
"Route_Maxfan" : 23,
"Route_Option" : "0",
"Run_Timing_Driven" : true,
"SECURE_MODE" : false,
"SECURITY_BIT" : true,
"SEU_HANDLER" : false,
"SEU_HANDLER_CHECKSUM" : false,
"SEU_HANDLER_MODE" : "auto",
"SSPI" : false,
"STOP_SEU_HANDLER" : false,
"Show_All_Warnings" : false,
"Synthesize_tool" : "GowinSyn",
"TclPre" : "",
"TopModule" : "",
"USERCODE" : "default",
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
"VCC" : "1.0",
"VCCAUX" : 3.3,
"VCCX" : "3.3",
"VHDL_Standard" : "VHDL_Std_1993",
"Verilog_Standard" : "Vlg_Std_2001",
"WAKE_UP" : "0",
"show_all_warnings" : false,
"turn_off_bg" : false
}

130
gowin/bttn/impl/gwsynthesis/bttn.log
View File

@ -1,130 +0,0 @@
GowinSynthesis start
Running parser ...
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v'
Compiling module 'bttn'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v":1)
Compiling module 'ALU'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":1)
Compiling module 'opCode'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v":1)
Compiling module 'arithmeticUnit'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v":1)
Compiling module 'addition'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":1)
Compiling module 'fulladder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":1)
Compiling module 'halfadder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v":1)
Compiling module 'subtraction'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":1)
Compiling module 'fullsubtraction'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":1)
Compiling module 'halfsubtraction'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v":1)
Compiling module 'logicUnit'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v":1)
Compiling module 'multiplier'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":1)
Compiling module 'BinaryToBCD'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":1)
Compiling module 'dabble'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v":1)
Compiling module 'selector'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v":1)
NOTE (EX0101) : Current top module is "bttn"
[5%] Running netlist conversion ...
Running device independent optimization ...
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "ALU" instantiated to "a1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v":10)
WARN (NL0002) : The module "arithmeticUnit" instantiated to "aU" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":20)
WARN (NL0002) : The module "addition" instantiated to "a1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v":13)
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "subtraction" instantiated to "s1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v":14)
WARN (NL0002) : The module "fullsubtraction" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":11)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
WARN (NL0002) : The module "fullsubtraction" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":12)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
WARN (NL0002) : The module "fullsubtraction" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":13)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
WARN (NL0002) : The module "fullsubtraction" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":14)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
WARN (NL0002) : The module "BinaryToBCD" instantiated to "btod1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":76)
WARN (NL0002) : The module "dabble" instantiated to "d1t" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":21)
WARN (NL0002) : The module "dabble" instantiated to "d2u" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":30)
WARN (NL0002) : The module "dabble" instantiated to "d3v" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":39)
WARN (NL0002) : The module "dabble" instantiated to "d4w" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":48)
WARN (NL0002) : The module "dabble" instantiated to "d5x" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":57)
WARN (NL0002) : The module "dabble" instantiated to "d6y" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":66)
WARN (NL0002) : The module "dabble" instantiated to "d7z" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":75)
WARN (NL0002) : The module "logicUnit" instantiated to "lU" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":21)
WARN (NL0002) : The module "multiplier" instantiated to "mU" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":22)
WARN (NL0002) : The module "addition" instantiated to "add0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":33)
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "addition" instantiated to "add1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":49)
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "addition" instantiated to "add2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":65)
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
WARN (NL0002) : The module "opCode" instantiated to "opCd" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":18)
[95%] Generate netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg" completed
[100%] Generate report file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn_syn.rpt.html" completed
GowinSynthesis finish

33
gowin/bttn/impl/gwsynthesis/bttn.prj
View File

@ -1,33 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
<Version>beta</Version>
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
<FileList>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v" type="verilog"/>
</FileList>
<OptionList>
<Option type="disable_insert_pad" value="0"/>
<Option type="global_freq" value="100.000"/>
<Option type="looplimit" value="2000"/>
<Option type="output_file" value="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg"/>
<Option type="print_all_synthesis_warning" value="0"/>
<Option type="ram_rw_check" value="0"/>
<Option type="verilog_language" value="verilog-2001"/>
<Option type="vhdl_language" value="vhdl-1993"/>
</OptionList>
</Project>

442
gowin/bttn/impl/gwsynthesis/bttn.vg
View File

@ -1,442 +0,0 @@
//
//Written by GowinSynthesis
//Tool Version "V1.9.9.03 Education (64-bit)"
//Sat Jan 18 22:12:34 2025
//Source file index table:
//file0 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v"
//file1 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v"
//file2 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v"
//file3 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v"
//file4 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v"
//file5 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v"
//file6 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v"
//file7 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v"
//file8 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v"
//file9 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v"
//file10 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/logicUnit.v"
//file11 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v"
//file12 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/opCode.v"
//file13 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/selector.v"
//file14 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v"
`pragma protect begin_protected
`pragma protect version="2.3"
`pragma protect author="default"
`pragma protect author_info="default"
`pragma protect encrypt_agent="GOWIN"
`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
`pragma protect key_block
XUxlt4kAZNWx+CZjpNFOxuyr5JO+J79HgKtXfRxwq3+j18TlfhUIlARkWKvjVVOxCF/MUt/NWoaJ
4ms5amTKHFuEObR0JwM3EOMte3cvLoPmahEU0sXSzQhKtOe+5EgFItJXy8m5ck6UFNwkGI7DU5av
EY+ZNc/foLf/qnSH7KqE13zSAMw6Yki5jMuAAExtuXbDsoISpuu8gvDgoaE6ZE4b+fCD/2gHIH8o
IlRz3L3ftcIfut5/DMSxtM/Io4DCvzqs/bAu1gvr/SdXbsdVpidDuEGk/Ds2uSIINeGEznqIPrjy
xzWh6Fb/1+hkQegvfmRYRxZbbW0acmF5V2ilMg==
`pragma protect encoding=(enctype="base64", line_length=76, bytes=22736)
`pragma protect data_keyowner="default-ip-vendor"
`pragma protect data_keyname="default-ip-key"
`pragma protect data_method="aes128-cfb"
`pragma protect data_block
IGlu8h0rQHXqAkMTX/S4FAy4d3Hh8d8mv+4a5mKfUxytokvuuzht/J9gqUS1v9921/CHwyLywyM/
qBRqlfUr7mkIBqqyqZah+pn9fUS0pZ69S9pATvfvQnN8ymlhG1GaqHAGDv+fl93HaGh70ClXRyEW
r5tKjApJxJzR5W8P0XyZTG/yzngLnGPI08F3wsvwJ41JxtLdp/n0IUDtJUYkc+oer0D2ieihPWPD
VAc4OyoVqMkayuCRaGPL8CT2sDT3ZVITm0Bc+G9DnAZ6w1qDrLn8i5Sk5YFzhq9Z9H+g1+7d5/Qq
wG7rZwWcqv0+JGpSQ5DgVpgVuvZEV4SprSk5kW0C/FEvPiW7gG+7xTLinpmbR/NzzxNsZdhDW9JS
MNL82u5zgxehfqA6c9ejFs+0drrugHpND2/D79mwuld2mdnlWrZn/OpZLZaaNLKhcql6UQbmPvIH
ipQx0CjTyEuVMG6P5Q0Uzn7JF/wQD+04MY9N6ihRZ+XVChIPUmJTdLEznM0ccya4ev+NYdp1S2fP
s47MXgXqK+v7uG2TXMw53y2z1y7ZPDKAXqCWZ9Qp1H9AhQTZETlcYM7m9gVvJi0hj0hUI7eZ+o2B
Y9Mqo8mGrVSw7z/F0Qj6qfL395JQyz4uZBRoRA1JwUN5Y5CPRy9oPoZ+Ivss4MI9+csVdlYHlGjH
ZRaZ0V39hyiayiLFxRbPW5nbS3SuNcpCIjrzrZxsOqWDRj9kYPh+G9jJhFMh1vKKyKB3o/G7x0g5
dlWhx9QiLt04FFQRnSyngh03ilxSzjdHD98FNC66Ai3jFfvL9SuihfeQzLjC4HEojN8zSQRGLAaG
VqM0ARdU8ViJiWAyxugkvew0kbg6pKKBFARP5smr/O/iJXjDfQCux7rZEapVe2E2I3IhYU80P6LQ
+Psr8Tn726ZF0gR/vQZmoJTk+Au8GhZ/JOUvyT0fm9YQQKy1+M/bDk2RQEmslYOlkGUB4muTdm04
aYa9k4n9vN2gushfHMwMIDLVDIT+auyf6R861p8q8VSQhZjBlUnAp42Rt1jOshwgcDp1swfeTNPs
mxBCJHNPAhGf299UXCSx3jfVGJA2/gUOMwzWYEwKAb7x+DVmMxgdO9q26urjtzWdh9p4sOET+l0B
/ziyqi1en4WBzfxDcLSczAbL7FLMqSIazDYsC4tECvsSsOhItol4iCST4dklSuV91liZdlB4oQYb
Nha95tE69Y/RMHZA3YnFFhStp6lU/M6+Iqu4Pb2+peqQ8QGq9c5c/4R/deARNninbzhAqhyaqDeI
TT3NYmy8JqfXBOAq7YlN9p+x6kKsiYUhZBqphzaGeLBsWrYeluC24CQLAWMJvYsQif1CtGgOUrBs
SJKxc6VF8gDUxZfAiNpaoDDhzHG6hnHvex/TRgZ919TWbBw7rNjN3FuOlHgayrIopNLsIjFGIxBN
ZcO+jgYmyzfgM8F976QievE/tM8F3XgmICytHQ036SCzGWFH9V/XgasHnW7vgut3AHYzp23Yybga
+XIXPSjswwxPO+YrOsa0v+tpN/WwRJ/MKRYBcYVz/Yksk4TVFZn/yLM2VsedCu0qRKqGnPBFwnM+
OpyBDcTKbfMjEmKSD3cjhNBASNkVkKHIgHJA2AtcaF0nBJw8RWuQsSzylYe6fRvbfwTBorgl9Dd7
v/GpjWEEFi+usXWjWXsgYimu178Ul6NLZ8n/OGfjm2juoIKfQK48S1qpMkxga7E7onuCaAtDzAZT
CqHJYRCTXiFxvd/VTfyPTUYoEMCcxGlf0JxkcVeBGqDSGgCLrQeA9V+bEBSAiLWqbCq1zSnK8xhe
WXecj5z8npboGsmyr/z4FJJilsXbBfiQslhikOZnLbTZOZVTg3RC1RyLDMUFMNqzf2f8IX4kDlME
E37Z+LcOagDEQufFt+KgFeGSLNfE21NFVUxjQk4mgQ5fZ9HPpPJOlOtRwZFbEY8LBEBAyUVuGwsE
LXtwH4Ekq6RijYBeAFmA24s7AFUuI2nG8in3mVSywPr9dxoFtj8TW14nRu8ih6Rj7i+azffIrGxV
ZYgbq7oT1wyf8xSLI1dzjdR6UMkOdO31q1mmHuKRJ2guf3aU/2WSH8WsBh2TrYKf89Sx6t/yxByC
P9r9k+lyC8C47ZKiUQY2maQOl3+kPxXWsKoOzxnqP3QpcdDtVL6qesNCoOvg/liQR5KRgPqD1X9i
A4oIYFkcsBh52/keIFJG+2Rf7w+AeOoLG9BKq3vUYwK4n8eq5lzIMPcvT9lciFaPbeqSo9/tsXRS
XYtXdbTzYuxZX3IUmUFSL02oYIGoTLYdvLBv5wJRo0c0OJXrLwBQQtSc2Kcw0TT1SjD106lrj0+G
mNUpTKytNHuD9Ql1aTEb0wu6lBtrnEREkPcB2mZyDNeVqWBDaoHmCS9PZ7tOxy8MqmERpQZDANhZ
9TDA4URAtJ3wlwI67HH9pbb+AH+oFQ4N3hjigqvIog7dZUIVxu0nMKKGq+QG54z6r7QadOXZTh3H
7EURTlyux1EmzJolLol/WcFQZdhK6o7MQ9AClWMuAZPjep73GhPIZjUQgg+ZLTR/gChiNOCwyIkU
HlABcIBaD1y1QsEq3Nl3xJkWr+B9PIoQQitVa0Zj/3cMvGdcRbNOSX0VgGLbSMuOtEPcQmJOUyE7
On1RqVNGQTj6Q4Vew9MpP5ivIB1sadvhyifWTCPjwVh8Lefcq7YQw/Cak5RbMTEzua76eMXg9u2W
VjTAV7sbGNhEH5tH6M3h5nOfIhxroou7jVMOHwXS2IYCFfBBF+7AAg/2UBl7M3KiW0OMx/qKJ+yS
Q7GbCXQxHKUEDk2HDpi3bKfhNW7dNk8dpjIWTzLhxcPEpKzus9t6hXFh4g0kCs7l+drM65xj5ocA
ORGgR7bB9rjxdOSP73PC/lyEGM5etLU6FanGQwiy4E5rmyoXQjKw2XFz0eL4TPgS9/4t/x2ZoNQ6
BFdSw3YCdqfvGgD+Wy9ll+s1JVgGGqsdMvqAJFPTQ6RH4QZMa6SxlE6YdXExmhhVMByblBhkedOw
JcWEPOFVoFbHygan1n2NVzQ4bAiTa5XZ04ZexUxTZoRB3L6VxOMWAy9eLp8yKXpfA0hrUNi81BIi
IPzTOVdFwqaWK2ZHUBzodOTg8hywDIEf/TWy5taf8aZlHuGkS8eVxTAg9lytzCOPVJq397S9HWjE
2cEf/daz7/nzsoegByGPx+fhUR2CraCI3/RJs6ap0msUVt06DAp3dnt7P9P/cPfxZT9w8izQBkuY
ejbFbY8Y5NvSEd37xJ11rkljrPrmm1qrnx3sQk52DXPEwn25I9vgYEODtYut0BQKtrHs8XbCBiTi
i99H/sZN/k47LdxjNQMz1Mrz/lVswGxLcXfMskP5C8XOHooCDmwq2z623sTKCQi0xJw/rEOzOf5B
/aQSLk27kjpeWb+lTmBG0BX4D6UWQ0S510J1UNMhVMih9SE7rC1JtVFVMTlP47Qjo2Bjb9EMyeOU
DqCT75T1gPfdDr3Y0bx3ou2L7w4GgHXwKPSJg3QmT7wkkdy+vsXV36lasxBxIpOA9cRZsrE5m3a2
bmbGJhBSzXKeGytiU9ebwsgZIHuwPZE+Oh7/tHWtaQOywmCKjb4tjbMJ+EA25y0FAb0Bk73bBkz/
mMZvQYR4WtL/Kv7KJJJeJyg0AIhO7eBcpjsLX85cr/advFwfTfMyGwnUefk+6GKF4eH6q7ClTNlX
aARZSr0yauAtAiCwwYbHWkAJonqClNAg+jOYe3jEI9BFfY3vOMLIfwZz/6MhY0zCz18K8SMcd/Gh
3YAbX70nb3LOSEFnpV8A/1LZfA3R7NwdbvFFBlN5SK5oSGXUsrH5Zu+sTVhxuflR9Gr93wTdzUt+
mZIzeZ6woTqEbG6Xrb92cwM7+y+CHsXsGiviTtEbwMFmEpxFoW3ZYi5XpEhnmpb6a5cKXR7pOMh1
fAzUQGCb2Fb5FAOZ8C35QXnUNuoVCae37At6JmbFihXLZp+nqTU/I21TlxYBvAnI55UvPs0Jk/dK
XSIoaMi2pDHTJ7JPO1A8+7uW+7Fq+5aES9iOL4igNCq7wvEkE2SqWSqmxUc4zjlvw3fu8uix89Kj
OjFgufcRz+32QrX9t1Ubgp2yQMiygIN2PhZpnITGJniHD7Y7w9hmzCm05xs8iXAVChPvMBX/eRve
EpRNT1XMFs4d8kESz1lqTzGdBufqaIuhY8Itn6nHfR94eEXyXS5B51gry1hO+ip8eMQZyu6IeYDB
CocJI6VSyx7Cew/lkqbIoZr9tukEGSaQ4SPAbEXKBxjEF2TY8HIEnE4IJ9uMUayybe2GSWLAUq6F
+Rc9UlgzvmdL73KDa8puxyPKWiWaxTuLcPiBbr7KWWftI85EOYM1VUT8/N6LsTGXRPDl+RcbAdSH
mNTirxPZPuE357R8UTTLHJS5/KluqBTC+GWLL1l8UvI4AAFSMu9Rp1UfvzcCi5zam9bHhNa7UKhd
cgWTLm8iG1kvUamdR7NRkqzmSdrurRiRKnDYVUBkKMtSep4u7NykTpbAgWYACrWDcCjlUUiipG66
PDuTgZOf3qjYykmOf5C3JGBpld4T1E7YznQfvdAeGXt3gIbP+eypgzJF36tTgVwy87LKjZyAbvFj
qQXLs3UeywnCJ0ViwOpLgTAMBTPhqnJxVKi4ZJ0/+JWOKxUmpVtzhTooLlu8CbU5i4tUGvKYQEDZ
zMNsiNpjok0tnVTHcxpi6tZ149m+G8h35NskY6OK7HuxvXbfUrBrLSPkVsEz7IuoNQCzcXf5wCLw
AbV02EifFtKS2KSxKGR5ljny2LuiLM/IIAzejx1ezttq1J0aqLP606EUHqp3qkcETAQjgRKRhmNs
yD+T7z7gNGgxBQe/eSN6I7nMzGap6AHXArScshJJJd5fa/U1lGcfz6NStIPp3kIbzv/XlAHDMsgC
ht3bQTdhHlkZUAUK3DXMH/jlMV2uBwvssku3kxfg1JlSaziShayc4rb50geLbPN02h3Ht1wWslmA
psiNTtmLKmS1g5oU32eAAcY+nybT1aq+ne9QI+sC6NG78EjbcDaE01mE4Aui7YzR1lf8OSUrn9in
BIx6gFCT3j9uw7JX8FWk/1q/klgFY5JTSVFkjuA96FBZg1RyCkeRXGaZ/F6jXFOfNUm7AkX+CLgw
eWCFgbb+Jo+GSVIbAkimbJczsB69HUnDI7w6dp2YidoINB35/OpKP+LDn1eD2Vy3TqKTBXlohqAW
2umXr81yB7zmsPDmr5d+g1INRwUi7AS4KLTUSw5xA9UhjJsonN6hErDqJPxMCtD5EcOzF8rdxzOa
J5fMoEw9yyLwmfI7avZbI6/94Whqowq0RYyCPQA0hd9QqrA9lbFYUspG+FeHIcwoGbddI3oOFhwe
3o27cyxdbUuXEXikjEK0U4DiM6epB6z4VZnOexgdpE6ZsjyW9dQL+xfqG/mAeDNooEbaZpLkc0Ek
2nPxvCg1Yo/LayYdlLMzzeL2DB0jpSnMp/jCjQJZSMMnAOA6xVwLHXIi4/ufs3RPR1csZVSqNz2f
AhKwtJdx04/lpIrWj2c5jwuzU3xsjfDabUxpGJVivOshWlM9NcAAykHQRezHWY1wCKyevaSYQnIt
xa3j09JABJrWTUWPI6gIlgvGDExveP4yll1NilLMJtmbxRkflhbWWCrdnccKJ93euLXuFfeU6O5C
PTwG+kL1MiXkfyfW5UHcqis4DZZk9Ro814BADR4VV5bgn/rHElJABND5zkxabE0ZSNbICnuUHOcC
o3cotNQT1mMt2FZ9qcJkarI3qFHFATa+knYltD0tQvcdJDKVkw3caDwn+MvbmVZU6Ift6xL1K62w
okGv5vU5cOlZIbKev+JZI4TLLVS2w121uP/0P7or7/39tgg/6zMTlIZ35/HqWwPC9ER4EdxktaHW
uxe6PotBgq3ARPpNMrx2Tw7/8QU82Q2UOEICFFtigeWCogF67Cz7Ra2ZCdT27P7VgMzmW9sw9wZ5
A1YzR0zmUGgHfrNF9L8xQa06Vle/YqIF3Fms5kux8EG5NLOX3tV4FNlgE3TewJcoRqhkYnRpkGdA
n4VHB/aN+OxqbM3RVb2yiyVR+Qf/sxpZ3fWXNVaqBMVLwwip2HejrfFEjCefc3FsUAVSOvXe9ZIl
rkKMbm0/PjETtVr/LHh5kbf2V59DXyDJoXzM7GPjG8gbcehPscPEbH2frHM5UrsMJlZHKaelUz52
TAuh6aj36WXvUJ7OKYJ+DKoe9OECPlQ9+kFkYU4CC/Eb1k4zs5I80t4UbwVp1CMvD+0ytprUY8b4
ZBTjsTOC8mfCYJftlLpS89w1DTm7k+oSGeJLQLnddmGEPjN9nhlmbWKiNXassAZwuBKMNm+EoUeZ
yodNASJ9x781YTngtr8IzF5gF6Am2oVUI5EiEX9vQkpUW3jGAxtgPAUcEDXNHrzOFevQ5JU+SCY0
x1ZUbWPBRFIydiiMzG+5gloh06JrWqy/72Y0swJdPcoQNwFkerlCqN7xha8ACgIJM22gmivD5MTo
1MumTLkkTZIRaZy8JV8UPta1uI64S0w+aJMjRnylInhYIbfbrcHqXlN4tnIvCrn1wJDQMgmiV6yw
cMbgGtxwklP9w0C4onyQLtfdam3oXwK7vaV5g6vxI84fw9IkYvzXWJbPuMt6wdKklK49fck/sUDP
YAk8eF2laJQ679oJa9dSLsSTGiAAHiarUEhvFKYvNjD3SMgMgz23gMvk6AbA34KPME5OKQQ59L29
er+132IoBFXOqRILtZ0UGvRtZr/gNL2f+2I6179pB2sI8qQUcNPc1/F2xMOHQ+cjeUvi/DEQEy7C
kynP2fls6Dv7rep9x09Maej/XMGjB9UT562h6GIZMh8U5rbT1W7IoVNkePRJx928H5idiL0B2OBR
rD+iWcssjGtV1gVXMgrt8Ky29sA6abJu7jOn3KTC5zQO7lW3N2wUIKK88iQcm2HlEQTh9SSllclo
/fK9WNFEvMokLIqX/ndB2ODaHihMojUaxkM5yUQ9j+CJHy57cQSpS3wycomMiwX8Huz0oaLwnTFC
GWEOK+EUnyeSqUjZzx6M29xuZaT2cRgMn2V/nnWqNati6+kCBu5XB1FtnDO7jo9vKIbnQ7onP3lp
cLVH9txOZcRfWDtV0IEvvSkTH4LgBv7NtX9jrUEzbSOYSgohH5n4rVuUtHVXldR0fMXKQxgkY9w3
4Hny0w8beS0I+AWqM9Pj6f24N7Rn00Msv0lJ6B1E9KWhNcrvJqz76I6r0qxSAtg3ZKkPHNULG3qw
Gf+Q/XM8O2ZmEGdpTdyMbCVURUFGIERxeE/mUDIWo9QNujzlmy2FACVY/weDWswQmY8Noweq5cXl
+45LiaC6gECswvJEOJc00+we8MQ1xfBo2akEf39N+AVGufiRiegGG0oGorjzetawZ0mvYusSHFBZ
QUeAYiznWva/7EhnTC3OESXkp+MFS+GqMjjaL+Z4rk+zzL02SYTeLkQrbZ+HHgN/1BIAyU91zrfw
60kya/DO2JdjtioGJS4hGP+KPQNixwi9GF4iX6DtPPtT6QXNplAjv31P227CW24u9yxUvdM8p/YA
A3zug3uORF3+C3TJibPk6bE3y/4gwBqLctoo7lU4IyCoLkav4TbSO+6XOfoILfQPBFIZneML8dGE
DuOvAf6GEO2/EZoqMi3mtLGIWg5XlVkjplL7vE7jnCwJSoXxB72lvx4Xco5u0f99yYkBOJrniEG6
4ANpaQELnAxe/0mwcKwrw2Z1TEzD0w9akvOWwDjhuxFxnTzVPjJ9y5BvFADt02nfoRUAKbDdCrpE
2pcTe7vAeT/3yZrMV1qi2pQI21gEsfinZcHgMWO6OrZ8ov50b/wRAzpmvg5OrMJsnQLTLUrUAedC
zxVkdXJ7ZR9zfsYpkxWHD8gQGy7Z9d0+GA4WR8xOkGGoZ5XN34Fc9NGm6AOB4by3QTyp7rBImlLp
F79d5b9h/nDY3f4jIASZIKvTRrHzRWZuqUgV4FQwWk9ywB1QWD2QVyaTXXRL+Kv2aluIH7URAfWD
AtAtK3lavtQHiJm30/RsI+IK2WTPA/Jy/2aGwoFyESonKHb48Gp+EJQdbPNp9ODMDBEpFVtyM5I8
2QZij3kkGgPQh+oAs+9HUivxxdRtiTZDFjUmBm9PACHhofQjOsqzBnoMJzK0qdZiy8zTpukkWA/L
1q2utJ6nS2L4SYS7FfAkhs4tvtVH4gJOGIk6BWAZ1wO+5rAn78iQyoo4GAGYP4A2pglofNsLZxG+
UxMVrLx22VoYx6EsArIBQRDaBgCeq5q+fE1yETFY6jxGXHSTwd9kyNBTOVFJipFrz0ciTl3mSNrh
2wEPld0JEHLyoNDT2oniU2c0X5nQ1jInmKHH0IWbIeJS5IaXqdu1P96x+JRf9ioZB/5IUoPGABRa
YOsDkdJsv2hMI4PaKyjnXSiBcO0oOTLxjMAgzcVK/HI7yYsD0rIvKCh83ceHR4gptlwfgOWQqyff
tkTpiABrNUChq2KxnJmxbZoohDxtxDxCSDHcxcJX/WNOuClSHxwn3ZrGPHa09CEOvTOCEZB4ay93
LyCBK/Vuo5TCUZF7i5BYtN/KoCcPH7HaK8Z5s2xQECP1w+lJ6r3NOB8nyW+jLPs7qvu3slDqPIKP
6H0eNdg12BHVX3nju3LatjMYEkapPuzvqcku6cEMrmpc4f3G7ZB1NCFxuytdPitTFsP62xRDHxBR
F8tM3imXBSPCXpnxyGv/FzZSo1L52XCKHqc8rOnM0bnfHYvuEvPsdqGXb1ooICDz9lyVtCuhSvhA
H3euDbsPwFH+ckgJ41bP7rXr2ZHDWayEqff8iFUZxQtlr9a4zz47pRfTJvPcs+KOihIkvDGmnIS4
ufqA+y88vX2fLLx/7FjwXzJGQ06qzkHeLTiBqVnC9VLkqI4B+QPvPztRzYGCZvpXkgGJEUfEfCOD
ka4cdTYOTAmE4ukwJ3lcpU7htTLVfn86LPnVBBZRhqn1Loen7QhODCYqtzEk5x4eWsFiDUCvdg0+
XvUhT+dyBHvL8uWwxc7tV46373Hy/3sytTtBtfoXLiBY5kPD7mCzO2OCeqnA8Coh42tDmIIrwDIt
jbu9IF95qtTXQ4WtcdpKaZpeEn2HTKQUXKRc51PHmVo9MD9YcZxJSp8kH/i7owWgZZEnm/cgaBqH
/Br9LQLPBejVRYcp0Bg/HswrXVryt6cpxTg0OeX0YWZBX7S98TQs4rQ9G1ZbLXe+YrIq63NY6bCc
h9XSBz/tJgmIbJJa+vpD1VIZIukycUPBLTX39cES/isEFqB/ymwYo+5tU9vEKOd+gnSJXl8N3qx8
Uw0vyD90B3eFZoNSepOQNgOGYKZyRx54HpMUIxcaR38srrUUZRndA/63RNYTg0JzXJJthr1nnvuN
e4UGycAfj4+ANfCTYb6JxDPfwXsh6JkbTYnLcbpa5kzxnpkfI6xp9oNts1ZBw0ZTBWMrWNGZGTb1
3cZyzXhyAKfemDUVVeL3WfiFwHmy/d2xdczZZ4Mtfn4BpOkREC9tflIrnqZZyBvYPVrzCiFwOxjG
JqhPJ23bgCp6bZNX3PJrneHmuCn21hxKB3JcCUu24PMDDFW0hn5N4Mbh47wbgs+CYiPhUqf+jvmQ
dgWnxwkGaokZuVmmJ3zLbOCeIoSq/BAdn/S5jiOidJGUWsKphPesBa5OyxxsD5jk1DD0BtjErZSw
TLLl7P1+FNwVF+GWJqrB8gzlXPi1mXMbX/mnYBBMfvLbgKDpqgXw3HjW0j691x52ibYzeTfcVOWj
0PbP4Wh2VY9BbhamBhoic9bxRsx//dL2sym3v93whU0LNBUJDQb3F704Swlm3GxErczDLmHwCrea
zs+8Krfy4PAVZsYWyjoow8AqkqWIuuwSQk30tgRE2MrWsQje/wjJ20hF+szO8VRwoprNvpCBe5QZ
JHsgb1J5TYuuyQpGKZXV2p4DWSGiimTNshfBJR7w6gjwZD7IWrMfh6VBdZ20uo7RKIouXwUcVbYJ
bTAAmt+gyI0eMfcydwM3dFglQf9CmyKmnm9aSVzHqc8G7RAkx5c2e3HZ6Ke+NYsTUT4k1Usceods
mH5BSGb2NM0jJQmeXQ1g0GuK4+7A4eMZD5VW7btdx2HdPk7lvhuOErWLV/8nWwGdoGMKK7qT0Lrm
LeqPzmUo3iP8LK96UnmzD5rLY8GpxTSIOj6/C6POn9KFyvrCHnWnvIPwE986AnYNrZqz2F5/LO/P
IuttouM5OfwpDgMstlYYrSdVvYcvCEMYbxsA3ExXC3GvC5PDseOj3EbfeSCsvzPnT52vFm0vCN58
NxnwaUG806obeBC8Ss9Yj46a7IIS0eCwxonLQbytRTamXICGOT0NsfL2wCsIwx+HBKjooAsgpC3A
B8vw8PicT7SYwaxWF8yuXug3A6vF9u9oUukqOieK+gDdjFHnn4OndyJwPAZHIAgUxlxC3AxeeMFp
T0nsa1hTAGUdI/MNXYSWN0x21e4CEiYx26XJPmuZ2avf00NvFTxR3kqCH8EQNrXjRdFneTa/VnXc
awWeZdbSswPsWM8d45/hLRFfEbfTI0FKPTFyHWzZLAq4TAZE73U1p4zFYTi3Q5jOkGvv9Bi/COQz
GkG5krDuYltCLFj7JPgntfvNUUQaguhZfYjQhUv0XYIAxRDSUlVGdyegx2pbETFU+rLeLJBVUPpN
CfOojRjiGKWWtrcoyZgEygq7vH1KbE2gbV6h9Aht+86+C5muuQaqIvaLqQYs/TLXVi8fKLLyeStG
myEk3RTI4aV/jO4w2ZSClLU/usFoyDoAByguPw5vhMiZ6ISyTpIaJSfCwryK2da22Qccu5WpNgis
3y+76LfQXFnGGD9Vd3oGDnL+DBqAogBs9dbpdmLw2Xm70zpHwzdBCk47DFJSzcZFWgGSjcqdSbZX
kVFOnzs5E5LLhtclAdspgemCvgz0z8U5vXo1qWnFE7n20tNx1wAUeleleO+OmLFTgnli3rI5K+Je
dXMYqEwobzYrBO4Op0R9tXjx6oj2rkEUl0IzELaIY5KvdlIMsbYugOVbZuero0ZJr+NE25pXCAIk
dlwUUy2uOlaKFWQ0YAihDYAuirMkzABnCW+hSSoJ3RHcLqrLlWYpURJMXjloWaHOlCmt3oUYjXaj
nZnhn7uT86I8vIXGlocDBlLcPpLkFUc/JVKVLeb6HjGvK2VGlLl5JkaYOtWJhMbbUZPQ1EObyo1G
1iP/B0Gn637/ncK8pjjPqNFpgTKiBdCj54BV+XNEZiAnMSHRnv1ktfAQO65nUGwd2AOsAFAxcVEQ
fO7l7WKjkfxxrPmmt2RtYY9gAo5xZeHJor0/5uPP01Qbx6pKxZM7msodNTWDMvCajfzMXCs/HWBW
C3heZP/C+P5EUVWFGkfcjVLQ2t4GD98hEGQ/qbnxYBLY9yFA+rWSHClP4ngl8EbSj+lZWS3VKRRC
/CaHhYcH2YIGTmumzo1NhajuNMMIYHNdLxZNM+WFpZGso//+aLXb4yH3C3lwR8cBquVSlkVNmsr8
9+uN2kRbCMoW4dfZHXnGZB1/1uTgvIOMHsOk0HU1Kyv8p7UaCpqhiFYf+BLd9blPHbVom+0KAOpY
Qrp0d9CDJ1DSKOcKEfBUnI05TiM82BQczwhQ+ZhcDNnxLQjwYlj98uGIwB7CKrZZrMCIUICo4EwV
h5kfNIs2btiSPRiNBhoQ0HJnFQ+Z9yR2ZsEgZ7RZu0/Wkeyr9iqTDHJWW/L0kJ9KSAyXX+QPQ5/U
OOGdOHtfJaQfWYvPXnInkek9iNDcWtghX69+3iPOfk4dFdZQ5Sj+YgboLKkBniaeF/X2FmqS8STU
4HNIH7pMV6G1Q9QtGEaOeNbLgrNesvWXChZ2mxqA4/ct02CPyUcEpLZXtc9WDeTT55N32XLm0PsZ
8rzC6xfXT/uybncAtgztBy86ZjcMPeGx306qUcPd+v16tmI55JIPQkvEZTPjrT1JVvEFT0jgw2Zc
k+jCStAhJQZC8ElFCVQn0TxwoWFLkYHKyXtCdH7pDKO7iCaDBneHzqYbCWkKt8dayJM2ZLyooV7a
8eOOESgkIMNxqTEbRkIM0EpSk2xK7HCsRsKswD5KhMxipFTVelA0tDmBRAvWDXAzUPwoIZBDStcU
BhnGG1BEKr+g5HkWuuYZENvCNeGOUCdqkEIm19tKWPfLfQ/PXA1kglBopotpHott1ZmN174UlRVw
H2j+TuthkwHjG/7qTKdDIs+S2kKqH6+SbHk9+LECvu5Kmyd/kZ1i7yHv3CIQA8LMnU3UQeMnZPdj
EKklmNhcU8HH+yCEvucYe0mtt1udqEgdKWWECpuTg37aDp9ZQEagJEQCgZBLICViLMAyEVQJelk9
5iclSnzh1BZHncPMLkJQR04CQ4XNMABQRjziK+BbWmvJBZLbNtEQ9t3x0odBsLfgi3HxUupSesVP
3RuE+MJUyX7ZYDxpQCLymo4wdFwa68A30HPNBWNw0kMiGrJUFO6lLyTinv0Y4e6FbEOpZe+peC13
ZWb5SK6f0VgoPey9THf8+4uB7gJ9UWIT71Moq3Q3I5pyUfJF1Kg1JfiGE/4yFhmbsygK7tGX8wr8
h/ZJ/d3GamzZ4nPTKXKoI/mllhL6iPs1n/YUOvRKxLeGXVPe27zHi0wZFfRSwrylVGNhYfGQURK+
FKGgY9SZJLZfm2HjRQqC8VjcGUq2tGHs5gDKG3gMEItj1WUUR/p+ZEZ43i+PHv6iLdAhZJDW8d5n
9FyBdDHnQlZz7kysqNuaEZ2OCDhEMvMQ/BLuJYT0EzF1f7YSKGpG/4sDutdavm2JUVHCVeBx9/OH
l1V6sWpw5g6y+qOI0UI7QIGj0PS0TbE+4mzeGQBft6FHEC5RfbGegTcKXGr9F75V//O6Fu1kb4ZO
A54ydHSA/PA0TM5Tnxar+yDh7Y1PYr5DsAleQUuqfDLUC5Zm/agBN7hNIC4bv237tjyCOZtfx9DQ
lixkqh6y5k4qnBnIKvniz4X4iIkMo+UECTlhFbKVfH3vxU/GHwutXZenQYI2ENF4jlB9vZozCYKE
fRRkdM+0L4EeA4XcN3q/bbjCHjh5CxxDp6g1CePld9wEZ8yd9swp2HMNZmi7mn2NEFlkJzBU6n+6
ZflAE0remVIb7rn9TmTbwI4ddwqlhhOGTPzJu3p9yhHedJNwTkRb4mIXdXb3EhNhYCobSn58Btz5
eRCGSQKwFc5uK2phOpSfQEBvUeOss5NRulHij7n+ajdlB18DTPPTGqM5UwQUHAOBFB+li5j0Qwkq
CB8/bsu1Xczj0GINMHUzLt6iQJAz1IEmhEIKCUc3fNijknPv0FgdphHBrXPOszP/KTupvXgKTCMQ
1dEDtBsekq85yXPy7ta2WLYFfR1w1J7OfWEhe+4Fv3Ki2exNJQMaf0DEHs2Jku1C5EtoHnLzMH+P
6PsWPj5zYZoz/6igaEVOZmrAGq5ZUiSy+vj48vyeVLDDaX1aaaoMSzIl4MnflJ/73sblHmcNUnIW
hs/1NZpltFbTKkW2pdoQzZnNQi/UZRmzUcoI/zPZZ41NMPo0qO1LyL9rp2GVqyMg/cow17m5q3te
XWxLSd9wDZQJEn2wbRiN38GLJ+J9UXwDR2D5hZOJaur72n1zW7PLgSETFDyP4j8EaNSECIMTTA6C
ja3vqTw7k9RT9JerVLIeXMGu5C1xd4FQ7UUOexrIo5A42UzAILWTR/bHn4sfva7seYGL8Nxn2HJt
c5tSTt3CaSkYRKbvbY9e1TViFnvP2SsxBwfow9MhPQyVXcOZE/hFMCB7wYKDPESfTHmLwK2g5yhU
UJW7DqrJG6SrcdALtW7JvXhS8Qai/Kqf5MdIjiaM/M0sdRlhvXdR4dcrGv1RAjzYelg8b7Nw6sn8
I8R024M3uVNTgGYcuUIHjoYR6TBFIs8ZmKBhyswTMNyxAjJSFLvX5TSLtWD4BiLMVclh5AWr/i/i
JWgPPwUucLUkuB1yACwpQZF0ScKqLKyJ+5ASRPBi2bR3Kz1v3JJadS1DTyHcuKkt2z9nNghznVWZ
A8f2nEkQZJ5hhIgQHzy6GPmULYNwS05C7W5iW88cmmHzUOImkEF3y1vglSH+x6N4cQlju+Q52fgg
8fAgIVuergl+DnfpX6dmMAoIbQ97s38T7E/5kWj5Afu3b8UM6ADgAnYaLzcOzLfC4GrU1Pp2iMiW
WhAeSiSWnCr4SpBB4TeMeRTNWlmNLVGmwJQK/H+fsnBW2RYybQEvwZHyCmd9twnFa9XpVT7vx9vW
ideMLSZSXpa0kfknRgxUpV7k3u6IN6zmL5EMMENhFXOCa0OzTvRteZZLIpG8Ro42EfibPP1xV/+E
WRKL5i3cEXkqsXmQSxRLxvzOnNphQeHJ5ncLWzdaldEFqv1TzeOd3FLf6gNyxz8bNtA76LrlEk8S
Sg6UVKzxBD7FZ10Xq+UH1zze06ryKCladPWTkvhFm317omd3WaWe2qqzcMjLuLUKg6VDLofqLYg6
p8bvf0LqO4rZg9SIp2QPj+eztTimJCGTLF+dHvGyju0qoqbd7234SqnXcWddhxBIVB7jfxYMA1dZ
F0AOAb8pYfe9T5Yx2u7TxE5fSpYLCb7bNJOXsWm0AwXZvU3Av0Exg29IZp2b1+rUEdRq+by6XA7d
TfsH4cf+4NTE1swkMYz0JlVko94o7zm9g+qdm94L1ld23ccoosJiqczwAyFtd0t8p+ssp9aTMAzO
NaipInEhJTb9paWINVWA8GG12kmcl3H19PUMhXz5UHNggQNBQV9bXh+BfgXKD0X3M7XMXCRdoi4Y
0Y58G2B5oCqyXC+VSH0/RwWqMx+ilbJsU1V4L0NXFRkalhZpqZcWvTY7Lg/hDOdZ066PIB32vhqu
TfVbJF1pWuuTkjZtYVBBXG1LNiKTo1TfLgmzIT6iEdKXEdnWyOeUW0jK/Ikd8y6IYq88L8Y4oFgh
54ey67mDkMH+40Q5JHEm6sRCCrd5dzSi+g6AiL0mrwunx8QNPvmKLVbFbT6DJmFJgubAGF0bmq9v
VuTdUgxqZLasLLFr1Iy+AD6SoZWJPO8rH/dwe2HkueaRIA+BXGbI57wBHWp11UfSc+zRp84BlgQ2
vfXRcR8EdDcmlsoJh8YNt90w63RxbyrwJ2kXYgVMeu2mEMpe5fLvo7VDNaROOGs6QtKcCbuKONtZ
6YPnFxZaSdpVJ5+uBDIS8lOs5gKQQK/qQcAinJ07+WAKELzv9GN0ICJ5M7h2FC76fOORfVC3cz4p
ZpliAMfeBGjowrdVqLTprSN/v7RgBiPQeq8oMG6O7+WxOOj9h9hh5c9B06uDWsXlorQAEJ71mY/F
MYe5X71aDPqFmx9e0zooWdj6Xr06Q3tI8QhPB4QrOyjQhtfgi8Et8AoazQx0mzQnrv7Aomyo0dJ4
QyLy73TRAnBlERsR6IZjzFCBYpRKQZztAQtALvwmvV4IjtyqNyGDh4t+uR7In8kFS8H1HNhEZ016
rvs5E6RTiDAXEzW9EF3uYJs47cVs6H0cq8CbaD2lvAPmfwmpYTS6frK5RYZ/FuxZ98IXAkab3ppU
Wxs1h5Ddd0PmyFKON4b6qH3VUrBhFKhRXJtvN9k8ewDuDJkhR1TDpIUf9RAZn44w1yib+w5D7cnA
pzsttsyEVX2vCIqwGxoXjak5vZm16HK1vQbrnK2dd+mglncIgVnK+xtQVehlvckC0fBDswdnYto1
Z33zC0Q9nY73/dTvBjFTG4BkYqqkUQsv0aAhtEBvgFKFK4sqkbCxhK2NLa4qW7TJLqax+bPNw4L/
UO+4Yk05gWJm5uXXbVdUsAOaLISRtc0DD/lBaS09scjp+aTryJht0OINSlV5fWJ9kHdA+XECMPKV
E6dCDP0dBwWv2IlKPn4gFDsPoLncobFclXRsoG3NzuaCs7rPAEKaABzs8rx5037Y/2x9/PkRfF3/
pGaIa+hWxbooLMy5T2/PO9a5xAzuseS/5iU6QFD/5RBZgCIVhdk2CF1KsUCV2P5XwWAqLpln/JmW
IiqJY0HvQGXA4L7pq51qfFMRWzKpLYk7WoylLihPwe2tD2zIKoMr1bm0ckiQ/96NGstQOV6/ktZw
MHzxnPboLMbFQzh6Fhju4GfD4CWZXdu0UJt/2HURH8h2tyFuA1A1A5QgxrtAL98vBH4cMpUSIAWi
yU3yrewpey40WtcU7Wnp4DImJie3l9ZLSBoE2yFkUpa7sKCY0vF+8RN4nA8+he6/5ewo7P8QoIar
hx+W0b07/sKRyih7l4vc/dHgaR/cC35n9O8OrATEl+fGCXWWu/xogf4HduUhJ+VGv/5WtXH0XP8n
tmf2iumNYn1yzYZl1/8ycFITvIXuG9NSuMshycpQwhIzJPQsXNnB/8CvT1Vq0k+bJwOCTtjXuQxi
tOZKTGhkGK4OPc/BZCeH7F1LNmXL/iYhPpx6AOYbpgmW1nXhj2CM2zZfj8cCWDp1xJSlvdC86ORS
93uyMZ+dlrZwZURWsVCHTIF1XG1O144WjJ33koW6Qe6Vj2aNL8JwioLHIFHBsoeearbdVZoPknOf
HnDBOvfweNt2fXq/vbCsIwfzMiB7Qt0KQS0v9dwz6QmFsXm3c1cfwMxT/2xwX3ApjLPao5Rf02AX
7DYt6V6D6AfQ0Hj7NgfTaNtbKcgos+KNJzBzyCsQYLc9C4udowwGly7Pv8UFQO+3/FhI/hKOiEPa
lWuowtCySx6mfZduBZIIlU9zjMVD4QzEJNJpdJ5/UMd8OW2jfUNlmFrkCZbCFg7JFDhg8x9eqUZv
Pb1vNyVrHkQC3hZmlLTa1qRvVhE9DL/FeT8gGEja/WRtSKBxgWn2Lli1fMRbw1aA7NU1Y4vf7y5H
1jsZvYJzWMQsRnk8oX+6AyEC3RhljJaEYq/qoGf5ZbuoKW4R9O1GuRQViY/tJbSoRzvuGVKcEy36
vLamHB8vNn7uclbGp6jfLNTWOWRrYF6EJnl1QXCH55+U3BwjgkrZ/Gvntu4Bs2TyJShzLyTQWrv6
+AyjEeD5N4desGvcV4MJTapJ3zvGBbccxor8HM3XKjonbwAl9a2DZnv6Q3iP7z0OPU0Xmyw6ySzv
Z/WUrpXE5O79PxAOGZiTYni+YPNzuu0Oam9mdd6tE0r+xRRJAIyzKkmbw+bnMnnli9LhZE2MU1P4
eP0RaUlua760P7a49dhSkSENWoNW6mYtyIa0Em6wj5J4EznjCbuIs2NY2UMZPrl3sYs64bHJxZng
FwpUwcmmj+rwvLeKuh7nFYQqPWgj2uLiGM2k+OV4sswYV3XntuJwsJDE5wtmgGennr0D3oSLl/mx
kGnJvCPs9XtrcYtDezDwb0dbHXOqvToMUbcVV8xQpERHCCkkrjnvnFnJ4UrfIjN+4fCZstf8KnLD
xTHVzUqR8Npu9/n697L796UMady1Ow7vIiSmVfakCvJU+zPlgRFMi512S+p0EX7i55iC1hInuCVA
y4XCgCPFcrF0Gpgfbf7I2eqbzBkfX95jHd0Um5TpMsLaQPTle1ZC8ljRwzNOVbax67pD+XUODaQP
GD7go1CYx5UNKQoxUFsMRwfo9bTr8kLttrCRY7AcJqgq9gnVFTMLrHwAjss0DJqN7jdA4p2/1tQO
ja/AGpOXuTYhlOSV+9DtwTzlHR7n0Ss1iKFGs5G2flim5bc6by7yP4uc6aoA3WNshEOr5M1QogEw
iOMVVsWNeLWbC+Bww4C1GAxw2CWpyliNnnYwVsOIPHLg1p9FHQ/nd3PCWC9YfrygHYZZR1o85bts
Kv195z8c9Y5zY6k0tjvY6sduCewfH+KTUhpXT2Y8bvADBTaraMIIuTmUfIhP7KhwNwSSYJSanl1l
BQVQ6yc/EUz3xTCDyYpU3kkJQ5V+y/n52Q7oNa5GNZqWefacFo60Iu3MCEqZlo2YnAjxNbzqmeB3
rx7gBRVR4dCo7Z85umg3xNk9ueV/UY9X4gYtnmqQSQw+sT+X45AyXPO+c61TH+G1iQMUubHxCCx0
TPjwI4IZ0jFVbKVv23h7Y5Y/b/dU51IMbQx/zandVBx4+cRqAcu6hTa35P29Y53wLD1fTE1hDjMf
yXS6qAzMk3j7l/YLKSyOxRd66bXX+Wn4Ph0hHrNBFhytc2QUc1nSwVcvKkqpAtZSZ7dgtwsx9Fqh
77eLa8NjmD+/CAGUqSv1QzSCeBB47VH9BxJFfSDgrxUIA4K8OXEo4E6w9VJifHZBDy+zXR6MR8o4
acY19D+l0RvAHTcNRD+YoupiArfgKwulIx8aIMREDRSfojeSExPCsFT4iaTCy95g5oee+NPCVfEE
478w7SroC7C0pUpf8Jhqg3sujDd6hw4hWTCWsJi1fFsry+9IlIBDXeEcCQLuj2YEGOQ29T2N2dRo
J6XEYzqbfMkAK4A0zP1SRBHXW5FY79I6iFV4FgCQkD6WHDW5HG0OdLhc+5A2Bd591valE9UjeyU5
ZA3q78Bc3syG+zlbgTZ2m2ymtkOb4lcibF+SnjUnlGioSRytErbFz6EqJGLqfxUiuQUBCkhsWpa2
bXyzpFzsmLJF6Qhf5lYCDW4wRyiY8kL90A6JVgs73GZtN0WULyHU+KZBLEYtddZAhJLccdod5wg8
OBVTFgFKvcC9zUSZw4vULWf3m4gblI8kkuLffSGr9XSl//G6foAb3JRv5m+aH/IcxdNW5wYEFsOp
FYu+VRDD1jhHH0mzJ1j6HzonjIYYf/1ZIO37vlNpz0CyWNA4FAr9B0q7bOeDgz6FJZg7FPTDrWjM
2EtrgAefYKbNnZvGbtt0Pvp+UaIfbO8ObP3fMGMO51rkTr7XRaEjYc8ZbaEVzbV3S5AD5kShQaHq
q+6EHW/1dsDiJ9PIDchXuH2cfE96LgsNENXzOU+AxpbHCkFc2TZWCDAiVlnfTe0O4DUKMcdmHzV7
HfdP/UWC36WVCfE2/DZkJzbAP3FNIfJUzfEJv0ISlWr1IzUwNB3R9pVvwK48pMKAmRC3OPINvTXU
YG03CcYxGQOfHUON3nwk2KMEUJJnAuF+xzck3GnVM3CiKVtZvPIxmG/yUyBw1AGCli7lX7DMgdbj
F6TEMR3yyiL9C3J2AGZT404vpPNozCl8pMVDWownLm3F3+ZCEDSjub2+am1ecMLoUToRrqwNagHt
uCf9Lw4ZDqTyrGr2UdY/e0t0FOIOiafaqujKHERuL+mA02dh3wHjYpTSG6Y9Vg+n+G+gRpbVs21A
L59gheCS1GFgXyGAeIzcTlvjT/4BKKqWZSzk6nGiOPln/yT6MEoid5QTQwiIfuF5OC+duRnwRZcb
nhyjxXhloFGk/ZTMtALwj1W3smM6lZ8TGFWGw11mp3EOEqiugSjz21dL8xfLQcsf84lwsX04ZgeU
HREInOx2um01RkvUJPHoD1usfUj0jzCoaEDtRm/XOfIRmSIlvptpa2hkHu+OD842QM6gFkO0w2wl
gNu8wybQ+XIBB22gMIYN0bVJqCDC7bFrvW3x4eRWdw4jm+qX+WhVGKsJwO5Zz4kDQZs/DmP5ZlPU
IABkMRlCgrFdlQyxZ4YybZJ+OE9A/ad0GzJWrZlK0S7NEdoxeNJUVf1szRsi2qFKYqRjoFDzmndd
1a0wLdXUrD1VVb9w9CLEGIrIBP2njzAAvjIjTPJSvpRBOugukupqqQrG0/9BSFciMCnH70qWW1Sd
9O9hoMn4yj1+FAzuM/ecU+TEd1aXHYftkbcWI7KPo872+OsVL6RtsoeVs6A7k/PqjQfjierNPmbv
CUOoj1WNk5NZ+1giztUe0Yi9mSUxpigjLYm8DOl41d0pwt1OA5B+EZ1yTxSustF5qFiUjmf/ZX4b
LLAOEI1jeHP+53XrT2a3fTDlLmRDTbh7DuZ0IblQ7sdqqWzk0KOdGoPmXxl3Ne7i0TUqVclh7p+7
z/5Cxu9V1p6FGelP7M+9fVBoERoj/XjNLCicZY7i6oCeLQVMLKo6HJ+rcN7uceu68Tk9HKJ6/nQx
SYgIuBIDFWcS7+vM9nmqby9Q6Ix6CI0XerORDN3SuCjfyJSW/sntYygHaOVEgQblhXDX7iKfAXXe
S6O3wXHR1vDt/pzgk2F0H+Komy6GYG9Fcp8AAkPjDvsaSDA3U4h6DQ4NWcywvl9gH5hZLirM7DbC
zwL8pt4O16mvnORNkIpt+PbwLhaNVnV+3sDqfAW19KiPoh0PgHMiNrT/JlkYwq/iyok1gYs5pNM2
Mpf+xLzwXlh3NKvDqStc8rr9Lp8gf+NhE0eJYLrhibLcKzXF6OpGenMGdpMrd3/aVp/Z1gM7KdPn
PEEX5SrmWx97qhOFs+UlKEzDbZL8/Eu2ZkKzsMW9L5Mv4OAjcEvHv+GFbAB/S6qN3W2i4n4Oya10
EAJRfqhB+ksqJqVOhSgN7V/q5jNGT2xFdvPnhnxHahHEM2zwQlKOWcumvcNwL1WZg4/EneKdiboQ
37hoYqmx24E4v+yrmJCEcCgnnphCgidBCyfk5DBx01jtUJwp5t25JoUFh+r3hajpdvWLd5tSlsWA
P/j9AXenECrurt+4fb2V09v5jrSQEmt2O0InMaV4tFdLZYpJG/qIjQ71s4OMutkg6btgJWLnBug/
KCKvCHzxe3DvUapLkdgU3yUyKyg5PRGFixz6nGgkkUOQInaiR3xcZi58/Yc1SrjDbXmYW0BsB9cK
NblKw7pwzAM3M3tUbK3DziDe+06KzXjxID9pVgHZbK+UtcBjjX0hXqf5bcBIbqGbbRhaSCCrhMTw
3BJ8l8TmzP3YnD1Cl6a1w8qL7dXesnU02HAKNXgJw/ktp6MY5G4HJi49ycIpGTbkobXXGUD0Zquo
4gNXeftA9bkL/XkM3cY/N2kDOdPzL8etSpfJYo5d9ANkGBQgRsMSRRhQ2wgfjrDhfyS3KQtmuipP
MkVy0J1MFAH5SC35+4r9SfAMjO62l7qhS2ZGfbvFK7ssVjfPTFhKdmnTd5uQK/61YhCvfB+/rCFa
/Yb50kz89JYgQ2HOWNuEFD+lFqddCkSfQd2+HoTmQLNY2sKeNFUnnEeANnd2I5bhxrYoV+Glo3Bp
KWLtgDGN9VP6Cmd/iwWuLIIALilrD0/eXSuYxFvGRG4Pc8JbxSzbwKJenIQysZX6B+cGOx8LVUVp
3fjPEfuJxMPw2X3oj2jk2p3ncGpSad2M91qGyYXtD0qgESUEKb7URUtPkZjze6rcm5QQiMg8h1GZ
KkUs3xTlTmtyF1W42KONm4W5CWD0xbeEDoow36GmaELA43yCgE3KpwI/J8EsYaWbm32jkV8jyrLh
NtiN0+1aQ7Vvk/sMH9yR3su/obRZZJ/dWvs7IRG+Fkfwh4+QPN7O1RjKmsjq6nMNBu6OcKCXeLEA
/Sh4jbaVQRoOA9jd0JB1yU+aMtxFZ1E15ZVP+PHV2WSdfXZgXQpBj1Ahg1ONs3TPfEseew1YGJrU
A6AGPTUTVafxbAt0Ghr2ECCf6MRbAm3y2APnNIRN9xZ+Mg4t1iP3hbnKUoVPfk7GmUvUODMsm1Qk
Xk2p95Yb9I7l4MyBSN+yl541HvZhFzYI1yHyBI64joMuaVH6JPjFcboj9BVNlJWWTmGBbMYItGMH
PO468CTlLLO0zS5a7DZeeSlsqjwu5e69CdNBS+lrVfXeFfbpqeiLbl18qhIQJbuyk9U8p6sboBrm
JR88vWqCQfaqu+ED5jJHja2SxC5DXtBuaTSWtYs7RITn0R5qdgKRNlF1VSdZlwvhMrCeDVCWAJU1
srI/pA4qkT/mtXENRmbYv4IGO5KoOP9XK/9ZF2MGffRFpo0Jf3tmcYiGLHks6uVYjTHfRlnrdMP2
K00lxmhHmfOV2Li7F4WlIkm98D0Vy6l0BQZdV3Tn35SnAX7WH1+lOPOBRU8aa1m+k+WROpZdMYyV
F+/3Cy+ZJQjvwU9+Llg8KoZMkdLe6C6ePOhZOddMUpoLY8yjmYkTqX+KLZvy6pmu3x2Wfea3ZgfA
++MQ+B1f/yyeOI1JzVN7yiHVzX8Aq0uXew7VIdjt/JCgoyr0IjuVqLVcMiJxePuPiTV5VAYEDaBN
TnMmFwFZk5ljTktS1NtuaaufvY1qBTaKH8iuPphAQ4mov8nqu8v0aWXX7WkfZOnXMeZGoaEljTG6
7oGliVzTi2K3WyhoMkad51mmYZJxRg/62BdGopicdZUU4NPc0/zU+eCBj4e0HdYH6G0fmL60cSUF
haXv6+y4l4HXFtLL4xjqJlzSsVc+G5ZwJ2nBnmqbO8sQBYciVePgHhXJ6FgB1scCNAUqb6FTVxd+
4/kjN0Atobq7r3nwL/VBoXFjZYvzcpZ3jLJbi8XPTSicju6vaIZCnfSATCYyuqIu1mIUlxrKn5Ya
30mhvwQgMVo4EOdNjwo7d9+mXqdAZlSh9dVU++U4nPXx3uifjd1A+O9gzre8HJIqL6c4LjYD+AAo
x1fDkoSZ4LDsnrw5lIUb2flCgfjBgLMVwuwzrhyHX3VanUJcZf9b+pdg8NiRsL4e9qDE8CEVsnlk
9AWFms2o27/hk++KW4SuU0GabMozUMHDivqHo3MQVByN6ubhiuEGg1VtQsMvAJcBkcApxlUHBid9
X+YllehffDpWbT8MzYV+KmyTVYuMsZIbn8z1wQORAutomA94r8WCGAtORg6g7hltPbxj7PwHwldi
+p5CbswEAMuWEZupofdJYo86uWYqQzzaBqKpW/xwjfLMO9Jpf7PVArG79I8pdDs9tCx25Edfh3dI
9Yu3xxXOI8iJKmaBmxqYiJLPp9zlcESVdXVFTjk8yRiDlObvee4HChi+P/QEjfuBICpbFuAF4tzE
k7X7XBJaRi3OKM45gVvaUd1zd4Y0rE40EK74QUFCNIiW+XUoO3tX50NkOyKamAAqc7ezgJUJh+gg
AU0hzRiHXph5l4aqf9hgvPAJcE9XV3E2U/VhryeQyhQjhcES1pXNlq2MRKVCcOak7yWG3djJwPl1
NOHORWyLANDLcHCOQG29DGk0Jy1YC9WPQJTw1ZqR5ckKlX5HAgUF7tMiyNrPu0Nm41NxTGx/dvoL
kChWvRdyQLmA+mgi4qvdNByUVPxLRJ6kCqQ3AuVHi94rRxUoXSpLIq1aE7VuEoyqKvtwXxHEXg3k
8FnxpF2teR9hI+CbxLfGdczhIbCE+HF/CP0avzQc5vomnmcsxs0iOhVm8FMy1OZcpZiEl8YY20lG
8watvhizWBon7crUDEUlveBAi0mLxpu+loi0H9uYHI8ARitS7CZLiQQdn2ZC2gDspOTuLue+fM7P
4uEl/3x8uMD7k8L+RtSjttpmwxo43Ue54tPKyMz3fSKVpo8dIJwr1XurivJo3eCura0fwlQGv9wq
BzGvc18b87FtEtTtv3LEIeVBLPP6T3ZgnedO2UNUrn8CGw/Qe36ToDnitO6MxlXUVHH6uw5yw92c
81OXvyxpkPQeadnkS6IgEd3E35viKmNZorI5hNFlT9h8FLppi7gfUFKLdQFqKdhRPgMLlsnL++9D
QYx1cyxIpUr+l7Is0Hahq1/0q5ckGpK09VlJnLJfvVwnQoHEeDaLsLf2EkSxfaJc2XE2mtMUu8rM
uAa1+L5OVaHt8nhNcPg0zVS7JhC3UvYJdLb2p9FPcGBLgDJZvx07SJtL9umnpW3pwtQsXzGlR58a
/2y7cV8uEqd5LaqbKDXd+LPZvlySWXmDGyGKto+dqlK0yqhxxgEpL+jq2hwsj1AcFgVHZ9tttT2m
HKYpz0Pji4YKZC1wD012RjUBqt3AR8A3d4zMJkbv6GiA2ccyS2KEhOZcucwdUvmxPLmxxiumxn/F
Hofz3PxaWd5FecsvrM+uABnxz04jeaexyTAFU0zlyTDQ9INckLJQROkt5hCtQxRwH5a/n/3CB+1V
Q5RLE0gymKIVPtpS4/fw3cUV8pjXMArGvBMcaGT8ONLLYZkqXtP85cKM4RrC3c6XF+emKL0WnvRK
92/lPhJzgRjRxOzk1rc7ok8QEHmUIELv+/qNhkD8mZPJlb/BwSqeB8+zOUKSwNn3vWig0+HVVZ+L
I+FWoCrgxwYxoPHb/IWjM8bZJBKXmVA5Vd9F4IUgDh7LToyVP+w/+DQML05f8ARcxLncCGP41jLX
2XYk6imR6kaUM0aSKIPTIKmcl0sacBI3oHY2s4PR251vppsvuSnwEkqkBo/r8AukDfTlRei0Q6J0
sGJs3JVUKO7QYmS2wTBGr3IXUS/AaOSwKIwBmw9nR1LoYo5FzqL/90F0JfoJZg68xH7WLfjfOjTf
u6j1+8njHLRvr9tVcSh5FRNDx3BNzWLe626Oca9d644zO1nrkwlCnRVHT8bYVPC/eNz3Z54hIEkp
Ri+rEq83bpIZIMTytor7UGEo6B36TizLr3XfLm7Ykvna+dSiMcfajbFD5PkvxMy3aBnGPO9zdVkj
KiySODfeeP0mXaauZMgWVYwX1i6UHHCblVbC1JCU65oJ6RENO1+7wu5nzuKoJngTqHLKxQl6C95W
ABQd0IyxXlKb4N6ZRCSg0YupvG1+Eha1u/dzouHHl3Qj9Ucdez0EazZqpuMJN1P91G7Ue1drkxky
ySOapQMdJ6qWgmOSh/bQqfRtYGwBiNVQEZMrB5pWu0O1PHo3QJL8UYGqbkS3iqKa7eDRZNDihlat
NkhAfPC3TasxOYdSLIdIeQjt1/rDdccy92xPMw4bxlcY11fvGURnU+RmJ3ZXAYvL5vJLvT2KAjoy
ry2155yW4IBiNP0IBKuInrsK9OvpFIilXUx+JyXa2TYgcVd4kulTEiAozJ4aZVJLiXFZTS6vkyVK
eXvWZpPtWy/YwhC3i4DvPD1jFP+H5bBN2Znd1uujJehkEzYSgidiG/LiXTfmIL6dTo2W+1CkJsX2
J3gtm92M4BnZ11dxF1PSKw2+/MZwq5XLnn5/nsCcI31VXTVOt9cPlFoRNSrCiV+yqQqQRbEAviT9
i5v6130tn/qQScBGWO6ssOBrrjSRNXnWXTK9OZ5FkKte6+qJ7Fv1/GOii0PBxK/ge3EFXp7aEs6F
GghQCelNCO/Tuq0sLPhsPi1Arvafl6+ynjXtDpXsgHkpnjeaAsQMj4LpMqsHfURYZkDQK8YOlqpw
UfN3RxRYjd6xIoBm2B0XNldXU6dGoCs2d5tMgKXSl68KXGPzkmMnAQ4i8ZN4PKcCcW1gEEsufrCG
JBnhNMrYFRlW+o3RH6SFwh+HA1ztb2WPdt/Rm8LYEkJ2xjoQ/GYLlwCb6qTs+GK/VWyZt8C8nxfU
Bc+MSj2PI5/cNaekI8Amkajnh/PzdTnSynygYzq8G82eUWiFq+/4kt+sgCwHngkosZitqjh+pbYR
aWO58AJN7GsG50o4AOH2eROpnk0Ludfb8rEaJbpNT1KHIEeorguO9YduB5Uws2hHwm38OhVQySN0
E1vf0KduzfYqc4Wpr2FjDsklX0TXVgz0K/UFswlhoMh0o/ejGwuNm2lupKrhAdHHuuBNbYsV8cpe
ViCnn9SpBTEVJb2tP1rHVdrfCXDzVbp5sxfK77IIqPhXFRzqQS/xLSbhi737Px4e3VqicUyc+peE
1pCJZJOSQ26ueCM3xLERek9BffUs7+OcTX2mu4pWeEA9vKcQeWtFl/s7/nndYo6Y9N2qsSD6tubD
xHmOgF9prTakzNgTUSm/RjKIHgKVZLGaSOAiBcwGHXuwEKHK6gskUR/vqBXtZZY4YqFz8HxpCK+y
D3uEfs1jQGYfS9Uzw4FWAodC/L486CQuo1g3xPbT17ocFNqME1R5iZm3LDo7qqnhmqVe7rbhp/v9
mseJ5O5f5sn48w9fGv88Y8fKdsdx8mjPecDx/X67q5wYBetDEJwPeuRTptb65PhWFI+ieyUD1x8q
/+FBN3qm7U8TtSofgzWZjmKnuJTwRALVNb6uriL/aw0IIStir1C/WCraNwWCmn2ewKxW+B6A8MLG
/4LwJPRGPAbhwfuTUBIPJMOpubhA+k0nan26OYqHM5JuJ94UREhWhgUKDaW0E6Eyz6/Nj8pVsVki
9L8rPE/6vNz//Hjz3CbVX9z6DImjBi73aGsRx7JUT1H6oLg+Khf4p/TNoC7qfufNCbXy0egW6lZ4
WDDm6i6eU6Xd+HGSValC5CQSR+962IZiASrm3EVRcEEGEU4jPEzLpYapFqjtdOlrPmGwsTpwfsvw
T4I45hXH6jm7K9cg1WLNk8Ye43cyGf6z2O+OEjbRUDJnr1QrO6HuOjiKOhdufcg0IC4YjIiStlmc
BbP4Nh7XtlPPeljCC+SErsAZxDQElQqVtWbs9Md2E8XDnNP2p0LUDLpxxuluVcQhyG8w+uC+mA+W
3O4d80p3IXEtHEjPFJpxcgVs/t2BttIhkbs0Psq5v7xuvU5Pg6HQgIDBFOEiL/BN7AeCU0cprAIi
WRKyCr2vlcvXsU2sf1EFrK2R11CUz7XArORv+ajHAkQlNGXhULeRzWWL7OC8gCp2gmbX7k8uFekW
RXz1BSIVvzEEQLzzfEcrZqcaual9aDWrHfAjMp0N5j/68m3mmRV/iyKNTdLoyO8maFsuKa3b4zch
8pO9PjOOxfy3InGBOniRqbV0RdablI0CFR/RVcJAiy0tcqS2MJy39Q0Wy2wo9f0pzrVY3YWxY/vy
MRKzvw2VPlMdER5jPFja7x27cE+9l4f5ECpwewBu0ZUWqi4uQPTbbXV57wZPdT6iReWBoMGyW0AY
L63m7zNqRmb796V06q/8zj/bDJdHEBCv1LHtXl0MqZOSCnVatgd/PMwJWSwTPW+bWE0E2h8y2ybv
yLCY3oXOXAMS1Li0HBB/EuOfUJcenwbOPxQWfnGZM1zHPayiulP/9qlbWFR8jBpXtcpqmIZrwyXD
fFrDb5Va5i/bE9qiH2oCAjxsR9nynCRA4W7qmcp6rVPg4WRAjr5NN3LwPjQaJybXhtieQH3yIuXd
vxa3hIjmiE1/sXkCeO4AzB37ORgvR/n83B8p0t5ydjwNVuPbx5Sooorv79kgoRD20YkvYIKaKKJY
MidczUG/TSOF01jkWMquL+SkNAPJkpg/WaYlTFUbD8W8LEvzdRkZDGpEmjexhshzTr5X9YnJD1wv
MUFfErEy4n0YCriP3HoH8FjEJjMgmJHLlk4gjIH7aw1qe+XUMpe7OVvGSkk7XrehsNnzV7WuUCJP
ueBC0WYWvxetjfOOjSslWnxtdhv8v1HpoL5VcZI25XNvJ3tX+GsO1lYUu1DUT2oB4ieCI8hzXU7J
4ae3AIclPpdC5PSp0odpgnooIafOm0mbgzQTOWMO/GURIZL8AsmhkyLwZV8tn7olk5SNk0TLw90j
n/aunHs+PVcUS5GV28IB+iJe+STx1VBdq8fcaFCuZcicrjpBN/iwbIcgETlcroduip5Ps/SF/z3V
NOVR21GGYzUdNBbqyE5Dt3nXkXi3N4Df+5bZOUFy27ZCFuCWNnroqgl6pAItdGto+iI/d/2FK0d8
IQcFRB11286aISOIKs3ElU7v7cUzT0IODw7ehjfp1eOm4UsUgLXy1PZkyG4X0C7yiZm0BCWkLfcS
EYQCGzVjb7tr9zNqkxYoFUj2lr/gMXHFBZHTuKb7WCXUg614y6xoxd+kva140RMFfogEcRCwuLMX
PelwbN+F8g5LCaneXakRvICCUky1MupTJrjrlf+tr+rlHVenczK79Ch/TkOt9aUloS5NRhnMoOI0
utD5aecxoXawQTVGbpXjBUeuZDHqnl/2RyVMlRjZ/gfucSJS9eU1gtugNg2+nlLVROVIguvstgua
fRaHfF1qhWKOUKHw7I9RCiS+yS8BV1HhFd8oqoR76owmstJrTspBzCVnNtrCWr69LciHI2mLyzFb
T+RkITta+Fr3nbOENwzSbLaAP+k9qMrAjzKMAkskO2jboU8TNgFwY4Oegh2yz024otdD1AjKHsuW
yl/yw8rCJ+qvNc4fZBmbfqXUyOK8xh7dAakdzu23qDg4XKT12VLk+6mbpJD0+N+YnwnjevQ+jN+y
APFcvMK8dpOEyzDIxD6WJVMK6TZlACh7/orJCeTSOtPD6phHtuCgyiKLyeS9vzhLyetcE2/2auf0
PZ+CBYJyJZBUP2KMnbkTWKlEJjYNBHvcVOBkfVIID4oPRKuoMu7RiJJxwidPZabn/rC3fntWvvyU
AJiD/34Cb6cJARhUpeyg+Wn23/inoISQTpC8BxbSfxo6y5CTAe93huD/H/jPjKGqWRfSP99y1TDB
dTclNmfBK7u8YpLL8RkxJZGauGt6U9kMXiwHKIVLW93zTIrYpwVLDXxeKRJm5y0aXKQMuGvE9h/6
E6GIoZTkgzgzWkmfJw1r05H0WcAVfJttRntG8iGqk4p3ET41EPqEAKrhiti9pUiZK3x2KbODzROw
DBaYv6hVfecBj11qS9qfGk87wh+luBjwrRiPE6PESRYoOICQvgZPhYrctatqCZq0TvwOv+IGy8pu
Kx3R3+Fr6qL+QeYkt9M5LAUNXd9e6Vqfu7mOd1Dr4U9dk4VigGCiGr+Rswp2dYPBhIRZpNHrsbv+
P2BAv5nUbyuTf38FRzFExZazs0XoTvXTmb8/hhu+X8B83ybHWLn3ji+M7LhtXYWfYrVTR0jplIPd
rGYWCu9Zg5m5odyWYuBGvzl+iwirZ6Tr352XNPrJFcqwHKRlF58rmCgSJxmkq2UnCFf7oCkgWYgF
ZMmulwAV7PtIBiLY2GhV26TroLo4QVcD6qULNIfRnwr4J/T71+u83rhlpj4L7AQMxnjr5OrbLYVu
pZKXyoXAH8o4vf2yQd+bpFQo/AJ5u/OjweFRxLYFfnfYyuk1aV7cDvguZ7CaS7bxNDw0QjuyPq/b
I1hz9Jv7UIxhMXApQDtadUhyfEAQMX/2oUGI3lHDwoGiNBql18u9OWTpfjX4hSPlICD1swYDa4Bf
P17bW0GuYT7PzZ+kkYzCC3a7gY1aBhfZ1YnetOIHd8olsrXG/hYFvIgwhSbYwSNt8OZSH/n/EXHb
4b0UFqgXhqZ/7mImwH9nYPdlbH6MIODzoRsElFutL8yAKB85W9tSkSfRnoxMoRxSTj/9KHWyMdHU
tlIm8o74OHx3ovPnAmKDK5hfau31V/+vK+Q4ySU+9vt6Ox436Rg3PBlceQBU/1ar4IR7tW/HxUdO
jvse+eYNw7KED34a6xUmedIps5cCIlqKZ/2FPnPFUMTzCa0rkRN2qVfp/an/ivx3imoXBt0JPu/v
5eC5reloQYbWza/Z5Ie9fNDymwUQlJ7OcZ9w0fUyO6W6pac5Y2HWRXs9YyoR08Io7aEpEJt6HmJ1
VDG7NTuXyfprQ01TdIgCFifkRlLAOfpYf/1LNbM0ig1H6TSsb1awbee+hID92Y4v0dcgZeGgqMof
3a+HZK/MkNIkL1l6zAvtUkD+qtNuc06pYyBiDzLbhn7Ym8m3RLFpZ+a0v+3z2Eob6PZofdJNsR7P
2KSP15Hs7j6Rt+jWmaWjGGc8LvaWwNAEHYLtq3NV0U511SpNiJW+XGnz0ae0cy32mCfGHXvcZVzH
uxc/0jgLYpLfEH148rkF4SjGiDjLRqkG8QmhlJ00cBM27pIY19SegSbKYeA1+1MKLZrz9IpOcaWh
wNrQaJEC8BywrylCUH/vbpjdGlTi1leYNAhZnOc+Hh23HJ98pbANZkJXW57UgxqV9te300T+n7zW
JUhuAzJL/ougGO39obEql/lmUAu7e8PsJdXIijizyVhks9M3qYe8R0Fy+Dz9n7oL6RhtPN2JDzvC
fhdrXK08Co+DyFYhzs2wUbH9HodM2GsDD+bAUKChP0gfkBwC5bEs64PcSQf+6Ivvb/HlhmIKL+Fc
1oCG3w94f30683LB1aW26I9m+nPEZhNFSCYvT61tyGACqVw5AOSPCQi74KP/cPw85DK5w4ymZud1
rZJ6VriQmhSg2kN0IDm04ol4MRUpiQMHUmaSzKfX9DOtLlOt6Uc2G8taDreGHZoYqhyC4s5ucefF
UrYiUYN4IYcvy3qGiP/KSpd4GChUqL0F7oYtjn2UAHNaAQdMGKY0AXb1K7Qc091k7PZtypE3I/Ux
rT03WSDDGCgbvE5zuYxBtByZFfJ2uXnVzwERygklCVwxP6Stp//zcWVSIvzcnP3lg3f00rCoLBoV
maTPe3fxmLCD9nPuBKJ8nc7FQY09pqrou42i1K8I2JcaY36XgYoW4eA7rFEyIKdesQrNbs46DS1w
hHoPxRS5QIa3hq8hIoSJFIVXcFxfdiYY2ZGCgnFGUVSThSQI9QIBQ3heUKdlbNY7TB+VsfpeaT+6
yhAjTfVz3ax6KXN28wuNOJulkhucNWm8+NYp4upWv5Lymx2nui0HjjT/IqV1dJQ6Jso=
`pragma protect end_protected

189
gowin/bttn/impl/gwsynthesis/bttn_syn.rpt.html
View File

@ -1,189 +0,0 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>synthesis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper{ width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table td.label { min-width: 100px; width: 8%;}
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.9.03 Education (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sat Jan 18 22:12:34 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>bttn</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.353s, Peak memory usage = 391.969MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 391.969MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 391.969MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 391.969MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 391.969MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 391.969MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 391.969MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 391.969MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 391.969MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 391.969MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 391.969MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 391.969MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 391.969MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 391.969MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 391.969MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>25</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>25</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>13</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>12</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>137</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>20</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>35</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>82</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>137(137 LUT, 0 ALU) / 20736</td>
<td><1%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>0 / 46</td>
<td>0%</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

56
gowin/bttn/impl/gwsynthesis/bttn_syn_resource.html
View File

@ -1,56 +0,0 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Hierarchy Module Resource</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
div#main_wrapper{ width: 100%; }
h1 {text-align: center; }
h1 {margin-top: 36px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { align = "center"; padding: 5px 2px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="content">
<h1>Hierarchy Module Resource</h1>
<table>
<tr>
<th class="label">MODULE NAME</th>
<th class="label">REG NUMBER</th>
<th class="label">ALU NUMBER</th>
<th class="label">LUT NUMBER</th>
<th class="label">DSP NUMBER</th>
<th class="label">BSRAM NUMBER</th>
<th class="label">SSRAM NUMBER</th>
<th class="label">ROM16 NUMBER</th>
</tr>
<tr>
<td class="label">bttn (//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp|--s1
(//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">137</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

4
gowin/bttn/impl/gwsynthesis/bttn_syn_rsc.xml
View File

@ -1,4 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<Module name="bttn" T_Lut="137(0)">
<SubModule name="s1" Lut="137" T_Lut="137(137)"/>
</Module>

BIN
gowin/bttn/impl/pnr/bttn.bin
View File

Binary file not shown.

BIN
gowin/bttn/impl/pnr/bttn.binx
View File

Binary file not shown.

BIN
gowin/bttn/impl/pnr/bttn.db
View File

Binary file not shown.

1378
gowin/bttn/impl/pnr/bttn.fs
View File

File diff suppressed because it is too large Load Diff

29
gowin/bttn/impl/pnr/bttn.log
View File

@ -1,29 +0,0 @@
Reading netlist file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg"
Parsing netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg" completed
Processing netlist completed
Reading constraint file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst"
Physical Constraint parsed completed
Running placement......
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
[30%] Placement Phase 2 completed
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.power.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.pin.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.rpt.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.rpt.txt" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.tr.html" completed
Sat Jan 18 22:12:46 2025

3897
gowin/bttn/impl/pnr/bttn.pin.html
View File

File diff suppressed because it is too large Load Diff

269
gowin/bttn/impl/pnr/bttn.power.html
View File

@ -1,269 +0,0 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//ENhttp://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Power Analysis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper { width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td {white-space:pre; border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.thermal_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.Configure_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table th.label { min-width: 8%; width: 8%; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#Message" style=" font-size: 16px;">Power Messages</a>
<ul>
<li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li>
</ul>
</li>
<li><a href="#Summary" style=" font-size: 16px;">Power Summary</a>
<ul>
<li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li>
<li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li>
<li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li>
</ul>
</li>
<li><a href="#Detail" style=" font-size: 16px;">Power Details</a>
<ul>
<li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li>
<li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li>
<li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="Message">Power Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Power Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.9.03 Education (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sat Jan 18 22:12:42 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h2><a name="Configure_Info">Configure Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Grade</td>
<td>Commercial</td>
</tr>
<tr>
<td class="label">Process</td>
<td>Typical</td>
</tr>
<tr>
<td class="label">Ambient Temperature</td>
<td>25.000
</tr>
<tr>
<td class="label">Use Custom Theta JA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Heat Sink</td>
<td>None</td>
</tr>
<tr>
<td class="label">Air Flow</td>
<td>LFM_0</td>
</tr>
<tr>
<td class="label">Use Custom Theta SA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Board Thermal Model</td>
<td>None</td>
</tr>
<tr>
<td class="label">Use Custom Theta JB</td>
<td>false</td>
</tr>
<tr>
<td class="label">Related Vcd File</td>
<td></td>
</tr>
<tr>
<td class="label">Related Saif File</td>
<td></td>
</tr>
<tr>
<td class="label">Filter Glitches</td>
<td>false</td>
</tr>
<tr>
<td class="label">Default IO Toggle Rate</td>
<td>0.125</td>
</tr>
<tr>
<td class="label">Default Remain Toggle Rate</td>
<td>0.125</td>
</tr>
</table>
<h1><a name="Summary">Power Summary</a></h1>
<h2><a name="Power_Info">Power Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Total Power (mW)</td>
<td>124.284</td>
</tr>
<tr>
<td class="label">Quiescent Power (mW)</td>
<td>121.171</td>
</tr>
<tr>
<td class="label">Dynamic Power (mW)</td>
<td>3.114</td>
</tr>
</table>
<h2><a name="Thermal_Info">Thermal Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Junction Temperature</td>
<td>28.980</td>
</tr>
<tr>
<td class="label">Theta JA</td>
<td>32.020</td>
</tr>
<tr>
<td class="label">Max Allowed Ambient Temperature</td>
<td>81.020</td>
</tr>
</table>
<h2><a name="Supply_Summary">Supply Information:</a></h2>
<table class="summary_table">
<tr>
<th class="label">Voltage Source</th>
<th class="label">Voltage</th>
<th class="label">Dynamic Current(mA)</th>
<th class="label">Quiescent Current(mA)</th>
<th class="label">Power(mW)</th>
</tr>
<tr>
<td>VCC</td>
<td>1.000</td>
<td>0.513</td>
<td>69.983</td>
<td>70.496</td>
</tr>
<tr>
<td>VCCX</td>
<td>3.300</td>
<td>0.513</td>
<td>15.000</td>
<td>51.192</td>
</tr>
<tr>
<td>VCCIO18</td>
<td>1.800</td>
<td>0.505</td>
<td>0.937</td>
<td>2.597</td>
</tr>
</table>
<h1><a name="Detail">Power Details</a></h1>
<h2><a name="By_Block_Type">Power By Block Type:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Block Type</th>
<th class="label">Total Power(mW)</th>
<th class="label">Static Power(mW)</th>
<th class="label">Average Toggle Rate(millions of transitions/sec)</th>
</tr>
<tr>
<td>IO</td>
<td>7.854
<td>4.740
<td>6.500
</tr>
</table>
<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Hierarchy Entity</th>
<th class="label">Total Power(mW)</th>
<th class="label">Block Dynamic Power(mW)</th>
</tr>
<tr>
<td>bttn</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>bttn/s1/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
</table>
<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Domain</th>
<th class="label">Clock Frequency(Mhz)</th>
<th class="label">Total Dynamic Power(mW)</th>
</tr>
<tr>
<td>NO CLOCK DOMAIN</td>
<td>0.000</td>
<td>0.000</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

4143
gowin/bttn/impl/pnr/bttn.rpt.html
View File

File diff suppressed because it is too large Load Diff

363
gowin/bttn/impl/pnr/bttn.rpt.txt
View File

@ -1,363 +0,0 @@
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
1. PnR Messages
<Report Title>: PnR Report
<Design File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg
<Physical Constraints File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst
<Timing Constraints File>: ---
<Tool Version>: V1.9.9.03 Education (64-bit)
<Part Number>: GW2A-LV18PG256C8/I7
<Device>: GW2A-18
<Device Version>: C
<Created Time>:Sat Jan 18 22:12:45 2025
2. PnR Details
Running placement:
Placement Phase 0: CPU time = 0h 0m 0.021s, Elapsed time = 0h 0m 0.021s
Placement Phase 1: CPU time = 0h 0m 0.354s, Elapsed time = 0h 0m 0.354s
Placement Phase 2: CPU time = 0h 0m 0.008s, Elapsed time = 0h 0m 0.008s
Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Running routing:
Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Routing Phase 1: CPU time = 0h 0m 0.173s, Elapsed time = 0h 0m 0.173s
Routing Phase 2: CPU time = 0h 0m 0.224s, Elapsed time = 0h 0m 0.224s
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Total Routing: CPU time = 0h 0m 0.397s, Elapsed time = 0h 0m 0.397s
Generate output files:
CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s
Total Time and Memory Usage: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 391MB
3. Resource Usage Summary
----------------------------------------------------------
Resources | Usage
----------------------------------------------------------
Logic | 137/20736 <1%
--LUT,ALU,ROM16 | 137(137 LUT, 0 ALU, 0 ROM16)
--SSRAM(RAM16) | 0
Register | 0/16173 0%
--Logic Register as Latch | 0/15552 0%
--Logic Register as FF | 0/15552 0%
--I/O Register as Latch | 0/621 0%
--I/O Register as FF | 0/621 0%
CLS | 74/10368 <1%
I/O Port | 25
I/O Buf | 25
--Input Buf | 13
--Output Buf | 12
--Inout Buf | 0
IOLOGIC | 0%
BSRAM | 0%
DSP | 0%
PLL | 0/4 0%
DCS | 0/8 0%
DQCE | 0/24 0%
OSC | 0/1 0%
CLKDIV | 0/8 0%
DLLDLY | 0/8 0%
DQS | 0/9 0%
DHCEN | 0/16 0%
==========================================================
4. I/O Bank Usage Summary
-----------------------
I/O Bank | Usage
-----------------------
bank 0 | 1/29(3%)
bank 1 | 3/20(15%)
bank 2 | 2/20(10%)
bank 3 | 8/32(25%)
bank 4 | 2/36(5%)
bank 5 | 0/36(0%)
bank 6 | 1/18(5%)
bank 7 | 8/16(50%)
=======================
5. Global Clock Usage Summary
-------------------------------
Global Clock | Usage
-------------------------------
PRIMARY | 0/8(0%)
LW | 0/8(0%)
GCLK_PIN | 1/8(13%)
PLL | 0/4(0%)
CLKDIV | 0/8(0%)
DLLDLY | 0/8(0%)
===============================
6. Global Clock Signals
-------------------------------------------
Signal | Global Clock | Location
-------------------------------------------
===========================================
7. Pinout by Port Name
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | BankVccio
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
A[0] | | A11/7 | Y | in | IOL15[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
A[1] | | N6/3 | Y | in | IOR51[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
A[2] | | E15/1 | Y | in | IOT44[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | NA | NA | 1.8
A[3] | | L9/3 | Y | in | IOR40[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
B[0] | | B11/7 | Y | in | IOL13[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
B[1] | | D11/7 | Y | in | IOL22[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
B[2] | | N7/3 | Y | in | IOR47[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
B[3] | | N8/3 | Y | in | IOR40[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
opCodeA[0] | | T5/4 | Y | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
opCodeA[1] | | T4/4 | Y | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
opCodeA[2] | | E8/6 | Y | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
select[0] | | A15/7 | Y | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
select[1] | | A14/7 | Y | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
Y[0] | | P6/3 | Y | out | IOR53[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[1] | | T7/3 | Y | out | IOR29[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[2] | | P8/3 | Y | out | IOR42[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[3] | | P9/3 | Y | out | IOR38[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[4] | | T11/2 | Y | out | IOR24[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[5] | | T12/2 | Y | out | IOR17[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[6] | | M14/1 | Y | out | IOT40[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
Y[7] | | J14/0 | Y | out | IOT22[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
Y[8] | | D14/1 | Y | out | IOT44[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
Y[9] | | B14/7 | Y | out | IOL2[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[10] | | B13/7 | Y | out | IOL8[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[11] | | B12/7 | Y | out | IOL7[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
===================================================================================================================================================================================================================
8. All Package Pins
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | Bank Vccio
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
L15/0 | - | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D16/0 | - | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E14/0 | - | in | IOT4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C16/0 | - | in | IOT5[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D15/0 | - | in | IOT5[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E16/0 | - | in | IOT6[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F15/0 | - | in | IOT6[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F13/0 | - | in | IOT8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G12/0 | - | in | IOT8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F14/0 | - | in | IOT9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F16/0 | - | in | IOT9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F12/0 | - | in | IOT12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G13/0 | - | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G15/0 | - | in | IOT13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G14/0 | - | in | IOT13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G11/0 | - | in | IOT14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H12/0 | - | in | IOT14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G16/0 | - | in | IOT16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H15/0 | - | in | IOT16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H13/0 | - | in | IOT18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J12/0 | - | in | IOT18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H14/0 | - | in | IOT20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H16/0 | - | in | IOT20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J16/0 | - | in | IOT22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J14/0 | Y[7] | out | IOT22[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
J15/0 | - | in | IOT24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K16/0 | - | in | IOT24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H11/0 | - | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J13/0 | - | in | IOT27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K14/1 | - | in | IOT30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K15/1 | - | in | IOT30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J11/1 | - | in | IOT32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L12/1 | - | in | IOT32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L16/1 | - | in | IOT34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L14/1 | - | in | IOT34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K13/1 | - | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K12/1 | - | in | IOT36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K11/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L13/1 | - | in | IOT38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M14/1 | Y[6] | out | IOT40[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
M15/1 | - | in | IOT40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D14/1 | Y[8] | out | IOT44[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
E15/1 | A[2] | in | IOT44[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | NA | NA | 1.8
N15/1 | - | in | IOT48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P16/1 | - | in | IOT48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N16/1 | - | in | IOT52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N14/1 | - | in | IOT52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P15/1 | - | in | IOT54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R16/1 | - | in | IOT54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
A4/5 | - | in | IOB2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C5/5 | - | in | IOB2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D6/5 | - | in | IOB3[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E7/5 | - | in | IOB3[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A3/5 | - | in | IOB4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B4/5 | - | in | IOB4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A5/5 | - | in | IOB7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B6/5 | - | in | IOB7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B1/5 | - | in | IOB8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C2/5 | - | in | IOB8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D3/5 | - | in | IOB9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D1/5 | - | in | IOB9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E2/5 | - | in | IOB12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E3/5 | - | in | IOB12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B3/5 | - | in | IOB13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A2/5 | - | in | IOB13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C1/5 | - | in | IOB14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D2/5 | - | in | IOB14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E1/5 | - | in | IOB16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F2/5 | - | in | IOB16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F4/5 | - | in | IOB18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G6/5 | - | in | IOB18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F3/5 | - | in | IOB19[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F1/5 | - | in | IOB19[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G5/5 | - | in | IOB20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G4/5 | - | in | IOB20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G2/5 | - | in | IOB21[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G3/5 | - | in | IOB21[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F5/5 | - | in | IOB22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H6/5 | - | in | IOB22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G1/5 | - | in | IOB24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H2/5 | - | in | IOB24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H4/5 | - | in | IOB26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J6/5 | - | in | IOB26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J1/5 | - | in | IOB27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J3/5 | - | in | IOB27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L2/4 | - | in | IOB30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M1/4 | - | in | IOB30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H3/4 | - | in | IOB32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H1/4 | - | in | IOB32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J2/4 | - | in | IOB34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K1/4 | - | in | IOB34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H5/4 | - | in | IOB35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J4/4 | - | in | IOB35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K3/4 | - | in | IOB36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K2/4 | - | in | IOB36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J5/4 | - | in | IOB37[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K6/4 | - | in | IOB37[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L1/4 | - | in | IOB38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L3/4 | - | in | IOB38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K4/4 | - | in | IOB39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L5/4 | - | in | IOB39[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K5/4 | - | in | IOB40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L4/4 | - | in | IOB40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N2/4 | - | in | IOB41[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P1/4 | - | in | IOB41[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M3/4 | - | in | IOB42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N1/4 | - | in | IOB42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M2/4 | - | in | IOB43[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N3/4 | - | in | IOB43[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R1/4 | - | in | IOB44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P2/4 | - | in | IOB44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P4/4 | - | in | IOB45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T4/4 | opCodeA[1] | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R3/4 | - | in | IOB48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T2/4 | - | in | IOB48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P5/4 | - | in | IOB50[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R5/4 | - | in | IOB50[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R4/4 | - | in | IOB52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T3/4 | - | in | IOB52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R6/4 | - | in | IOB54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T5/4 | opCodeA[0] | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
B14/7 | Y[9] | out | IOL2[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
A15/7 | select[0] | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
C12/7 | - | in | IOL7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B12/7 | Y[11] | out | IOL7[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
B13/7 | Y[10] | out | IOL8[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
A14/7 | select[1] | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
F10/7 | - | in | IOL11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B11/7 | B[0] | in | IOL13[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
A12/7 | - | in | IOL13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A11/7 | A[0] | in | IOL15[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
C11/7 | - | in | IOL15[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D10/7 | - | in | IOL17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E10/7 | - | in | IOL17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D11/7 | B[1] | in | IOL22[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
A9/7 | - | in | IOL27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C9/7 | - | in | IOL27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C8/6 | - | in | IOL29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A8/6 | - | in | IOL29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F9/6 | - | in | IOL31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E11/6 | - | in | IOL31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B9/6 | - | in | IOL33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A10/6 | - | in | IOL33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F8/6 | - | in | IOL35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D9/6 | - | in | IOL35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D8/6 | - | in | IOL38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E9/6 | - | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B7/6 | - | in | IOL40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C7/6 | - | in | IOL40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F7/6 | - | in | IOL45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E8/6 | opCodeA[2] | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
C4/6 | - | in | IOL47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B5/6 | - | in | IOL47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E6/6 | - | in | IOL53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D7/6 | - | in | IOL53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
T15/2 | - | in | IOR7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R14/2 | - | in | IOR7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P12/2 | - | in | IOR8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T13/2 | - | in | IOR8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R12/2 | - | in | IOR11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P13/2 | - | in | IOR11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R11/2 | - | in | IOR17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T12/2 | Y[5] | out | IOR17[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
R13/2 | - | in | IOR20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T14/2 | - | in | IOR20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M10/2 | - | in | IOR22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N11/2 | - | in | IOR22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T11/2 | Y[4] | out | IOR24[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
P11/2 | - | in | IOR24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C6/2 | - | out | IOR25[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
B8/2 | - | in | IOR25[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A7/2 | - | in | IOR26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A6/2 | - | in | IOR26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N10/2 | - | in | IOR27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M11/2 | - | in | IOR27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T7/3 | Y[1] | out | IOR29[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
R8/3 | - | in | IOR29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M16/3 | - | in | IOR30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B16/3 | - | in | IOR30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C15/3 | - | in | IOR31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B10/3 | - | in | IOR31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A13/3 | - | in | IOR32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C13/3 | - | in | IOR32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P10/3 | - | in | IOR33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R10/3 | - | in | IOR33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M9/3 | - | in | IOR34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L10/3 | - | in | IOR34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R9/3 | - | in | IOR35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T10/3 | - | in | IOR35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M8/3 | - | in | IOR36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N9/3 | - | in | IOR36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T9/3 | - | in | IOR38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P9/3 | Y[3] | out | IOR38[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
C10/3 | - | in | IOR39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N8/3 | B[3] | in | IOR40[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
L9/3 | A[3] | in | IOR40[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
P8/3 | Y[2] | out | IOR42[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
T8/3 | - | in | IOR42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M6/3 | - | in | IOR44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L8/3 | - | in | IOR44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M7/3 | - | in | IOR47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N7/3 | B[2] | in | IOR47[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
R7/3 | - | in | IOR49[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P7/3 | - | in | IOR49[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N6/3 | A[1] | in | IOR51[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
P6/3 | Y[0] | out | IOR53[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
T6/3 | - | in | IOR53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
========================================================================================================================================================================================

10
gowin/bttn/impl/pnr/bttn.tr.html
View File

@ -1,10 +0,0 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Timing Analysis Report</title>
</head>
<frameset cols="20%, 80%">
<frame src="bttn_tr_cata.html" name="cataFrame" />
<frame src="bttn_tr_content.html" name="mainFrame"/>
</frameset>
</html>

132
gowin/bttn/impl/pnr/bttn_tr_cata.html
View File

@ -1,132 +0,0 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Timing Report Navigation</title>
<style type="text/css">
@import url(../temp/style.css);
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#catalog_wrapper { width: 100%; }
div#catalog ul { list-style: none; margin-left: -15px; }
div#catalog ul li { margin: 3px 0 3px 0; text-align: left; color: #0084ff; white-space: nowrap; word-break: keep-all; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 4px; margin: 0 0 0 0; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
div.triangle_fake, div.triangle { display: inline-block; cursor: pointer; width: 8px; height: 0; border-top: 5px solid transparent; border-bottom: 5px solid transparent; }
div.triangle_fake { border-left: 5px solid transparent; }
div.triangle { border-left: 5px solid #0084ff; }
div.triangle:hover { border-left-color: #000; }
</style>
<script>
function onClick(obj){var childs=obj.parentNode.childNodes;for(var i=0;i<childs.length;i++){if(childs[i].tagName=="UL"){if(childs[i].style.display=="none"){childs[i].style.display="block"}else{childs[i].style.display="none"}}}};
</script>
</head>
<body>
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<!-- messages begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Message" target="mainFrame" style=" font-size: 16px;">Timing Messages</a></li>
<!-- messages end-->
<!-- summaries begin-->
<li><div class="triangle" onclick="onClick(this)"></div><a href="bttn_tr_content.html#Summary" style=" font-size: 16px;" target="mainFrame">Timing Summaries</a>
<ul>
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#STA_Tool_Run_Summary" style=" font-size: 14px;" target="mainFrame">STA Tool Run Summary</a></li>
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Clock_Report" style=" font-size: 14px;" target="mainFrame">Clock Summary</a></li>
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Max_Frequency_Report" style=" font-size: 14px;" target="mainFrame">Max Frequency Summary</a></li>
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Total_Negative_Slack_Report" style=" font-size: 14px;" target="mainFrame">Total Negative Slack Summary</a></li>
</ul>
</li>
<!-- summaries end-->
<!-- details begin-->
<li><div class="triangle" onclick="onClick(this)"></div><a href="bttn_tr_content.html#Detail" style=" font-size: 16px;" target="mainFrame">Timing Details</a>
<ul>
<!--All_Path_Slack_Table begin-->
<li><div class="triangle" onclick="onClick(this)"></div><a href="bttn_tr_content.html#All_Path_Slack_Table" style=" font-size: 14px;" target="mainFrame">Path Slacks Table</a>
<ul>
<!--Setup_Slack_Table begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Setup_Slack_Table" style=" font-size: 13px;" target="mainFrame">Setup Paths Table</a>
</li>
<!--Setup_Slack_Table end-->
<!--Hold_Slack_Table begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Hold_Slack_Table" style=" font-size: 13px;" target="mainFrame">Hold Paths Table</a>
</li>
<!--Hold_Slack_Table end-->
<!--Recovery_Slack_Table begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Recovery_Slack_Table" style=" font-size: 13px;" target="mainFrame">Recovery Paths Table</a>
</li>
<!--Recovery_Slack_Table end-->
<!--Removal_Slack_Table begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Removal_Slack_Table" style=" font-size: 13px;" target="mainFrame">Removal Paths Table</a>
</li>
<!--Removal_Slack_Table end-->
</ul>
</li><!--All_Path_Slack_Table end-->
<!--MIN_PULSE_WIDTH_TABLE begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#MIN_PULSE_WIDTH_TABLE" style=" font-size: 14px;" target="mainFrame">Minimum Pulse Width Table</a>
</li>
<!--MIN_PULSE_WIDTH_TABLE end-->
<!--Timing_Report_by_Analysis_Type begin-->
<li><div class="triangle" onclick="onClick(this)"></div><a href="bttn_tr_content.html#Timing_Report_by_Analysis_Type" style=" font-size: 14px;" target="mainFrame">Timing Report By Analysis Type</a>
<ul>
<!--Setup_Analysis begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Setup_Analysis" style=" font-size: 13px;" target="mainFrame">Setup Analysis Report</a>
</li>
<!--Setup_Analysis end-->
<!--Hold_Analysis begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Hold_Analysis" style=" font-size: 13px;" target="mainFrame">Hold Analysis Report</a>
</li>
<!--Hold_Analysis end-->
<!--Recovery_Analysis begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Recovery_Analysis" style=" font-size: 13px;" target="mainFrame">Recovery Analysis Report</a>
</li>
<!--Recovery_Analysis end-->
<!--Removal_Analysis begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Removal_Analysis" style=" font-size: 13px;" target="mainFrame">Removal Analysis Report</a>
</li>
<!--Removal_Analysis end-->
</ul>
</li>
<!--Timing_Report_by_Analysis_Type end-->
<!--Minimum_Pulse_Width_Report begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Minimum_Pulse_Width_Report" style=" font-size: 14px;" target="mainFrame">Minimum Pulse Width Report</a>
</li>
<!--Minimum_Pulse_Width_Report end-->
<!--High_Fanout_Nets_Report begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#High_Fanout_Nets_Report" style=" font-size: 14px;" target="mainFrame">High Fanout Nets Report</a></li>
<!--High_Fanout_Nets_Report end-->
<!--Route_Congestions_Report begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Route_Congestions_Report" style=" font-size: 14px;" target="mainFrame">Route Congestions Report</a></li>
<!--Route_Congestions_Report end-->
<!--Timing_Exceptions_Report begin-->
<li><div class="triangle" onclick="onClick(this)"></div><a href="bttn_tr_content.html#Timing_Exceptions_Report" style=" font-size: 14px;" target="mainFrame">Timing Exceptions Report</a>
<ul>
<!--Setup_Analysis_Exceptions begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Setup_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Setup Analysis Report</a>
</li>
<!--Setup_Analysis_Exceptions end-->
<!--Hold_Analysis_Exceptions begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Hold_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Hold Analysis Report</a>
</li>
<!--Hold_Analysis_Exceptions end-->
<!--Recovery_Analysis_Exceptions begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Recovery_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Recovery Analysis Report</a>
</li>
<!--Recovery_Analysis_Exceptions end-->
<!--Removal_Analysis_Exceptions begin-->
<li><div class="triangle_fake" onclick="onClick(this)"></div><a href="bttn_tr_content.html#Removal_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Removal Analysis Report</a>
</li>
<!--Removal_Analysis_Exceptions end-->
</ul>
</li>
<!--Timing_Exceptions_Report end-->
<!--SDC_Report begin-->
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#SDC_Report" style=" font-size: 14px;" target="mainFrame">Timing Constraints Report</a></li>
<!--SDC_Report end-->
</ul>
</li>
<!-- details end-->
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
</body>
</html>

257
gowin/bttn/impl/pnr/bttn_tr_content.html
View File

@ -1,257 +0,0 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Timing Analysis Report</title>
<style type="text/css">
@import url(../temp/style.css);
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#content { width: 100%; margin: }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td {white-space:pre; border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table th.label { min-width: 8%; width: 8%; }
</style>
</head>
<body>
<div id="content">
<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.9.03 Education (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sat Jan 18 22:12:46 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.95V 85C C8/I7</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.05V 0C C8/I7</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>124</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>12</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
</table>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h4>Nothing to report!</h4>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h4>No setup paths to report!</h4>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h4>No hold paths to report!</h4>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>No recovery paths to report!</h4>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>No removal paths to report!</h4>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h4>Nothing to report!</h4>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R29C29</td>
<td>52.78%</td>
</tr>
<tr>
<td>R30C29</td>
<td>40.28%</td>
</tr>
<tr>
<td>R27C29</td>
<td>33.33%</td>
</tr>
<tr>
<td>R30C28</td>
<td>33.33%</td>
</tr>
<tr>
<td>R29C28</td>
<td>27.78%</td>
</tr>
<tr>
<td>R29C30</td>
<td>27.78%</td>
</tr>
<tr>
<td>R30C27</td>
<td>26.39%</td>
</tr>
<tr>
<td>R29C27</td>
<td>23.61%</td>
</tr>
<tr>
<td>R30C30</td>
<td>19.44%</td>
</tr>
<tr>
<td>R27C28</td>
<td>19.44%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
</div><!-- content -->
</body>
</html>

13
gowin/bttn/impl/pnr/cmd.do
View File

@ -1,13 +0,0 @@
-d \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg
-p GW2A-18C-PBGA256-8
-pn GW2A-LV18PG256C8/I7
-cst \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst
-cfg \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\device.cfg
-bit
-tr
-ph
-timing
-cst_error
-correct_hold 1
-route_maxfan 23
-global_freq 100.000

21
gowin/bttn/impl/pnr/device.cfg
View File

@ -1,21 +0,0 @@
set JTAG regular_io = false
set SSPI regular_io = false
set MSPI regular_io = false
set READY regular_io = false
set DONE regular_io = false
set I2C regular_io = false
set RECONFIG_N regular_io = false
set CRC_check = true
set compress = false
set encryption = false
set security_bit_enable = true
set bsram_init_fuse_print = true
set background_programming = off
set secure_mode = false
set program_done_bypass = false
set wake_up = 0
set format = binary
set power_on_reset_monitor = true
set multiboot_spi_flash_address = 0x00000000
set vccx = 3.3
set unused_pin = default

702
gowin/bttn/impl/temp/rtl_parser.result
View File

@ -1,702 +0,0 @@
[
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
"InstLine" : 1,
"InstName" : "bttn",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
"ModuleLine" : 1,
"ModuleName" : "bttn",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
"InstLine" : 10,
"InstName" : "a1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
"ModuleLine" : 1,
"ModuleName" : "ALU",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
"InstLine" : 18,
"InstName" : "opCd",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/opCode.v",
"ModuleLine" : 1,
"ModuleName" : "opCode"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
"InstLine" : 20,
"InstName" : "aU",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
"ModuleLine" : 1,
"ModuleName" : "arithmeticUnit",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
"InstLine" : 13,
"InstName" : "a1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"ModuleLine" : 1,
"ModuleName" : "addition",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 11,
"InstName" : "f0",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 12,
"InstName" : "f1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 13,
"InstName" : "f2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 14,
"InstName" : "f3",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
"InstLine" : 14,
"InstName" : "s1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
"ModuleLine" : 1,
"ModuleName" : "subtraction",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
"InstLine" : 11,
"InstName" : "f0",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "fullsubtraction",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 8,
"InstName" : "hf1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 9,
"InstName" : "hf2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
"InstLine" : 12,
"InstName" : "f1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "fullsubtraction",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 8,
"InstName" : "hf1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 9,
"InstName" : "hf2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
"InstLine" : 13,
"InstName" : "f2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "fullsubtraction",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 8,
"InstName" : "hf1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 9,
"InstName" : "hf2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
"InstLine" : 14,
"InstName" : "f3",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "fullsubtraction",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 8,
"InstName" : "hf1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 9,
"InstName" : "hf2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
}
]
}
]
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
"InstLine" : 21,
"InstName" : "lU",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/logicUnit.v",
"ModuleLine" : 1,
"ModuleName" : "logicUnit"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
"InstLine" : 22,
"InstName" : "mU",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/multiplier.v",
"ModuleLine" : 1,
"ModuleName" : "multiplier",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/multiplier.v",
"InstLine" : 26,
"InstName" : "add0",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"ModuleLine" : 1,
"ModuleName" : "addition",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 11,
"InstName" : "f0",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 12,
"InstName" : "f1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 13,
"InstName" : "f2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 14,
"InstName" : "f3",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/multiplier.v",
"InstLine" : 42,
"InstName" : "add1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"ModuleLine" : 1,
"ModuleName" : "addition",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 11,
"InstName" : "f0",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 12,
"InstName" : "f1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 13,
"InstName" : "f2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 14,
"InstName" : "f3",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/multiplier.v",
"InstLine" : 58,
"InstName" : "add2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"ModuleLine" : 1,
"ModuleName" : "addition",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 11,
"InstName" : "f0",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 12,
"InstName" : "f1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 13,
"InstName" : "f2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 14,
"InstName" : "f3",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
}
]
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
"InstLine" : 76,
"InstName" : "btod1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"ModuleLine" : 1,
"ModuleName" : "BinaryToBCD",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 14,
"InstName" : "d1t",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 23,
"InstName" : "d2u",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 32,
"InstName" : "d3v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 41,
"InstName" : "d4w",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 50,
"InstName" : "d5x",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 59,
"InstName" : "d6y",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 68,
"InstName" : "d7z",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
}
]
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
"InstLine" : 11,
"InstName" : "s1",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/selector.v",
"ModuleLine" : 1,
"ModuleName" : "selector"
}
]
}
]

73
gowin/bttn/impl/temp/rtl_parser_arg.json
View File

@ -1,73 +0,0 @@
{
"Device" : "GW2A-18C",
"Files" : [
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/logicUnit.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/multiplier.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/opCode.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/selector.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
"Type" : "verilog"
}
],
"IncludePath" : [
],
"LoopLimit" : 2000,
"ResultFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/impl/temp/rtl_parser.result",
"Top" : "",
"VerilogStd" : "verilog_2001",
"VhdlStd" : "vhdl_93"
}

0
gowin/bttn/impl/temp/style.css
View File

2191
gowin/bttn/src/bttn
View File

File diff suppressed because it is too large Load Diff

59
gowin/bttn/src/bttn.cst
View File

@ -1,59 +0,0 @@
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Physical Constraints file
//Tool Version: V1.9.9.03 Education (64-bit)
//Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18
//Device Version: C
//Created Time: Sat 01 18 21:56:09 2025
IO_LOC "Y[11]" B12;
IO_PORT "Y[11]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[10]" B13;
IO_PORT "Y[10]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[9]" B14;
IO_PORT "Y[9]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[8]" D14;
IO_PORT "Y[8]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[7]" J14;
IO_PORT "Y[7]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[6]" M14;
IO_PORT "Y[6]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[5]" T12;
IO_PORT "Y[5]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[4]" T11;
IO_PORT "Y[4]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[3]" P9;
IO_PORT "Y[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[2]" P8;
IO_PORT "Y[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[1]" T7;
IO_PORT "Y[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[0]" P6;
IO_PORT "Y[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "select[1]" A14;
IO_PORT "select[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "select[0]" A15;
IO_PORT "select[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[2]" E8;
IO_PORT "opCodeA[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[1]" T4;
IO_PORT "opCodeA[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[0]" T5;
IO_PORT "opCodeA[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "B[3]" N8;
IO_PORT "B[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[2]" N7;
IO_PORT "B[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[1]" D11;
IO_PORT "B[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[0]" B11;
IO_PORT "B[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[3]" L9;
IO_PORT "A[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[2]" E15;
IO_PORT "A[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[1]" N6;
IO_PORT "A[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[0]" A11;
IO_PORT "A[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;

13
gowin/bttn/src/bttn.v
View File

@ -1,13 +0,0 @@
module bttn (
input [3:0] A, B,
input [2:0] opCodeA,
input [1:0] select,
output [11:0] Y
);
wire wire1, wire2;
wire [11:0] selectY;
ALU a1(.A(A), .B(B), .opCodeA(opCodeA), .CarryIN(1'b0), .bcd(selectY), .CarryOUT(wire1), .overflow(wire2));
selector s1(.A(A), .B(B), .opCodeA(opCodeA), .select(select), .ALUY(selectY), .Y(Y));
endmodule

1103
gowin/bttn/src/bttn.vcd
View File

File diff suppressed because it is too large Load Diff

8
tangTest/bttn.cst → gowin/bttn/src/top.cst
View File

@ -5,7 +5,7 @@
//Part Number: GW2A-LV18PG256C8/I7 //Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18 //Device: GW2A-18
//Device Version: C //Device Version: C
//Created Time: Sat 01 18 21:56:09 2025 //Created Time: Mon 01 20 17:48:00 2025
IO_LOC "Y[11]" B12; IO_LOC "Y[11]" B12;
IO_PORT "Y[11]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8; IO_PORT "Y[11]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
@ -31,6 +31,12 @@ IO_LOC "Y[1]" T7;
IO_PORT "Y[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8; IO_PORT "Y[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[0]" P6; IO_LOC "Y[0]" P6;
IO_PORT "Y[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8; IO_PORT "Y[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[1]" L14;
IO_PORT "leds[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[0]" L16;
IO_PORT "leds[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Cin" E9;
IO_PORT "Cin" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "select[1]" A14; IO_LOC "select[1]" A14;
IO_PORT "select[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8; IO_PORT "select[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "select[0]" A15; IO_LOC "select[0]" A15;

19
gowin/bttn/src/top.v Normal file
View File

@ -0,0 +1,19 @@
module top (
input [3:0] A, B,
input [2:0] opCodeA,
input [1:0] select,
input Cin,
output [1:0] leds,
output [11:0] Y
);
wire wire1, wire2;
wire [11:0] selectY;
ALU a1(.A(A), .B(B), .opCodeA(opCodeA), .CarryIN(Cin), .bcd(selectY), .CarryOUT(wire2), .overflow(wire1)); //ALU module
selector s1(.A(A), .B(B), .opCodeA(opCodeA), .select(select), .ALUY(selectY), .Y(Y)); // selector for 7 segment
assign leds[0] = ~wire1; //overflow led
assign leds[1] = ~wire2; //CarryOut/BorrowOut led
endmodule

6
gowin/bttn/src/bttnTB.v → gowin/bttn/src/topTB.v
View File

@ -1,11 +1,11 @@
module bttnTB(); module topTB();
reg [3:0] A,B; reg [3:0] A,B;
reg [2:0] opCodeA; reg [2:0] opCodeA;
reg [1:0] select; reg [1:0] select;
wire [11:0] Y; wire [11:0] Y;
bttn uut ( top uut (
.A(A), .A(A),
.B(B), .B(B),
.opCodeA(opCodeA), .opCodeA(opCodeA),
@ -14,7 +14,7 @@ bttn uut (
); );
initial begin initial begin
$dumpfile("bttn.vcd"); $dumpfile("top.vcd");
$dumpvars; $dumpvars;
A = 4'b0001; B = 4'b0110; opCodeA = 3'b000; select = 2'b01; #5; A = 4'b0001; B = 4'b0110; opCodeA = 3'b000; select = 2'b01; #5;
$finish; $finish;

291
iverilog/tobb/lab4/bib3 Normal file
View File

@ -0,0 +1,291 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55ec90657360 .scope module, "bib3TB" "bib3TB" 2 1;
.timescale 0 0;
v0x55ec9066dea0_0 .var "A", 8 0;
v0x55ec9066df60_0 .net "Y", 3 0, v0x55ec9066dd60_0; 1 drivers
S_0x55ec906574f0 .scope module, "uut" "bib3" 2 6, 3 1 0, S_0x55ec90657360;
.timescale 0 0;
.port_info 0 /INPUT 9 "buyruk";
.port_info 1 /OUTPUT 4 "sonuc";
v0x55ec90618c00_0 .var/i "a", 31 0;
v0x55ec9066d8d0_0 .var/i "b", 31 0;
v0x55ec9066d9b0_0 .net "buyruk", 8 0, v0x55ec9066dea0_0; 1 drivers
v0x55ec9066da70_0 .var/i "c", 31 0;
v0x55ec9066db50_0 .var/i "count", 31 0;
v0x55ec9066dc80_0 .var/i "i", 31 0;
v0x55ec9066dd60_0 .var "sonuc", 3 0;
E_0x55ec9064fc40 .event edge, v0x55ec9066d9b0_0;
.scope S_0x55ec906574f0;
T_0 ;
%wait E_0x55ec9064fc40;
%load/vec4 v0x55ec9066d9b0_0;
%parti/s 3, 6, 4;
%dup/vec4;
%pushi/vec4 0, 0, 3;
%cmp/u;
%jmp/1 T_0.1, 6;
%dup/vec4;
%pushi/vec4 1, 0, 3;
%cmp/u;
%jmp/1 T_0.2, 6;
%dup/vec4;
%pushi/vec4 2, 0, 3;
%cmp/u;
%jmp/1 T_0.3, 6;
%dup/vec4;
%pushi/vec4 3, 0, 3;
%cmp/u;
%jmp/1 T_0.4, 6;
%dup/vec4;
%pushi/vec4 4, 0, 3;
%cmp/u;
%jmp/1 T_0.5, 6;
%dup/vec4;
%pushi/vec4 5, 0, 3;
%cmp/u;
%jmp/1 T_0.6, 6;
%dup/vec4;
%pushi/vec4 6, 0, 3;
%cmp/u;
%jmp/1 T_0.7, 6;
%dup/vec4;
%pushi/vec4 7, 0, 3;
%cmp/u;
%jmp/1 T_0.8, 6;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
%jmp T_0.9;
T_0.1 ;
%load/vec4 v0x55ec9066d9b0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55ec9066d9b0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%add;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
%jmp T_0.9;
T_0.2 ;
%load/vec4 v0x55ec9066d9b0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55ec9066d9b0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%sub;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
%jmp T_0.9;
T_0.3 ;
%load/vec4 v0x55ec9066d9b0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55ec9066d9b0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%and;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
%jmp T_0.9;
T_0.4 ;
%load/vec4 v0x55ec9066d9b0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55ec9066d9b0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%or;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
%jmp T_0.9;
T_0.5 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55ec9066dc80_0, 0, 32;
T_0.10 ;
%load/vec4 v0x55ec9066dc80_0;
%cmpi/s 4, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.11, 5;
%load/vec4 v0x55ec9066d9b0_0;
%load/vec4 v0x55ec9066dc80_0;
%part/s 1;
%load/vec4 v0x55ec9066d9b0_0;
%load/vec4 v0x55ec9066dc80_0;
%addi 1, 0, 32;
%part/s 1;
%cmp/e;
%jmp/0xz T_0.12, 4;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
%jmp T_0.13;
T_0.12 ;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
T_0.13 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55ec9066dc80_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55ec9066dc80_0, 0, 32;
%jmp T_0.10;
T_0.11 ;
%jmp T_0.9;
T_0.6 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55ec90618c00_0, 0, 32;
T_0.14 ;
%load/vec4 v0x55ec90618c00_0;
%cmpi/s 5, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.15, 5;
%load/vec4 v0x55ec9066d9b0_0;
%load/vec4 v0x55ec90618c00_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.16, 4;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
%jmp T_0.17;
T_0.16 ;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
T_0.17 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55ec90618c00_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55ec90618c00_0, 0, 32;
%jmp T_0.14;
T_0.15 ;
%jmp T_0.9;
T_0.7 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55ec9066db50_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55ec9066d8d0_0, 0, 32;
T_0.18 ;
%load/vec4 v0x55ec9066d8d0_0;
%cmpi/s 5, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.19, 5;
%load/vec4 v0x55ec9066d9b0_0;
%load/vec4 v0x55ec9066d8d0_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.20, 4;
%load/vec4 v0x55ec9066db50_0;
%addi 1, 0, 32;
%store/vec4 v0x55ec9066db50_0, 0, 32;
T_0.20 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55ec9066d8d0_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55ec9066d8d0_0, 0, 32;
%jmp T_0.18;
T_0.19 ;
%load/vec4 v0x55ec9066db50_0;
%pushi/vec4 2, 0, 32;
%mod/s;
%cmpi/e 0, 0, 32;
%jmp/0xz T_0.22, 4;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
%jmp T_0.23;
T_0.22 ;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
T_0.23 ;
%jmp T_0.9;
T_0.8 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55ec9066db50_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55ec9066da70_0, 0, 32;
T_0.24 ;
%load/vec4 v0x55ec9066da70_0;
%cmpi/s 5, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.25, 5;
%load/vec4 v0x55ec9066d9b0_0;
%load/vec4 v0x55ec9066da70_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.26, 4;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55ec9066db50_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55ec9066db50_0, 0, 32;
T_0.26 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55ec9066da70_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55ec9066da70_0, 0, 32;
%jmp T_0.24;
T_0.25 ;
%load/vec4 v0x55ec9066db50_0;
%pushi/vec4 2, 0, 32;
%mod/s;
%cmpi/e 0, 0, 32;
%jmp/0xz T_0.28, 4;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
%jmp T_0.29;
T_0.28 ;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x55ec9066dd60_0, 0, 4;
T_0.29 ;
%jmp T_0.9;
T_0.9 ;
%pop/vec4 1;
%jmp T_0;
.thread T_0, $push;
.scope S_0x55ec90657360;
T_1 ;
%vpi_call 2 12 "$dumpfile", "bib3.vcd" {0 0 0};
%vpi_call 2 13 "$dumpvars" {0 0 0};
%pushi/vec4 9, 0, 9;
%store/vec4 v0x55ec9066dea0_0, 0, 9;
%delay 5, 0;
%pushi/vec4 97, 0, 9;
%store/vec4 v0x55ec9066dea0_0, 0, 9;
%delay 5, 0;
%pushi/vec4 165, 0, 9;
%store/vec4 v0x55ec9066dea0_0, 0, 9;
%delay 5, 0;
%pushi/vec4 227, 0, 9;
%store/vec4 v0x55ec9066dea0_0, 0, 9;
%delay 5, 0;
%pushi/vec4 319, 0, 9;
%store/vec4 v0x55ec9066dea0_0, 0, 9;
%delay 5, 0;
%pushi/vec4 289, 0, 9;
%store/vec4 v0x55ec9066dea0_0, 0, 9;
%delay 5, 0;
%pushi/vec4 353, 0, 9;
%store/vec4 v0x55ec9066dea0_0, 0, 9;
%delay 5, 0;
%pushi/vec4 417, 0, 9;
%store/vec4 v0x55ec9066dea0_0, 0, 9;
%delay 5, 0;
%pushi/vec4 481, 0, 9;
%store/vec4 v0x55ec9066dea0_0, 0, 9;
%delay 5, 0;
%end;
.thread T_1;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"bib3TB.v";
"bib3.v";

49
iverilog/tobb/lab4/bib3.v Normal file
View File

@ -0,0 +1,49 @@
module bib3 (
input [8:0] buyruk,
output reg [3:0] sonuc
);
integer i, a, b, c, count;
always@(buyruk) begin
case (buyruk[8:6])
default: sonuc = 4'b0000;
3'b000: sonuc = buyruk[5:3] + buyruk[2:0];
3'b001: sonuc = buyruk[5:3] - buyruk[2:0];
3'b010: sonuc = buyruk[5:3] & buyruk[2:0];
3'b011: sonuc = buyruk[5:3] | buyruk[2:0];
3'b100: begin
for (i = 0; i <= 4; i++)
if (buyruk[i] == buyruk[i+1])
sonuc = 4'b1111;
else
sonuc = 4'b0000;
end
3'b101: for (a = 0; a <= 5; a++) begin
if (buyruk[a] == 1)
sonuc = 4'b1111;
else
sonuc = 4'b0000;
end
3'b110: begin
count = 0;
for (b = 0; b <= 5; b++) begin
if (buyruk[b] == 1)
count = count + 1;
end
if (count % 2 == 0)
sonuc = 4'b1111;
else
sonuc = 4'b0000;
end
3'b111: begin
count = 0;
for (c = 0; c <= 5; c++)
if (buyruk[c] == 1)
count++;
if (count % 2 == 0)
sonuc = 4'b0000;
else
sonuc = 4'b1111;
end
endcase
end
endmodule

81
iverilog/tobb/lab4/bib3.vcd Normal file
View File

@ -0,0 +1,81 @@
$date
Sat Jan 25 01:26:43 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module bib3TB $end
$var wire 4 ! Y [3:0] $end
$var reg 9 " A [8:0] $end
$scope module uut $end
$var wire 9 # buyruk [8:0] $end
$var reg 4 $ sonuc [3:0] $end
$var integer 32 % a [31:0] $end
$var integer 32 & b [31:0] $end
$var integer 32 ' c [31:0] $end
$var integer 32 ( count [31:0] $end
$var integer 32 ) i [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
bx )
bx (
bx '
bx &
bx %
b10 $
b1001 #
b1001 "
b10 !
$end
#5
b11 !
b11 $
b1100001 "
b1100001 #
#10
b100 !
b100 $
b10100101 "
b10100101 #
#15
b111 !
b111 $
b11100011 "
b11100011 #
#20
b1111 !
b1111 $
b101 )
b100111111 "
b100111111 #
#25
b0 !
b0 $
b101 )
b100100001 "
b100100001 #
#30
b1111 !
b1111 $
b110 %
b101100001 "
b101100001 #
#35
b110 &
b10 (
b110100001 "
b110100001 #
#40
b0 !
b0 $
b110 '
b10 (
b111100001 "
b111100001 #
#45

25
iverilog/tobb/lab4/bib3TB.v Normal file
View File

@ -0,0 +1,25 @@
module bib3TB();
reg [8:0] A;
wire [3:0] Y;
bib3 uut (
.buyruk(A),
.sonuc(Y)
);
initial begin
$dumpfile("bib3.vcd");
$dumpvars;
A = 9'b000_001_001; #5;
A = 9'b001_100_001; #5;
A = 9'b010_100_101; #5;
A = 9'b011_100_011; #5;
A = 9'b100_111_111; #5;
A = 9'b100_100_001; #5;
A = 9'b101_100_001; #5;
A = 9'b110_100_001; #5;
A = 9'b111_100_001; #5;
end
endmodule

117
iverilog/tobb/lab4/sube3soru2 Normal file
View File

@ -0,0 +1,117 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55a0b73b0f40 .scope module, "sube3soru2TB" "sube3soru2TB" 2 1;
.timescale 0 0;
v0x55a0b73c4170_0 .var "A", 9 0;
v0x55a0b73c4250_0 .var "B", 5 0;
v0x55a0b73c4320_0 .net "D", 4 0, v0x55a0b73c3b30_0; 1 drivers
v0x55a0b73c4420_0 .net "l1", 4 0, v0x55a0b73c3d00_0; 1 drivers
v0x55a0b73c44f0_0 .net "l2", 4 0, v0x55a0b73c3e30_0; 1 drivers
S_0x55a0b73b10d0 .scope module, "uut" "sube3soru2" 2 7, 3 1 0, S_0x55a0b73b0f40;
.timescale 0 0;
.port_info 0 /INPUT 10 "A";
.port_info 1 /INPUT 6 "B";
.port_info 2 /OUTPUT 5 "D";
.port_info 3 /OUTPUT 5 "l1";
.port_info 4 /OUTPUT 5 "l2";
v0x55a0b7376c00_0 .net "A", 9 0, v0x55a0b73c4170_0; 1 drivers
v0x55a0b73c3a50_0 .net "B", 5 0, v0x55a0b73c4250_0; 1 drivers
v0x55a0b73c3b30_0 .var "D", 4 0;
v0x55a0b73c3c20_0 .var/i "hunderedR", 31 0;
v0x55a0b73c3d00_0 .var "l1", 4 0;
v0x55a0b73c3e30_0 .var "l2", 4 0;
v0x55a0b73c3f10_0 .var/i "tempD", 31 0;
v0x55a0b73c3ff0_0 .var/i "tempO", 31 0;
E_0x55a0b73ae360 .event edge, v0x55a0b73c3a50_0, v0x55a0b7376c00_0;
.scope S_0x55a0b73b10d0;
T_0 ;
%wait E_0x55a0b73ae360;
%load/vec4 v0x55a0b7376c00_0;
%parti/s 8, 2, 3;
%pad/u 32;
%muli 100, 0, 32;
%store/vec4 v0x55a0b73c3c20_0, 0, 32;
%load/vec4 v0x55a0b7376c00_0;
%parti/s 2, 0, 2;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_0.0, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_0.1, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_0.2, 6;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55a0b73c3f10_0, 0, 32;
%jmp T_0.4;
T_0.0 ;
%pushi/vec4 25, 0, 32;
%store/vec4 v0x55a0b73c3f10_0, 0, 32;
%jmp T_0.4;
T_0.1 ;
%pushi/vec4 50, 0, 32;
%store/vec4 v0x55a0b73c3f10_0, 0, 32;
%jmp T_0.4;
T_0.2 ;
%pushi/vec4 75, 0, 32;
%store/vec4 v0x55a0b73c3f10_0, 0, 32;
%jmp T_0.4;
T_0.4 ;
%pop/vec4 1;
%load/vec4 v0x55a0b73c3c20_0;
%load/vec4 v0x55a0b73c3f10_0;
%add;
%store/vec4 v0x55a0b73c3ff0_0, 0, 32;
%load/vec4 v0x55a0b73c3ff0_0;
%load/vec4 v0x55a0b73c3a50_0;
%pad/u 32;
%div;
%store/vec4 v0x55a0b73c3ff0_0, 0, 32;
%load/vec4 v0x55a0b73c3ff0_0;
%pushi/vec4 100, 0, 32;
%div/s;
%pad/s 5;
%store/vec4 v0x55a0b73c3b30_0, 0, 5;
%load/vec4 v0x55a0b73c3ff0_0;
%pushi/vec4 100, 0, 32;
%mod/s;
%pushi/vec4 10, 0, 32;
%div/s;
%pad/s 5;
%store/vec4 v0x55a0b73c3d00_0, 0, 5;
%load/vec4 v0x55a0b73c3ff0_0;
%pushi/vec4 10, 0, 32;
%mod/s;
%pad/s 5;
%store/vec4 v0x55a0b73c3e30_0, 0, 5;
%jmp T_0;
.thread T_0, $push;
.scope S_0x55a0b73b0f40;
T_1 ;
%vpi_call 2 16 "$dumpfile", "sube3soru2.vcd" {0 0 0};
%vpi_call 2 17 "$dumpvars" {0 0 0};
%pushi/vec4 25, 0, 10;
%store/vec4 v0x55a0b73c4170_0, 0, 10;
%pushi/vec4 3, 0, 6;
%store/vec4 v0x55a0b73c4250_0, 0, 6;
%delay 5, 0;
%vpi_call 2 19 "$finish" {0 0 0};
%end;
.thread T_1;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"sube3soru2TB.v";
"sube3soru2.v";

24
iverilog/tobb/lab4/sube3soru2.v Normal file
View File

@ -0,0 +1,24 @@
module sube3soru2 (
input [9:0] A,
input [5:0] B,
output reg [4:0] D,l1,l2
);
integer tempD, tempO, hunderedR;
always@(A or B) begin
hunderedR = A[9:2] * 100;
case(A[1:0])
2'b01: tempD = 25;
2'b10: tempD = 50;
2'b11: tempD = 75;
default: tempD = 00;
endcase
tempO = hunderedR + tempD;
tempO = tempO / B;
D = tempO / 100;
l1 = (tempO%100)/10;
l2 = tempO%10;
end
endmodule

44
iverilog/tobb/lab4/sube3soru2.vcd Normal file
View File

@ -0,0 +1,44 @@
$date
Sat Jan 25 03:14:14 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module sube3soru2TB $end
$var wire 5 ! l2 [4:0] $end
$var wire 5 " l1 [4:0] $end
$var wire 5 # D [4:0] $end
$var reg 10 $ A [9:0] $end
$var reg 6 % B [5:0] $end
$scope module uut $end
$var wire 10 & A [9:0] $end
$var wire 6 ' B [5:0] $end
$var reg 5 ( D [4:0] $end
$var reg 5 ) l1 [4:0] $end
$var reg 5 * l2 [4:0] $end
$var integer 32 + hunderedR [31:0] $end
$var integer 32 , tempD [31:0] $end
$var integer 32 - tempO [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b11010000 -
b11001 ,
b1001011000 +
b1000 *
b0 )
b10 (
b11 '
b11001 &
b11 %
b11001 $
b10 #
b0 "
b1000 !
$end
#5

22
iverilog/tobb/lab4/sube3soru2TB.v Normal file
View File

@ -0,0 +1,22 @@
module sube3soru2TB();
reg [9:0] A;
reg [5:0] B;
wire [4:0] D,l1,l2;
sube3soru2 uut (
.A(A),
.B(B),
.D(D),
.l1(l1),
.l2(l2)
);
initial begin
$dumpfile("sube3soru2.vcd");
$dumpvars;
A = 10'b0000011001; B = 6'b000011; #5;
$finish;
end
endmodule

193
iverilog/tobb/lab5/ayarliSayac Normal file
View File

@ -0,0 +1,193 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55b4b9d0fd50 .scope module, "ayarliSayacTB" "ayarliSayacTB" 2 1;
.timescale 0 0;
v0x55b4b9d66830_0 .var "clk", 0 0;
v0x55b4b9d668f0_0 .var "en", 0 0;
v0x55b4b9d669c0_0 .var "rst", 0 0;
v0x55b4b9d66ac0_0 .net "sayac", 5 0, v0x55b4b9d664f0_0; 1 drivers
v0x55b4b9d66b90_0 .var "sayma_miktari", 2 0;
v0x55b4b9d66c80_0 .var "sayma_yonu", 0 0;
S_0x55b4b9d0fee0 .scope module, "uut" "sayac" 2 8, 3 1 0, S_0x55b4b9d0fd50;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst";
.port_info 2 /INPUT 1 "en";
.port_info 3 /INPUT 3 "sayma_miktari";
.port_info 4 /INPUT 1 "sayma_yonu";
.port_info 5 /OUTPUT 6 "sayac";
v0x55b4b9d4e5b0_0 .net "clk", 0 0, v0x55b4b9d66830_0; 1 drivers
v0x55b4b9d66180_0 .var "clk_divider", 1 0;
v0x55b4b9d66260_0 .net "en", 0 0, v0x55b4b9d668f0_0; 1 drivers
v0x55b4b9d66300_0 .var "miktar", 2 0;
v0x55b4b9d663e0_0 .net "rst", 0 0, v0x55b4b9d669c0_0; 1 drivers
v0x55b4b9d664f0_0 .var "sayac", 5 0;
v0x55b4b9d665d0_0 .net "sayma_miktari", 2 0, v0x55b4b9d66b90_0; 1 drivers
v0x55b4b9d666b0_0 .net "sayma_yonu", 0 0, v0x55b4b9d66c80_0; 1 drivers
E_0x55b4b9d4f1d0/0 .event negedge, v0x55b4b9d4e5b0_0;
E_0x55b4b9d4f1d0/1 .event posedge, v0x55b4b9d663e0_0;
E_0x55b4b9d4f1d0 .event/or E_0x55b4b9d4f1d0/0, E_0x55b4b9d4f1d0/1;
.scope S_0x55b4b9d0fee0;
T_0 ;
%pushi/vec4 0, 0, 6;
%store/vec4 v0x55b4b9d664f0_0, 0, 6;
%pushi/vec4 0, 0, 2;
%store/vec4 v0x55b4b9d66180_0, 0, 2;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55b4b9d66300_0, 0, 3;
%end;
.thread T_0;
.scope S_0x55b4b9d0fee0;
T_1 ;
%wait E_0x55b4b9d4f1d0;
%load/vec4 v0x55b4b9d663e0_0;
%flag_set/vec4 8;
%jmp/0xz T_1.0, 8;
%pushi/vec4 0, 0, 6;
%assign/vec4 v0x55b4b9d664f0_0, 0;
%pushi/vec4 0, 0, 2;
%assign/vec4 v0x55b4b9d66180_0, 0;
%pushi/vec4 0, 0, 3;
%assign/vec4 v0x55b4b9d66300_0, 0;
%jmp T_1.1;
T_1.0 ;
%load/vec4 v0x55b4b9d66180_0;
%addi 1, 0, 2;
%assign/vec4 v0x55b4b9d66180_0, 0;
%load/vec4 v0x55b4b9d66180_0;
%cmpi/e 3, 0, 2;
%jmp/0xz T_1.2, 4;
%pushi/vec4 0, 0, 2;
%assign/vec4 v0x55b4b9d66180_0, 0;
%load/vec4 v0x55b4b9d66260_0;
%flag_set/vec4 8;
%jmp/0xz T_1.4, 8;
%load/vec4 v0x55b4b9d665d0_0;
%assign/vec4 v0x55b4b9d66300_0, 0;
T_1.4 ;
%load/vec4 v0x55b4b9d666b0_0;
%flag_set/vec4 8;
%jmp/0xz T_1.6, 8;
%load/vec4 v0x55b4b9d664f0_0;
%load/vec4 v0x55b4b9d66300_0;
%pad/u 6;
%add;
%cmpi/u 63, 0, 6;
%flag_inv 5; GE is !LT
%jmp/0xz T_1.8, 5;
%pushi/vec4 63, 0, 6;
%assign/vec4 v0x55b4b9d664f0_0, 0;
%jmp T_1.9;
T_1.8 ;
%load/vec4 v0x55b4b9d664f0_0;
%load/vec4 v0x55b4b9d66300_0;
%pad/u 6;
%add;
%assign/vec4 v0x55b4b9d664f0_0, 0;
T_1.9 ;
%jmp T_1.7;
T_1.6 ;
%load/vec4 v0x55b4b9d664f0_0;
%load/vec4 v0x55b4b9d66300_0;
%pad/u 6;
%cmp/u;
%flag_or 5, 4;
%jmp/0xz T_1.10, 5;
%pushi/vec4 0, 0, 6;
%assign/vec4 v0x55b4b9d664f0_0, 0;
%jmp T_1.11;
T_1.10 ;
%load/vec4 v0x55b4b9d664f0_0;
%load/vec4 v0x55b4b9d66300_0;
%pad/u 6;
%sub;
%assign/vec4 v0x55b4b9d664f0_0, 0;
T_1.11 ;
T_1.7 ;
T_1.2 ;
T_1.1 ;
%jmp T_1;
.thread T_1;
.scope S_0x55b4b9d0fd50;
T_2 ;
%load/vec4 v0x55b4b9d66830_0;
%inv;
%store/vec4 v0x55b4b9d66830_0, 0, 1;
%delay 1, 0;
%jmp T_2;
.thread T_2;
.scope S_0x55b4b9d0fd50;
T_3 ;
%vpi_call 2 22 "$dumpfile", "ayarliSayac.vcd" {0 0 0};
%vpi_call 2 23 "$dumpvars" {0 0 0};
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66830_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55b4b9d669c0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d668f0_0, 0, 1;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b4b9d66b90_0, 0, 3;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66c80_0, 0, 1;
%delay 32, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66830_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55b4b9d669c0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d668f0_0, 0, 1;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b4b9d66b90_0, 0, 3;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66c80_0, 0, 1;
%delay 8, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66830_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55b4b9d669c0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d668f0_0, 0, 1;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b4b9d66b90_0, 0, 3;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66c80_0, 0, 1;
%delay 64, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66830_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55b4b9d669c0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d668f0_0, 0, 1;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b4b9d66b90_0, 0, 3;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66c80_0, 0, 1;
%delay 16, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66830_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d669c0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d668f0_0, 0, 1;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x55b4b9d66b90_0, 0, 3;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66c80_0, 0, 1;
%delay 8, 0;
%vpi_call 2 29 "$finish" {0 0 0};
%end;
.thread T_3;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"ayarliSayacTB.v";
"sayac.v";

43
iverilog/tobb/lab5/ayarliSayac.v Normal file
View File

@ -0,0 +1,43 @@
module ayarliSayac (
input clk, rst, en,
input [2:0] sayma_miktari,
input sayma_yonu,
output reg [5:0] sayac
);
reg [2:0] miktar;
reg [1:0] clk_divider;
initial begin
sayac = 6'b0000_00;
miktar = 3'b001;
clk_divider = 2'b00;
end
always @(negedge clk or posedge rst) begin
if (rst) begin
sayac <= 6'b0000_00;
clk_divider <= 2'b00;
end else begin
clk_divider <= clk_divider + 1;
end
if (clk_divider == 2'b11) begin
if (en) begin
miktar = sayma_miktari;
if (sayma_yonu == 1) begin
if (sayac + miktar >= 6'b1111_11) begin
sayac <= 6'b1111_11;
end else begin
sayac <= miktar + sayac;
end
end else begin
if (sayac - miktar <= 6'b0000_00) begin
sayac <= 6'b0000_00;
end else begin
sayac <= sayac - miktar;
end
end
end
end
end
endmodule

393
iverilog/tobb/lab5/ayarliSayac.vcd Normal file
View File

@ -0,0 +1,393 @@
$date
Sun Jan 26 04:55:11 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module ayarliSayacTB $end
$var wire 6 ! sayac [5:0] $end
$var reg 1 " clk $end
$var reg 1 # en $end
$var reg 1 $ rst $end
$var reg 3 % sayma_miktari [2:0] $end
$var reg 1 & sayma_yonu $end
$scope module uut $end
$var wire 1 " clk $end
$var wire 1 # en $end
$var wire 1 $ rst $end
$var wire 3 ' sayma_miktari [2:0] $end
$var wire 1 & sayma_yonu $end
$var reg 2 ( clk_divider [1:0] $end
$var reg 3 ) miktar [2:0] $end
$var reg 6 * sayac [5:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 *
b0 )
b0 (
b111 '
1&
b111 %
0$
1#
1"
b0 !
$end
#1
b1 (
0"
#2
1"
#3
b10 (
0"
#4
1"
#5
b11 (
0"
#6
1"
#7
b111 )
b0 (
0"
#8
1"
#9
b1 (
0"
#10
1"
#11
b10 (
0"
#12
1"
#13
b11 (
0"
#14
1"
#15
b111 !
b111 *
b0 (
0"
#16
1"
#17
b1 (
0"
#18
1"
#19
b10 (
0"
#20
1"
#21
b11 (
0"
#22
1"
#23
b1110 !
b1110 *
b0 (
0"
#24
1"
#25
b1 (
0"
#26
1"
#27
b10 (
0"
#28
1"
#29
b11 (
0"
#30
1"
#31
b10101 !
b10101 *
b0 (
0"
#32
b1 (
0"
#33
1"
#34
b10 (
0"
#35
1"
#36
b11 (
0"
#37
1"
#38
b11100 !
b11100 *
b0 (
0"
#39
1"
#40
b1 (
0"
#41
1"
#42
b10 (
0"
#43
1"
#44
b11 (
0"
#45
1"
#46
b100011 !
b100011 *
b0 (
0"
#47
1"
#48
b1 (
0"
#49
1"
#50
b10 (
0"
#51
1"
#52
b11 (
0"
#53
1"
#54
b101010 !
b101010 *
b0 (
0"
#55
1"
#56
b1 (
0"
#57
1"
#58
b10 (
0"
#59
1"
#60
b11 (
0"
#61
1"
#62
b110001 !
b110001 *
b0 (
0"
#63
1"
#64
b1 (
0"
#65
1"
#66
b10 (
0"
#67
1"
#68
b11 (
0"
#69
1"
#70
b111000 !
b#70
00 *
b0 (
0"
#71
1"
#72
b1 (
0"
#73
1"
#74
b10 (
0"
#75
1"
#76
b11 (
0"
#77
1"
#78
b111111 !
b111111 *
b0 (
0"
#79
1"
#80
b1 (
0"
#81
1"
#82
b10 (
0"
#83
1"
#84
b11 (
0"
#85
1"
#86
b110 !
b110 *
b0 (
0"
#87
1"
#88
b1 (
0"
#89
1"
#90
b10 (
0"
#91
1"
#92
b11 (
0"
#93
1"
#94
b1101 !
b1101 *
b0 (
0"
#95
1"
#96
b1 (
0"
#97
1"
#98
b10 (
0"
#99
1"
#100
b11 (
0"
#101
1"
#102
b10100 !
b10100 *
b0 (
0"
#103
1"
#104
b1 (
0"
#105
1"
#106
b10 (
0"
#107
1"
#108
b11 (
0"
#109
1"
#110
b11011 !
b11011 *
b0 (
0"
#111
1"
#112
b1 (
0"
#113
1"
#114
b10 (
0"
#115
1"
#116
b11 (
0"
#117
1"
#118
b100010 !
b100010 *
b0 (
0"
#119
1"
#120
b0 )
b0 !
b0 *
0"
b10 %
b10 '
1$
#121
1"
#122
0"
#123
1"
#124
0"
#125
1"
#126
0"
#127
1"
#128
0"

32
iverilog/tobb/lab5/ayarliSayacTB.v Normal file
View File

@ -0,0 +1,32 @@
module ayarliSayacTB();
reg clk, rst, en;
reg [2:0] sayma_miktari;
reg sayma_yonu;
wire [5:0] sayac;
sayac uut (
.clk(clk),
.rst(rst),
.en(en),
.sayma_miktari(sayma_miktari),
.sayma_yonu(sayma_yonu),
.sayac(sayac)
);
always begin
clk = ~clk; #1;
end
initial begin
$dumpfile("ayarliSayac.vcd");
$dumpvars;
clk = 1; rst = 0; en = 1; sayma_miktari = 3'b111; sayma_yonu = 1'b1; #32;
clk = 1; rst = 0; en = 1; sayma_miktari = 3'b111; sayma_yonu = 1'b1; #8;
clk = 1; rst = 0; en = 1; sayma_miktari = 3'b111; sayma_yonu = 1'b1; #64;
clk = 1; rst = 0; en = 1; sayma_miktari = 3'b111; sayma_yonu = 1'b1; #16;
clk = 1; rst = 1; en = 1; sayma_miktari = 3'b010; sayma_yonu = 1'b1; #8;
$finish;
end
endmodule

101
iverilog/tobb/lab5/knightRider Normal file
View File

@ -0,0 +1,101 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55c07fb12c40 .scope module, "knightRiderTB" "knightRiderTB" 2 1;
.timescale 0 0;
v0x55c07fb24010_0 .var "clk", 0 0;
v0x55c07fb240e0_0 .net "leds", 7 0, v0x55c07fb23ef0_0; 1 drivers
S_0x55c07fb12dd0 .scope module, "uut" "knightRider" 2 6, 3 1 0, S_0x55c07fb12c40;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /OUTPUT 8 "leds";
v0x55c07fad87f0_0 .net "clk", 0 0, v0x55c07fb24010_0; 1 drivers
v0x55c07fad8c00_0 .var "direction", 0 0;
v0x55c07fb23ef0_0 .var "leds", 7 0;
E_0x55c07fad7810 .event posedge, v0x55c07fad87f0_0;
.scope S_0x55c07fb12dd0;
T_0 ;
%pushi/vec4 7, 0, 8;
%store/vec4 v0x55c07fb23ef0_0, 0, 8;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55c07fad8c00_0, 0, 1;
%end;
.thread T_0;
.scope S_0x55c07fb12dd0;
T_1 ;
%wait E_0x55c07fad7810;
%load/vec4 v0x55c07fad8c00_0;
%pad/u 32;
%cmpi/e 0, 0, 32;
%jmp/0xz T_1.0, 4;
%load/vec4 v0x55c07fb23ef0_0;
%cmpi/e 224, 0, 8;
%jmp/0xz T_1.2, 4;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55c07fad8c00_0, 0;
%load/vec4 v0x55c07fb23ef0_0;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%shiftr 4;
%assign/vec4 v0x55c07fb23ef0_0, 0;
%jmp T_1.3;
T_1.2 ;
%load/vec4 v0x55c07fb23ef0_0;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%shiftl 4;
%assign/vec4 v0x55c07fb23ef0_0, 0;
T_1.3 ;
%jmp T_1.1;
T_1.0 ;
%load/vec4 v0x55c07fb23ef0_0;
%cmpi/e 7, 0, 8;
%jmp/0xz T_1.4, 4;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x55c07fad8c00_0, 0;
%load/vec4 v0x55c07fb23ef0_0;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%shiftl 4;
%assign/vec4 v0x55c07fb23ef0_0, 0;
%jmp T_1.5;
T_1.4 ;
%load/vec4 v0x55c07fb23ef0_0;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%shiftr 4;
%assign/vec4 v0x55c07fb23ef0_0, 0;
T_1.5 ;
T_1.1 ;
%jmp T_1;
.thread T_1;
.scope S_0x55c07fb12c40;
T_2 ;
%load/vec4 v0x55c07fb24010_0;
%inv;
%store/vec4 v0x55c07fb24010_0, 0, 1;
%delay 2, 0;
%jmp T_2;
.thread T_2;
.scope S_0x55c07fb12c40;
T_3 ;
%vpi_call 2 16 "$dumpfile", "knightRider.vcd" {0 0 0};
%vpi_call 2 17 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55c07fb24010_0, 0, 1;
%delay 50, 0;
%vpi_call 2 19 "$finish" {0 0 0};
%end;
.thread T_3;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"knightRiderTB.v";
"knightRider.v";

31
iverilog/tobb/lab5/knightRider.v Normal file
View File

@ -0,0 +1,31 @@
module knightRider (
input clk,
output reg [7:0] leds
);
reg direction;
initial begin
leds = 8'b0000_0111;
direction = 1'b0; // 0 left to right
end
always@(posedge clk) begin
if (direction == 0) begin
if (leds == 8'b1110_0000) begin
direction <= 1;
leds <= leds >> 1;
end else begin
leds <= leds << 1;
end
end else begin
if (leds == 8'b0000_0111) begin
direction <= 0;
leds <= leds << 1;
end else begin
leds <= leds >> 1;
end
end
end
endmodule

104
iverilog/tobb/lab5/knightRider.vcd Normal file
View File

@ -0,0 +1,104 @@
$date
Sat Jan 25 05:37:22 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module knightRiderTB $end
$var wire 8 ! leds [7:0] $end
$var reg 1 " clk $end
$scope module uut $end
$var wire 1 " clk $end
$var reg 1 # direction $end
$var reg 8 $ leds [7:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b111 $
0#
0"
b111 !
$end
#2
b1110 !
b1110 $
1"
#4
0"
#6
b11100 !
b11100 $
1"
#8
0"
#10
b111000 !
b111000 $
1"
#12
0"
#14
b1110000 !
b1110000 $
1"
#16
0"
#18
b11100000 !
b11100000 $
1"
#20
0"
#22
b1110000 !
b1110000 $
1#
1"
#24
0"
#26
b111000 !
b111000 $
1"
#28
0"
#30
b11100 !
b11100 $
1"
#32
0"
#34
b1110 !
b1110 $
1"
#36
0"
#38
b111 !
b111 $
1"
#40
0"
#42
b1110 !
b1110 $
0#
1"
#44
0"
#46
b11100 !
b11100 $
1"
#48
0"
#50
b111000 !
b111000 $
1"

22
iverilog/tobb/lab5/knightRiderTB.v Normal file
View File

@ -0,0 +1,22 @@
module knightRiderTB();
reg clk;
wire [7:0] leds;
knightRider uut (
.clk(clk),
.leds(leds)
);
always begin
clk = ~clk; #2;
end
initial begin
$dumpfile("knightRider.vcd");
$dumpvars;
clk = 0; #50;
$finish;
end
endmodule

48
iverilog/tobb/lab5/sayac.v Normal file
View File

@ -0,0 +1,48 @@
module sayac (
input clk, rst, en,
input [2:0] sayma_miktari,
input sayma_yonu,
output reg [5:0] sayac
);
reg [1:0] clk_divider;
reg [2:0] miktar;
initial begin
sayac = 6'b0000_00;
miktar = 3'b001;
clk_divider = 2'b00;
end
always@(*) begin
miktar = sayma_miktari;
end
always@(negedge clk or posedge rst) begin
if (rst) begin
sayac <= 6'b0000_00;
clk_divider <= 2'b00;
end else begin
clk_divider <= clk_divider + 1;
end
if (clk_divider == 2'b11) begin
clk_divider <= 2'b00;
if (en) begin
if (sayma_miktari) begin
if (sayac + miktar >= 6'b1111_11) begin
sayac <= 6'b1111_11;
end else begin
sayac <= sayac + miktar;
end
end else begin
if (miktar >= sayac) begin
sayac <= 6'b0000_00;
end else begin
sayac <= sayac - miktar;
end
end
end
end
end
endmodule

177
iverilog/tobb/lab5/tetris Normal file
View File

@ -0,0 +1,177 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x56335d23e170 .scope module, "tetrisTB" "tetrisTB" 2 1;
.timescale 0 0;
v0x56335d253500_0 .net "bitti_mi", 0 0, v0x56335d200370_0; 1 drivers
v0x56335d2535c0_0 .net "cevrim", 3 0, v0x56335d200c00_0; 1 drivers
v0x56335d253690_0 .var "clk", 0 0;
v0x56335d253790_0 .var "p", 2 0;
v0x56335d253860_0 .net "yukseklik", 3 0, v0x56335d253090_0; 1 drivers
S_0x56335d23e300 .scope module, "uut" "tetris" 2 9, 3 1 0, S_0x56335d23e170;
.timescale 0 0;
.port_info 0 /INPUT 3 "parca";
.port_info 1 /INPUT 1 "clk";
.port_info 2 /OUTPUT 4 "yukseklik";
.port_info 3 /OUTPUT 1 "bitti_mi";
.port_info 4 /OUTPUT 4 "cevrim";
v0x56335d200370_0 .var "bitti_mi", 0 0;
v0x56335d200c00_0 .var "cevrim", 3 0;
v0x56335d252ee0_0 .net "clk", 0 0, v0x56335d253690_0; 1 drivers
v0x56335d252fb0_0 .net "parca", 2 0, v0x56335d253790_0; 1 drivers
v0x56335d253090_0 .var "yukseklik", 3 0;
v0x56335d2531c0_0 .var "yukseklik1", 3 0;
v0x56335d2532a0_0 .var "yukseklik2", 3 0;
v0x56335d253380_0 .var "yukseklik3", 3 0;
E_0x56335d238670 .event posedge, v0x56335d252ee0_0;
.scope S_0x56335d23e300;
T_0 ;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x56335d200c00_0, 0, 4;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56335d200370_0, 0, 1;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x56335d253090_0, 0, 4;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x56335d2531c0_0, 0, 4;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x56335d2532a0_0, 0, 4;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x56335d253380_0, 0, 4;
%end;
.thread T_0;
.scope S_0x56335d23e300;
T_1 ;
%wait E_0x56335d238670;
%load/vec4 v0x56335d200370_0;
%nor/r;
%flag_set/vec4 8;
%jmp/0xz T_1.0, 8;
%load/vec4 v0x56335d252fb0_0;
%parti/s 1, 0, 2;
%flag_set/vec4 8;
%jmp/0xz T_1.2, 8;
%load/vec4 v0x56335d2531c0_0;
%addi 1, 0, 4;
%assign/vec4 v0x56335d2531c0_0, 0;
T_1.2 ;
%load/vec4 v0x56335d252fb0_0;
%parti/s 1, 1, 2;
%flag_set/vec4 8;
%jmp/0xz T_1.4, 8;
%load/vec4 v0x56335d2532a0_0;
%addi 1, 0, 4;
%assign/vec4 v0x56335d2532a0_0, 0;
T_1.4 ;
%load/vec4 v0x56335d252fb0_0;
%parti/s 1, 2, 3;
%flag_set/vec4 8;
%jmp/0xz T_1.6, 8;
%load/vec4 v0x56335d253380_0;
%addi 1, 0, 4;
%assign/vec4 v0x56335d253380_0, 0;
T_1.6 ;
%load/vec4 v0x56335d200c00_0;
%addi 1, 0, 4;
%assign/vec4 v0x56335d200c00_0, 0;
%load/vec4 v0x56335d200c00_0;
%cmpi/e 15, 0, 4;
%jmp/0xz T_1.8, 4;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x56335d200370_0, 0;
T_1.8 ;
T_1.0 ;
%jmp T_1;
.thread T_1;
.scope S_0x56335d23e300;
T_2 ;
%wait E_0x56335d238670;
%load/vec4 v0x56335d200370_0;
%flag_set/vec4 8;
%jmp/0xz T_2.0, 8;
%load/vec4 v0x56335d2532a0_0;
%load/vec4 v0x56335d2531c0_0;
%cmp/u;
%flag_get/vec4 4;
%flag_get/vec4 5;
%or;
%load/vec4 v0x56335d253380_0;
%load/vec4 v0x56335d2531c0_0;
%cmp/u;
%flag_get/vec4 4;
%flag_get/vec4 5;
%or;
%and;
%flag_set/vec4 8;
%jmp/0xz T_2.2, 8;
%load/vec4 v0x56335d2531c0_0;
%assign/vec4 v0x56335d253090_0, 0;
%jmp T_2.3;
T_2.2 ;
%load/vec4 v0x56335d2531c0_0;
%load/vec4 v0x56335d2532a0_0;
%cmp/u;
%flag_get/vec4 4;
%flag_get/vec4 5;
%or;
%load/vec4 v0x56335d253380_0;
%load/vec4 v0x56335d2532a0_0;
%cmp/u;
%flag_get/vec4 4;
%flag_get/vec4 5;
%or;
%and;
%flag_set/vec4 8;
%jmp/0xz T_2.4, 8;
%load/vec4 v0x56335d2532a0_0;
%assign/vec4 v0x56335d253090_0, 0;
%jmp T_2.5;
T_2.4 ;
%load/vec4 v0x56335d253380_0;
%assign/vec4 v0x56335d253090_0, 0;
T_2.5 ;
T_2.3 ;
T_2.0 ;
%jmp T_2;
.thread T_2;
.scope S_0x56335d23e170;
T_3 ;
%load/vec4 v0x56335d253690_0;
%inv;
%store/vec4 v0x56335d253690_0, 0, 1;
%delay 1, 0;
%jmp T_3;
.thread T_3;
.scope S_0x56335d23e170;
T_4 ;
%vpi_call 2 22 "$dumpfile", "tetris.vcd" {0 0 0};
%vpi_call 2 23 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56335d253690_0, 0, 1;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x56335d253790_0, 0, 3;
%delay 2, 0;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x56335d253790_0, 0, 3;
%delay 2, 0;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x56335d253790_0, 0, 3;
%delay 2, 0;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x56335d253790_0, 0, 3;
%delay 30, 0;
%vpi_call 2 28 "$finish" {0 0 0};
%end;
.thread T_4;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"tetrisTB.v";
"tetris.v";

49
iverilog/tobb/lab5/tetris.v Normal file
View File

@ -0,0 +1,49 @@
module tetris (
input [2:0] parca,
input clk,
output reg [3:0] yukseklik,
output reg bitti_mi,
output reg [3:0] cevrim
);
reg [3:0] yukseklik1, yukseklik2, yukseklik3;
initial begin
cevrim = 4'd0;
bitti_mi = 1'b0;
yukseklik = 4'b0;
yukseklik1 = 4'd0;
yukseklik2 = 4'd0;
yukseklik3 = 4'd0;
end
always@(posedge clk) begin
if (!bitti_mi) begin
if (parca[0]) begin
yukseklik1 <= yukseklik1 + 1;
end if (parca[1]) begin
yukseklik2 <= yukseklik2 + 1;
end if (parca[2]) begin
yukseklik3 <= yukseklik3 + 1;
end
cevrim <= cevrim + 1;
if (cevrim == 4'd15) begin
bitti_mi <= 1'b1;
end
end
end
always@(posedge clk) begin //comperator
if (bitti_mi) begin
if (yukseklik1 >= yukseklik2 && yukseklik1 >= yukseklik3) begin
yukseklik <= yukseklik1;
end else if (yukseklik2 >= yukseklik1 && yukseklik2 >= yukseklik3) begin
yukseklik <= yukseklik2;
end else begin
yukseklik <= yukseklik3;
end
end
end
endmodule

158
iverilog/tobb/lab5/tetris.vcd Normal file
View File

@ -0,0 +1,158 @@
$date
Sun Jan 26 06:03:11 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module tetrisTB $end
$var wire 4 ! yukseklik [3:0] $end
$var wire 4 " cevrim [3:0] $end
$var wire 1 # bitti_mi $end
$var reg 1 $ clk $end
$var reg 3 % p [2:0] $end
$scope module uut $end
$var wire 1 $ clk $end
$var wire 3 & parca [2:0] $end
$var reg 1 # bitti_mi $end
$var reg 4 ' cevrim [3:0] $end
$var reg 4 ( yukseklik [3:0] $end
$var reg 4 ) yukseklik1 [3:0] $end
$var reg 4 * yukseklik2 [3:0] $end
$var reg 4 + yukseklik3 [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 +
b0 *
b0 )
b0 (
b0 '
b10 &
b10 %
0$
0#
b0 "
b0 !
$end
#1
b1 "
b1 '
b1 *
1$
#2
0$
b11 %
b11 &
#3
b10 "
b10 '
b10 *
b1 )
1$
#4
0$
b10 %
b10 &
#5
b11 "
b11 '
b11 *
1$
#6
0$
b0 %
b0 &
#7
b100 "
b100 '
1$
#8
0$
#9
b101 "
b101 '
1$
#10
0$
#11
b110 "
b110 '
1$
#12
0$
#13
b111 "
b111 '
1$
#14
0$
#15
b1000 "
b1000 '
1$
#16
0$
#17
b1001 "
b1001 '
1$
#18
0$
#19
b1010 "
b1010 '
1$
#20
0$
#21
b1011 "
b1011 '
1$
#22
0$
#23
b1100 "
b1100 '
1$
#24
0$
#25
b1101 "
b1101 '
1$
#26
0$
#27
b1110 "
b1110 '
1$
#28
0$
#29
b1111 "
b1111 '
1$
#30
0$
#31
1#
b0 "
b0 '
1$
#32
0$
#33
b11 !
b11 (
1$
#34
0$
#35
1$
#36
0$

31
iverilog/tobb/lab5/tetrisTB.v Normal file
View File

@ -0,0 +1,31 @@
module tetrisTB();
reg [2:0] p;
reg clk;
wire [3:0] yukseklik;
wire bitti_mi;
wire [3:0] cevrim;
tetris uut (
.parca(p),
.clk(clk),
.yukseklik(yukseklik),
.bitti_mi(bitti_mi),
.cevrim(cevrim)
);
always begin
clk = ~clk; #1;
end
initial begin
$dumpfile("tetris.vcd");
$dumpvars;
clk = 0; p = 3'b010; #2;
p = 3'b011; #2;
p = 3'b010; #2;
p = 3'b000; #30;
$finish;
end
endmodule

286
iverilog/tobb/lab6/bibp Normal file
View File

@ -0,0 +1,286 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55e76f51ca80 .scope module, "bibpTB" "bibpTB" 2 1;
.timescale 0 0;
P_0x55e76f51cc10 .param/l "N" 0 2 2, +C4<00000000000000000000000000000011>;
v0x55e76f534860_0 .var "A", 8 0;
v0x55e76f534920_0 .net "sonuc", 3 0, v0x55e76f534720_0; 1 drivers
S_0x55e76f51ccb0 .scope module, "uut" "bibp" 2 6, 3 1 0, S_0x55e76f51ca80;
.timescale 0 0;
.port_info 0 /INPUT 9 "buyruk";
.port_info 1 /OUTPUT 4 "sonuc";
P_0x55e76f51d420 .param/l "N" 0 3 1, +C4<00000000000000000000000000000011>;
v0x55e76f4d8cf0_0 .var/i "a", 31 0;
v0x55e76f534290_0 .var/i "b", 31 0;
v0x55e76f534370_0 .net "buyruk", 8 0, v0x55e76f534860_0; 1 drivers
v0x55e76f534430_0 .var/i "c", 31 0;
v0x55e76f534510_0 .var/i "count", 31 0;
v0x55e76f534640_0 .var/i "i", 31 0;
v0x55e76f534720_0 .var "sonuc", 3 0;
E_0x55e76f511f90 .event edge, v0x55e76f534370_0;
.scope S_0x55e76f51ccb0;
T_0 ;
%wait E_0x55e76f511f90;
%load/vec4 v0x55e76f534370_0;
%parti/s 3, 6, 4;
%dup/vec4;
%pushi/vec4 0, 0, 3;
%cmp/u;
%jmp/1 T_0.1, 6;
%dup/vec4;
%pushi/vec4 1, 0, 3;
%cmp/u;
%jmp/1 T_0.2, 6;
%dup/vec4;
%pushi/vec4 2, 0, 3;
%cmp/u;
%jmp/1 T_0.3, 6;
%dup/vec4;
%pushi/vec4 3, 0, 3;
%cmp/u;
%jmp/1 T_0.4, 6;
%dup/vec4;
%pushi/vec4 4, 0, 3;
%cmp/u;
%jmp/1 T_0.5, 6;
%dup/vec4;
%pushi/vec4 5, 0, 3;
%cmp/u;
%jmp/1 T_0.6, 6;
%dup/vec4;
%pushi/vec4 6, 0, 3;
%cmp/u;
%jmp/1 T_0.7, 6;
%dup/vec4;
%pushi/vec4 7, 0, 3;
%cmp/u;
%jmp/1 T_0.8, 6;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55e76f534720_0, 0, 4;
%jmp T_0.9;
T_0.1 ;
%load/vec4 v0x55e76f534370_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55e76f534370_0;
%parti/s 3, 0, 2;
%pad/u 4;
%add;
%store/vec4 v0x55e76f534720_0, 0, 4;
%jmp T_0.9;
T_0.2 ;
%load/vec4 v0x55e76f534370_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55e76f534370_0;
%parti/s 3, 0, 2;
%pad/u 4;
%sub;
%store/vec4 v0x55e76f534720_0, 0, 4;
%jmp T_0.9;
T_0.3 ;
%load/vec4 v0x55e76f534370_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55e76f534370_0;
%parti/s 3, 0, 2;
%pad/u 4;
%and;
%store/vec4 v0x55e76f534720_0, 0, 4;
%jmp T_0.9;
T_0.4 ;
%load/vec4 v0x55e76f534370_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55e76f534370_0;
%parti/s 3, 0, 2;
%pad/u 4;
%or;
%store/vec4 v0x55e76f534720_0, 0, 4;
%jmp T_0.9;
T_0.5 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55e76f534640_0, 0, 32;
T_0.10 ;
%load/vec4 v0x55e76f534640_0;
%cmpi/s 4, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.11, 5;
%load/vec4 v0x55e76f534370_0;
%load/vec4 v0x55e76f534640_0;
%part/s 1;
%load/vec4 v0x55e76f534370_0;
%load/vec4 v0x55e76f534640_0;
%addi 1, 0, 32;
%part/s 1;
%cmp/e;
%jmp/0xz T_0.12, 4;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x55e76f534720_0, 0, 4;
%jmp T_0.13;
T_0.12 ;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55e76f534720_0, 0, 4;
T_0.13 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55e76f534640_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55e76f534640_0, 0, 32;
%jmp T_0.10;
T_0.11 ;
%jmp T_0.9;
T_0.6 ;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55e76f534720_0, 0, 4;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55e76f4d8cf0_0, 0, 32;
T_0.14 ;
%load/vec4 v0x55e76f4d8cf0_0;
%cmpi/s 6, 0, 32;
%jmp/0xz T_0.15, 5;
%load/vec4 v0x55e76f534370_0;
%load/vec4 v0x55e76f4d8cf0_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.16, 4;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x55e76f534720_0, 0, 4;
T_0.16 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55e76f4d8cf0_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55e76f4d8cf0_0, 0, 32;
%jmp T_0.14;
T_0.15 ;
%jmp T_0.9;
T_0.7 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55e76f534510_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55e76f534290_0, 0, 32;
T_0.18 ;
%load/vec4 v0x55e76f534290_0;
%cmpi/s 6, 0, 32;
%jmp/0xz T_0.19, 5;
%load/vec4 v0x55e76f534370_0;
%load/vec4 v0x55e76f534290_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.20, 4;
%load/vec4 v0x55e76f534510_0;
%addi 1, 0, 32;
%store/vec4 v0x55e76f534510_0, 0, 32;
T_0.20 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55e76f534290_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55e76f534290_0, 0, 32;
%jmp T_0.18;
T_0.19 ;
%load/vec4 v0x55e76f534510_0;
%pushi/vec4 2, 0, 32;
%mod/s;
%cmpi/e 0, 0, 32;
%jmp/0xz T_0.22, 4;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x55e76f534720_0, 0, 4;
%jmp T_0.23;
T_0.22 ;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55e76f534720_0, 0, 4;
T_0.23 ;
%jmp T_0.9;
T_0.8 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55e76f534510_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55e76f534430_0, 0, 32;
T_0.24 ;
%load/vec4 v0x55e76f534430_0;
%cmpi/s 6, 0, 32;
%jmp/0xz T_0.25, 5;
%load/vec4 v0x55e76f534370_0;
%load/vec4 v0x55e76f534430_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.26, 4;
%load/vec4 v0x55e76f534510_0;
%addi 1, 0, 32;
%store/vec4 v0x55e76f534510_0, 0, 32;
T_0.26 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55e76f534430_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55e76f534430_0, 0, 32;
%jmp T_0.24;
T_0.25 ;
%load/vec4 v0x55e76f534510_0;
%pushi/vec4 2, 0, 32;
%mod/s;
%cmpi/e 0, 0, 32;
%jmp/0xz T_0.28, 4;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55e76f534720_0, 0, 4;
%jmp T_0.29;
T_0.28 ;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x55e76f534720_0, 0, 4;
T_0.29 ;
%jmp T_0.9;
T_0.9 ;
%pop/vec4 1;
%jmp T_0;
.thread T_0, $push;
.scope S_0x55e76f51ca80;
T_1 ;
%vpi_call 2 12 "$dumpfile", "bibp.vcd" {0 0 0};
%vpi_call 2 13 "$dumpvars" {0 0 0};
%pushi/vec4 9, 0, 9;
%store/vec4 v0x55e76f534860_0, 0, 9;
%delay 5, 0;
%pushi/vec4 97, 0, 9;
%store/vec4 v0x55e76f534860_0, 0, 9;
%delay 5, 0;
%pushi/vec4 165, 0, 9;
%store/vec4 v0x55e76f534860_0, 0, 9;
%delay 5, 0;
%pushi/vec4 227, 0, 9;
%store/vec4 v0x55e76f534860_0, 0, 9;
%delay 5, 0;
%pushi/vec4 319, 0, 9;
%store/vec4 v0x55e76f534860_0, 0, 9;
%delay 5, 0;
%pushi/vec4 289, 0, 9;
%store/vec4 v0x55e76f534860_0, 0, 9;
%delay 5, 0;
%pushi/vec4 353, 0, 9;
%store/vec4 v0x55e76f534860_0, 0, 9;
%delay 5, 0;
%pushi/vec4 417, 0, 9;
%store/vec4 v0x55e76f534860_0, 0, 9;
%delay 5, 0;
%pushi/vec4 481, 0, 9;
%store/vec4 v0x55e76f534860_0, 0, 9;
%delay 5, 0;
%end;
.thread T_1;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"bibpTB.v";
"bibp.v";

56
iverilog/tobb/lab6/bibp.v Normal file
View File

@ -0,0 +1,56 @@
module bibp #(parameter N = 3) (
input [(N*2)+2:0] buyruk,
output reg [N:0] sonuc
);
integer i, a, b, c, count;
always @(buyruk) begin
case (buyruk[(N*2)+2:N*2])
default: sonuc = {(N+1){1'b0}};
3'b000: sonuc = buyruk[(N*2)-1:(N*2)-3] + buyruk[(N*2)-4:0];
3'b001: sonuc = buyruk[(N*2)-1:(N*2)-3] - buyruk[(N*2)-4:0];
3'b010: sonuc = buyruk[(N*2)-1:(N*2)-3] & buyruk[(N*2)-4:0];
3'b011: sonuc = buyruk[(N*2)-1:(N*2)-3] | buyruk[(N*2)-4:0];
3'b100: begin
for (i = 0; i <= (N*2)-2; i++)
if (buyruk[i] == buyruk[i+1])
sonuc = {(N+1){1'b1}};
else
sonuc = {(N+1){1'b0}};
end
3'b101: begin
sonuc = {(N+1){1'b0}};
for (a = 0; a < (N*2); a++) begin
if (buyruk[a] == 1)
sonuc = {(N+1){1'b1}};
end
end
3'b110: begin
count = 0;
for (b = 0; b < (N*2); b++) begin
if (buyruk[b] == 1)
count = count + 1;
end
if (count % 2 == 0)
sonuc = {(N+1){1'b1}};
else
sonuc = {(N+1){1'b0}};
end
3'b111: begin
count = 0;
for (c = 0; c < (N*2); c++) begin
if (buyruk[c] == 1)
count = count + 1;
end
if (count % 2 == 0)
sonuc = {(N+1){1'b0}};
else
sonuc = {(N+1){1'b1}};
end
endcase
end
endmodule

81
iverilog/tobb/lab6/bibp.vcd Normal file
View File

@ -0,0 +1,81 @@
$date
Thu Jan 30 06:13:44 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module bibpTB $end
$var wire 4 ! sonuc [3:0] $end
$var reg 9 " A [8:0] $end
$scope module uut $end
$var wire 9 # buyruk [8:0] $end
$var reg 4 $ sonuc [3:0] $end
$var integer 32 % a [31:0] $end
$var integer 32 & b [31:0] $end
$var integer 32 ' c [31:0] $end
$var integer 32 ( count [31:0] $end
$var integer 32 ) i [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
bx )
bx (
bx '
bx &
bx %
b10 $
b1001 #
b1001 "
b10 !
$end
#5
b11 !
b11 $
b1100001 "
b1100001 #
#10
b100 !
b100 $
b10100101 "
b10100101 #
#15
b111 !
b111 $
b11100011 "
b11100011 #
#20
b1111 !
b1111 $
b101 )
b100111111 "
b100111111 #
#25
b0 !
b0 $
b101 )
b100100001 "
b100100001 #
#30
b1111 !
b1111 $
b110 %
b101100001 "
b101100001 #
#35
b110 &
b10 (
b110100001 "
b110100001 #
#40
b0 !
b0 $
b110 '
b10 (
b111100001 "
b111100001 #
#45

25
iverilog/tobb/lab6/bibpTB.v Normal file
View File

@ -0,0 +1,25 @@
module bibpTB();
parameter N = 3;
reg [(N*2)+2:0] A;
wire [N:0] sonuc;
bibp #(N) uut (
.buyruk(A),
.sonuc(sonuc)
);
initial begin
$dumpfile("bibp.vcd");
$dumpvars;
A = 9'b000_001_001; #5;
A = 9'b001_100_001; #5;
A = 9'b010_100_101; #5;
A = 9'b011_100_011; #5;
A = 9'b100_111_111; #5;
A = 9'b100_100_001; #5;
A = 9'b101_100_001; #5;
A = 9'b110_100_001; #5;
A = 9'b111_100_001; #5;
end
endmodule

341
iverilog/tobb/lab7/bib3A Normal file
View File

@ -0,0 +1,341 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55a2c2765ba0 .scope module, "bib3AdvancedTB" "bib3AdvancedTB" 2 1;
.timescale 0 0;
v0x55a2c2780cc0_0 .var "basla", 0 0;
v0x55a2c2780d80_0 .net "bitti", 0 0, v0x55a2c27805f0_0; 1 drivers
v0x55a2c2780e50_0 .var "buyruk", 8 0;
v0x55a2c2780f50_0 .var "clk", 0 0;
v0x55a2c2781020_0 .var/i "i", 31 0;
v0x55a2c27810c0 .array "memory", 15 0, 8 0;
v0x55a2c2781160_0 .net "sonuc", 3 0, v0x55a2c2780b40_0; 1 drivers
S_0x55a2c2765d30 .scope module, "uut" "bib3Advanced" 2 10, 3 1 0, S_0x55a2c2765ba0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "basla";
.port_info 2 /INPUT 9 "buyruk";
.port_info 3 /OUTPUT 4 "sonuc";
.port_info 4 /OUTPUT 1 "bitti";
v0x55a2c2723c00_0 .var/i "a", 31 0;
v0x55a2c2780470_0 .var/i "b", 31 0;
v0x55a2c2780550_0 .net "basla", 0 0, v0x55a2c2780cc0_0; 1 drivers
v0x55a2c27805f0_0 .var "bitti", 0 0;
v0x55a2c27806b0_0 .net "buyruk", 8 0, v0x55a2c2780e50_0; 1 drivers
v0x55a2c27807e0_0 .var/i "c", 31 0;
v0x55a2c27808c0_0 .net "clk", 0 0, v0x55a2c2780f50_0; 1 drivers
v0x55a2c2780980_0 .var/i "count", 31 0;
v0x55a2c2780a60_0 .var/i "i", 31 0;
v0x55a2c2780b40_0 .var "sonuc", 3 0;
E_0x55a2c275ba20 .event posedge, v0x55a2c27808c0_0;
.scope S_0x55a2c2765d30;
T_0 ;
%wait E_0x55a2c275ba20;
%load/vec4 v0x55a2c2780550_0;
%flag_set/vec4 8;
%jmp/0xz T_0.0, 8;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%load/vec4 v0x55a2c27806b0_0;
%parti/s 3, 6, 4;
%dup/vec4;
%pushi/vec4 0, 0, 3;
%cmp/u;
%jmp/1 T_0.3, 6;
%dup/vec4;
%pushi/vec4 1, 0, 3;
%cmp/u;
%jmp/1 T_0.4, 6;
%dup/vec4;
%pushi/vec4 2, 0, 3;
%cmp/u;
%jmp/1 T_0.5, 6;
%dup/vec4;
%pushi/vec4 3, 0, 3;
%cmp/u;
%jmp/1 T_0.6, 6;
%dup/vec4;
%pushi/vec4 4, 0, 3;
%cmp/u;
%jmp/1 T_0.7, 6;
%dup/vec4;
%pushi/vec4 5, 0, 3;
%cmp/u;
%jmp/1 T_0.8, 6;
%dup/vec4;
%pushi/vec4 6, 0, 3;
%cmp/u;
%jmp/1 T_0.9, 6;
%dup/vec4;
%pushi/vec4 7, 0, 3;
%cmp/u;
%jmp/1 T_0.10, 6;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
%jmp T_0.11;
T_0.3 ;
%load/vec4 v0x55a2c27806b0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55a2c27806b0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%add;
%assign/vec4 v0x55a2c2780b40_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%jmp T_0.11;
T_0.4 ;
%load/vec4 v0x55a2c27806b0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55a2c27806b0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%sub;
%assign/vec4 v0x55a2c2780b40_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%jmp T_0.11;
T_0.5 ;
%load/vec4 v0x55a2c27806b0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55a2c27806b0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%and;
%assign/vec4 v0x55a2c2780b40_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%jmp T_0.11;
T_0.6 ;
%load/vec4 v0x55a2c27806b0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55a2c27806b0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%or;
%assign/vec4 v0x55a2c2780b40_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%jmp T_0.11;
T_0.7 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55a2c2780a60_0, 0, 32;
T_0.12 ;
%load/vec4 v0x55a2c2780a60_0;
%cmpi/s 4, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.13, 5;
%load/vec4 v0x55a2c27806b0_0;
%load/vec4 v0x55a2c2780a60_0;
%part/s 1;
%load/vec4 v0x55a2c27806b0_0;
%load/vec4 v0x55a2c2780a60_0;
%addi 1, 0, 32;
%part/s 1;
%cmp/e;
%jmp/0xz T_0.14, 4;
%pushi/vec4 15, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
%jmp T_0.15;
T_0.14 ;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
T_0.15 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55a2c2780a60_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55a2c2780a60_0, 0, 32;
%jmp T_0.12;
T_0.13 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%jmp T_0.11;
T_0.8 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55a2c2723c00_0, 0, 32;
T_0.16 ;
%load/vec4 v0x55a2c2723c00_0;
%cmpi/s 5, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.17, 5;
%load/vec4 v0x55a2c27806b0_0;
%load/vec4 v0x55a2c2723c00_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.18, 4;
%pushi/vec4 15, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
%jmp T_0.19;
T_0.18 ;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
T_0.19 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55a2c2723c00_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55a2c2723c00_0, 0, 32;
%jmp T_0.16;
T_0.17 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%jmp T_0.11;
T_0.9 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55a2c2780980_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55a2c2780470_0, 0, 32;
T_0.20 ;
%load/vec4 v0x55a2c2780470_0;
%cmpi/s 5, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.21, 5;
%load/vec4 v0x55a2c27806b0_0;
%load/vec4 v0x55a2c2780470_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.22, 4;
%load/vec4 v0x55a2c2780980_0;
%addi 1, 0, 32;
%store/vec4 v0x55a2c2780980_0, 0, 32;
T_0.22 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55a2c2780470_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55a2c2780470_0, 0, 32;
%jmp T_0.20;
T_0.21 ;
%load/vec4 v0x55a2c2780980_0;
%pushi/vec4 2, 0, 32;
%mod/s;
%cmpi/e 0, 0, 32;
%jmp/0xz T_0.24, 4;
%pushi/vec4 15, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
%jmp T_0.25;
T_0.24 ;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
T_0.25 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%jmp T_0.11;
T_0.10 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55a2c2780980_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55a2c27807e0_0, 0, 32;
T_0.26 ;
%load/vec4 v0x55a2c27807e0_0;
%cmpi/s 5, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.27, 5;
%load/vec4 v0x55a2c27806b0_0;
%load/vec4 v0x55a2c27807e0_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.28, 4;
%load/vec4 v0x55a2c2780980_0;
%addi 1, 0, 32;
%store/vec4 v0x55a2c2780980_0, 0, 32;
T_0.28 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55a2c27807e0_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55a2c27807e0_0, 0, 32;
%jmp T_0.26;
T_0.27 ;
%load/vec4 v0x55a2c2780980_0;
%pushi/vec4 2, 0, 32;
%mod/s;
%cmpi/e 0, 0, 32;
%jmp/0xz T_0.30, 4;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
%jmp T_0.31;
T_0.30 ;
%pushi/vec4 15, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
T_0.31 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%jmp T_0.11;
T_0.11 ;
%pop/vec4 1;
%jmp T_0.1;
T_0.0 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x55a2c27805f0_0, 0;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x55a2c2780b40_0, 0;
T_0.1 ;
%jmp T_0;
.thread T_0;
.scope S_0x55a2c2765ba0;
T_1 ;
%load/vec4 v0x55a2c2780f50_0;
%inv;
%store/vec4 v0x55a2c2780f50_0, 0, 1;
%delay 5, 0;
%jmp T_1;
.thread T_1;
.scope S_0x55a2c2765ba0;
T_2 ;
%vpi_call 2 25 "$dumpfile", "bib3Advanced.vcd" {0 0 0};
%vpi_call 2 26 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a2c2780f50_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a2c2780cc0_0, 0, 1;
%pushi/vec4 0, 0, 9;
%store/vec4 v0x55a2c2780e50_0, 0, 9;
%vpi_call 2 28 "$readmemb", "memory.mem", v0x55a2c27810c0 {0 0 0};
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a2c2780cc0_0, 0, 1;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55a2c2781020_0, 0, 32;
T_2.0 ;
%load/vec4 v0x55a2c2781020_0;
%cmpi/s 16, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_2.1, 5;
%ix/getv/s 4, v0x55a2c2781020_0;
%load/vec4a v0x55a2c27810c0, 4;
%store/vec4 v0x55a2c2780e50_0, 0, 9;
%delay 10, 0;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x55a2c2781020_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x55a2c2781020_0, 0, 32;
%jmp T_2.0;
T_2.1 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a2c2780cc0_0, 0, 1;
%delay 10, 0;
%vpi_call 2 36 "$finish" {0 0 0};
%end;
.thread T_2;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"bib3AdvancedTB.v";
"bib3Advanced.v";

81
iverilog/tobb/lab7/bib3Advanced.v Normal file
View File

@ -0,0 +1,81 @@
// REWRITE !!
module bib3Advanced (
input clk,
input basla,
input [8:0] buyruk,
output reg [3:0] sonuc,
output reg bitti
);
integer i, a, b, c, count;
always@(posedge clk) begin
if(basla) begin
bitti <= 1'b0;
case (buyruk[8:6])
default: begin
sonuc <= 4'b0000;
end
3'b000: begin
sonuc <= buyruk[5:3] + buyruk[2:0];
bitti <= 1'b1;
end
3'b001: begin
sonuc <= buyruk[5:3] - buyruk[2:0];
bitti <= 1'b1;
end
3'b010: begin
sonuc <= buyruk[5:3] & buyruk[2:0];
bitti <= 1'b1;
end
3'b011: begin
sonuc <= buyruk[5:3] | buyruk[2:0];
bitti <= 1'b1;
end
3'b100: begin
for (i = 0; i <= 4; i++) begin
if (buyruk[i] == buyruk[i+1])
sonuc <= 4'b1111;
else
sonuc <= 4'b0000;
end
bitti <= 1'b1;
end
3'b101: begin
for (a = 0; a <= 5; a++) begin
if (buyruk[a] == 1)
sonuc <= 4'b1111;
else
sonuc <= 4'b0000;
end
bitti <= 1'b1;
end
3'b110: begin
count = 0;
for (b = 0; b <= 5; b++) begin
if (buyruk[b] == 1)
count = count + 1;
end
if (count % 2 == 0)
sonuc <= 4'b1111;
else
sonuc <= 4'b0000;
bitti <= 1'b1;
end
3'b111: begin
count = 0;
for (c = 0; c <= 5; c++)
if (buyruk[c] == 1)
count = count + 1;
if (count % 2 == 0)
sonuc <= 4'b0000;
else
sonuc <= 4'b1111;
bitti <= 1'b1;
end
endcase
end
else begin
bitti <= 1'b0;
sonuc <= 4'b0000;
end
end
endmodule

39
iverilog/tobb/lab7/bib3AdvancedTB.v Normal file
View File

@ -0,0 +1,39 @@
module bib3AdvancedTB();
reg clk;
reg basla;
reg [8:0] buyruk;
reg [8:0] memory [0:15];
wire [3:0] sonuc;
wire bitti;
bib3Advanced uut (
.clk(clk),
.basla(basla),
.buyruk(buyruk),
.sonuc(sonuc),
.bitti(bitti)
);
always begin
clk = ~clk; #5;
end
integer i;
initial begin
$dumpfile("bib3Advanced.vcd");
$dumpvars;
clk = 0; basla = 0; buyruk = 9'b0_0000_0000;
$readmemb("memory.mem", memory); #10;
basla = 1'b1;
for(i = 0; i <= 16; i++) begin
buyruk = memory[i]; #10;
end
basla = 1'b0; #10;
$finish;
end
endmodule

0
gowin/bttn/impl/pnr/bttn.timing_paths → iverilog/tobb/lab7/bib3_gelismis.v
View File

16
iverilog/tobb/lab7/memory.mem Normal file
View File

@ -0,0 +1,16 @@
000001001
001100001
010100101
011100011
100111111
100100001
101100001
110100001
111100001
000001001
001100001
010100101
011100011
100111111
100100001
101100001

12
iverilog/tobb/lab7/paramBib3Advanced.v Normal file
View File

@ -0,0 +1,12 @@
module paramBib3Advanced #(parameter N = 3) (
input clk,
input basla,
input [(N*2)+2:0] buyruk,
output reg [N:0] sonuc,
output reg bitti
);
genvar i;
generate
for (i = 0; i < N)
endgenerate

0
project0.2/selector.v → project0.2/!NOTUSE!selector.v
View File

32
project0.2/PU.v
View File

@ -1,32 +0,0 @@
module PU (
input A, // Dividend bit
input B, // Divisor bit
input Cin, // Carry input
input S, // Select input for the mux
output Y, // Output of the PU
output COut // Carry output from the full adder
);
wire Sum, notB;
// Invert B for subtraction
not n1 (notB, B);
// Full adder performs A - B + Cin
fulladder f1 (
.A(A),
.B(notB),
.Carry(Cin),
.Sum(Sum),
.CarryO(COut)
);
// 2:1 multiplexer to select between A and Sum
mux2 m1 (
.A0(A), // Input 0 of mux
.A1(Sum), // Input 1 of mux
.S(S), // Select line
.Y(Y) // Output of the mux
);
endmodule

9
project0.2/aluboard.v
View File

@ -1,9 +0,0 @@
module aluboard (
input [3:0] select,
input [7:0] Y,
input [3:0] A, B,
input [2:0] opCodeA,
output [7:0] sO
);
ALU alu0 ()

391
project0.2/divider4
View File

@ -1,391 +0,0 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55ec337fbbf0 .scope module, "divider4TB" "divider4TB" 2 1;
.timescale 0 0;
v0x55ec33821ff0_0 .var "Dividend", 3 0;
v0x55ec338220d0_0 .var "Divisor", 1 0;
v0x55ec33822170_0 .net "Quotient", 3 0, L_0x55ec338251a0; 1 drivers
v0x55ec33822240_0 .net "Remainder", 2 0, L_0x55ec33825510; 1 drivers
S_0x55ec337fa3a0 .scope module, "uut" "divider4" 2 12, 3 1 0, S_0x55ec337fbbf0;
.timescale 0 0;
.port_info 0 /INPUT 4 "Dividend";
.port_info 1 /INPUT 2 "Divisor";
.port_info 2 /OUTPUT 4 "Quotient";
.port_info 3 /OUTPUT 3 "Remainder";
L_0x55ec338251a0 .functor BUFZ 4, L_0x55ec338252b0, C4<0000>, C4<0000>, C4<0000>;
v0x55ec338218a0_0 .net "Carry", 3 0, L_0x55ec338253d0; 1 drivers
v0x55ec338219a0_0 .net "Dividend", 3 0, v0x55ec33821ff0_0; 1 drivers
v0x55ec33821a80_0 .net "Divisor", 1 0, v0x55ec338220d0_0; 1 drivers
v0x55ec33821b40_0 .net "Quotient", 3 0, L_0x55ec338251a0; alias, 1 drivers
v0x55ec33821c20_0 .net "Remainder", 2 0, L_0x55ec33825510; alias, 1 drivers
v0x55ec33821d50_0 .net "S0", 0 0, L_0x55ec33822310; 1 drivers
v0x55ec33821df0_0 .net "S1", 0 0, L_0x55ec338223e0; 1 drivers
v0x55ec33821e90_0 .net "Y", 3 0, L_0x55ec338252b0; 1 drivers
L_0x55ec33822310 .part L_0x55ec338253d0, 3, 1;
L_0x55ec338223e0 .part L_0x55ec338253d0, 2, 1;
L_0x55ec33822d50 .part v0x55ec33821ff0_0, 3, 1;
L_0x55ec33822e40 .part v0x55ec338220d0_0, 1, 1;
L_0x55ec338238c0 .part v0x55ec33821ff0_0, 2, 1;
L_0x55ec33823960 .part v0x55ec338220d0_0, 1, 1;
L_0x55ec33823a90 .part L_0x55ec338253d0, 3, 1;
L_0x55ec338243b0 .part v0x55ec33821ff0_0, 1, 1;
L_0x55ec33824530 .part v0x55ec338220d0_0, 0, 1;
L_0x55ec33824660 .part L_0x55ec338253d0, 2, 1;
L_0x55ec33825060 .part v0x55ec33821ff0_0, 0, 1;
L_0x55ec33825100 .part v0x55ec338220d0_0, 0, 1;
L_0x55ec33825210 .part L_0x55ec338253d0, 1, 1;
L_0x55ec338252b0 .concat8 [ 1 1 1 1], L_0x55ec33824ff0, L_0x55ec338242f0, L_0x55ec33823800, L_0x55ec33822c60;
L_0x55ec338253d0 .concat8 [ 1 1 1 1], L_0x55ec33824db0, L_0x55ec338240b0, L_0x55ec338235c0, L_0x55ec33822a20;
L_0x55ec33825510 .part L_0x55ec338253d0, 0, 3;
S_0x55ec337f9f60 .scope module, "PU1" "PU" 3 17, 4 1 0, S_0x55ec337fa3a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Cin";
.port_info 3 /INPUT 1 "S";
.port_info 4 /OUTPUT 1 "Y";
.port_info 5 /OUTPUT 1 "COut";
L_0x55ec33822480 .functor NOT 1, L_0x55ec33822e40, C4<0>, C4<0>, C4<0>;
v0x55ec33819cb0_0 .net "A", 0 0, L_0x55ec33822d50; 1 drivers
v0x55ec33819d70_0 .net "B", 0 0, L_0x55ec33822e40; 1 drivers
v0x55ec33819e30_0 .net "COut", 0 0, L_0x55ec33822a20; 1 drivers
L_0x7f82dfd33018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x55ec33819ed0_0 .net "Cin", 0 0, L_0x7f82dfd33018; 1 drivers
v0x55ec33819fc0_0 .net "S", 0 0, L_0x55ec33822310; alias, 1 drivers
v0x55ec3381a0b0_0 .net "Sum", 0 0, L_0x55ec33822870; 1 drivers
v0x55ec3381a150_0 .net "Y", 0 0, L_0x55ec33822c60; 1 drivers
v0x55ec3381a1f0_0 .net "notB", 0 0, L_0x55ec33822480; 1 drivers
S_0x55ec337f9a30 .scope module, "f1" "fulladder" 4 16, 5 1 0, S_0x55ec337f9f60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x55ec33822a20 .functor OR 1, L_0x55ec338224f0, L_0x55ec33822730, C4<0>, C4<0>;
v0x55ec33818dd0_0 .net "A", 0 0, L_0x55ec33822d50; alias, 1 drivers
v0x55ec33818e90_0 .net "B", 0 0, L_0x55ec33822480; alias, 1 drivers
v0x55ec33818f60_0 .net "Carry", 0 0, L_0x7f82dfd33018; alias, 1 drivers
v0x55ec33819060_0 .net "CarryO", 0 0, L_0x55ec33822a20; alias, 1 drivers
v0x55ec33819100_0 .net "Sum", 0 0, L_0x55ec33822870; alias, 1 drivers
v0x55ec338191f0_0 .net "and1", 0 0, L_0x55ec338224f0; 1 drivers
v0x55ec338192c0_0 .net "and2", 0 0, L_0x55ec33822730; 1 drivers
v0x55ec33819390_0 .net "xor1", 0 0, L_0x55ec338226a0; 1 drivers
S_0x55ec337f7800 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55ec337f9a30;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x55ec338224f0 .functor AND 1, L_0x55ec33822d50, L_0x55ec33822480, C4<1>, C4<1>;
L_0x55ec338226a0 .functor XOR 1, L_0x55ec33822d50, L_0x55ec33822480, C4<0>, C4<0>;
v0x55ec337f5bd0_0 .net "A", 0 0, L_0x55ec33822d50; alias, 1 drivers
v0x55ec337f7e00_0 .net "B", 0 0, L_0x55ec33822480; alias, 1 drivers
v0x55ec337f36f0_0 .net "Carry", 0 0, L_0x55ec338224f0; alias, 1 drivers
v0x55ec337f5980_0 .net "Sum", 0 0, L_0x55ec338226a0; alias, 1 drivers
S_0x55ec33818960 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55ec337f9a30;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x55ec33822730 .functor AND 1, L_0x55ec338226a0, L_0x7f82dfd33018, C4<1>, C4<1>;
L_0x55ec33822870 .functor XOR 1, L_0x55ec338226a0, L_0x7f82dfd33018, C4<0>, C4<0>;
v0x55ec337f7bb0_0 .net "A", 0 0, L_0x55ec338226a0; alias, 1 drivers
v0x55ec337f9de0_0 .net "B", 0 0, L_0x7f82dfd33018; alias, 1 drivers
v0x55ec33818b90_0 .net "Carry", 0 0, L_0x55ec33822730; alias, 1 drivers
v0x55ec33818c60_0 .net "Sum", 0 0, L_0x55ec33822870; alias, 1 drivers
S_0x55ec33819480 .scope module, "m1" "mux2" 4 25, 7 1 0, S_0x55ec337f9f60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A0";
.port_info 1 /INPUT 1 "A1";
.port_info 2 /INPUT 1 "S";
.port_info 3 /OUTPUT 1 "Y";
L_0x55ec33822ad0 .functor NOT 1, L_0x55ec33822310, C4<0>, C4<0>, C4<0>;
L_0x55ec33822b60 .functor AND 1, L_0x55ec33822870, L_0x55ec33822310, C4<1>, C4<1>;
L_0x55ec33822bf0 .functor AND 1, L_0x55ec33822ad0, L_0x55ec33822d50, C4<1>, C4<1>;
L_0x55ec33822c60 .functor OR 1, L_0x55ec33822b60, L_0x55ec33822bf0, C4<0>, C4<0>;
v0x55ec33819660_0 .net "A0", 0 0, L_0x55ec33822d50; alias, 1 drivers
v0x55ec33819750_0 .net "A1", 0 0, L_0x55ec33822870; alias, 1 drivers
v0x55ec33819860_0 .net "S", 0 0, L_0x55ec33822310; alias, 1 drivers
v0x55ec33819900_0 .net "Y", 0 0, L_0x55ec33822c60; alias, 1 drivers
v0x55ec338199a0_0 .net "and1", 0 0, L_0x55ec33822b60; 1 drivers
v0x55ec33819ab0_0 .net "and2", 0 0, L_0x55ec33822bf0; 1 drivers
v0x55ec33819b70_0 .net "notS", 0 0, L_0x55ec33822ad0; 1 drivers
S_0x55ec3381a320 .scope module, "PU2" "PU" 3 26, 4 1 0, S_0x55ec337fa3a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Cin";
.port_info 3 /INPUT 1 "S";
.port_info 4 /OUTPUT 1 "Y";
.port_info 5 /OUTPUT 1 "COut";
L_0x55ec33822fb0 .functor NOT 1, L_0x55ec33823960, C4<0>, C4<0>, C4<0>;
v0x55ec3381c350_0 .net "A", 0 0, L_0x55ec338238c0; 1 drivers
v0x55ec3381c410_0 .net "B", 0 0, L_0x55ec33823960; 1 drivers
v0x55ec3381c4d0_0 .net "COut", 0 0, L_0x55ec338235c0; 1 drivers
v0x55ec3381c570_0 .net "Cin", 0 0, L_0x55ec33823a90; 1 drivers
v0x55ec3381c660_0 .net "S", 0 0, L_0x55ec33822310; alias, 1 drivers
v0x55ec3381c750_0 .net "Sum", 0 0, L_0x55ec33823410; 1 drivers
v0x55ec3381c7f0_0 .net "Y", 0 0, L_0x55ec33823800; 1 drivers
v0x55ec3381c890_0 .net "notB", 0 0, L_0x55ec33822fb0; 1 drivers
S_0x55ec3381a5c0 .scope module, "f1" "fulladder" 4 16, 5 1 0, S_0x55ec3381a320;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x55ec338235c0 .functor OR 1, L_0x55ec33823020, L_0x55ec338232d0, C4<0>, C4<0>;
v0x55ec3381b3d0_0 .net "A", 0 0, L_0x55ec338238c0; alias, 1 drivers
v0x55ec3381b490_0 .net "B", 0 0, L_0x55ec33822fb0; alias, 1 drivers
v0x55ec3381b560_0 .net "Carry", 0 0, L_0x55ec33823a90; alias, 1 drivers
v0x55ec3381b660_0 .net "CarryO", 0 0, L_0x55ec338235c0; alias, 1 drivers
v0x55ec3381b700_0 .net "Sum", 0 0, L_0x55ec33823410; alias, 1 drivers
v0x55ec3381b7f0_0 .net "and1", 0 0, L_0x55ec33823020; 1 drivers
v0x55ec3381b8c0_0 .net "and2", 0 0, L_0x55ec338232d0; 1 drivers
v0x55ec3381b990_0 .net "xor1", 0 0, L_0x55ec33823240; 1 drivers
S_0x55ec3381a7a0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55ec3381a5c0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x55ec33823020 .functor AND 1, L_0x55ec338238c0, L_0x55ec33822fb0, C4<1>, C4<1>;
L_0x55ec33823240 .functor XOR 1, L_0x55ec338238c0, L_0x55ec33822fb0, C4<0>, C4<0>;
v0x55ec3381a9d0_0 .net "A", 0 0, L_0x55ec338238c0; alias, 1 drivers
v0x55ec3381aab0_0 .net "B", 0 0, L_0x55ec33822fb0; alias, 1 drivers
v0x55ec3381ab70_0 .net "Carry", 0 0, L_0x55ec33823020; alias, 1 drivers
v0x55ec3381ac40_0 .net "Sum", 0 0, L_0x55ec33823240; alias, 1 drivers
S_0x55ec3381adb0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55ec3381a5c0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x55ec338232d0 .functor AND 1, L_0x55ec33823240, L_0x55ec33823a90, C4<1>, C4<1>;
L_0x55ec33823410 .functor XOR 1, L_0x55ec33823240, L_0x55ec33823a90, C4<0>, C4<0>;
v0x55ec3381b020_0 .net "A", 0 0, L_0x55ec33823240; alias, 1 drivers
v0x55ec3381b0f0_0 .net "B", 0 0, L_0x55ec33823a90; alias, 1 drivers
v0x55ec3381b190_0 .net "Carry", 0 0, L_0x55ec338232d0; alias, 1 drivers
v0x55ec3381b260_0 .net "Sum", 0 0, L_0x55ec33823410; alias, 1 drivers
S_0x55ec3381ba80 .scope module, "m1" "mux2" 4 25, 7 1 0, S_0x55ec3381a320;
.timescale 0 0;
.port_info 0 /INPUT 1 "A0";
.port_info 1 /INPUT 1 "A1";
.port_info 2 /INPUT 1 "S";
.port_info 3 /OUTPUT 1 "Y";
L_0x55ec33823670 .functor NOT 1, L_0x55ec33822310, C4<0>, C4<0>, C4<0>;
L_0x55ec33823700 .functor AND 1, L_0x55ec33823410, L_0x55ec33822310, C4<1>, C4<1>;
L_0x55ec33823790 .functor AND 1, L_0x55ec33823670, L_0x55ec338238c0, C4<1>, C4<1>;
L_0x55ec33823800 .functor OR 1, L_0x55ec33823700, L_0x55ec33823790, C4<0>, C4<0>;
v0x55ec3381bcd0_0 .net "A0", 0 0, L_0x55ec338238c0; alias, 1 drivers
v0x55ec3381bdc0_0 .net "A1", 0 0, L_0x55ec33823410; alias, 1 drivers
v0x55ec3381bed0_0 .net "S", 0 0, L_0x55ec33822310; alias, 1 drivers
v0x55ec3381bfc0_0 .net "Y", 0 0, L_0x55ec33823800; alias, 1 drivers
v0x55ec3381c060_0 .net "and1", 0 0, L_0x55ec33823700; 1 drivers
v0x55ec3381c150_0 .net "and2", 0 0, L_0x55ec33823790; 1 drivers
v0x55ec3381c210_0 .net "notS", 0 0, L_0x55ec33823670; 1 drivers
S_0x55ec3381c9e0 .scope module, "PU3" "PU" 3 36, 4 1 0, S_0x55ec337fa3a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Cin";
.port_info 3 /INPUT 1 "S";
.port_info 4 /OUTPUT 1 "Y";
.port_info 5 /OUTPUT 1 "COut";
L_0x55ec33823b30 .functor NOT 1, L_0x55ec33824530, C4<0>, C4<0>, C4<0>;
v0x55ec3381ea80_0 .net "A", 0 0, L_0x55ec338243b0; 1 drivers
v0x55ec3381eb40_0 .net "B", 0 0, L_0x55ec33824530; 1 drivers
v0x55ec3381ec00_0 .net "COut", 0 0, L_0x55ec338240b0; 1 drivers
v0x55ec3381eca0_0 .net "Cin", 0 0, L_0x55ec33824660; 1 drivers
v0x55ec3381ed90_0 .net "S", 0 0, L_0x55ec338223e0; alias, 1 drivers
v0x55ec3381ee80_0 .net "Sum", 0 0, L_0x55ec33823f00; 1 drivers
v0x55ec3381ef20_0 .net "Y", 0 0, L_0x55ec338242f0; 1 drivers
v0x55ec3381efc0_0 .net "notB", 0 0, L_0x55ec33823b30; 1 drivers
S_0x55ec3381cc60 .scope module, "f1" "fulladder" 4 16, 5 1 0, S_0x55ec3381c9e0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x55ec338240b0 .functor OR 1, L_0x55ec33823ba0, L_0x55ec33823dc0, C4<0>, C4<0>;
v0x55ec3381db30_0 .net "A", 0 0, L_0x55ec338243b0; alias, 1 drivers
v0x55ec3381dbf0_0 .net "B", 0 0, L_0x55ec33823b30; alias, 1 drivers
v0x55ec3381dcc0_0 .net "Carry", 0 0, L_0x55ec33824660; alias, 1 drivers
v0x55ec3381ddc0_0 .net "CarryO", 0 0, L_0x55ec338240b0; alias, 1 drivers
v0x55ec3381de60_0 .net "Sum", 0 0, L_0x55ec33823f00; alias, 1 drivers
v0x55ec3381df50_0 .net "and1", 0 0, L_0x55ec33823ba0; 1 drivers
v0x55ec3381e020_0 .net "and2", 0 0, L_0x55ec33823dc0; 1 drivers
v0x55ec3381e0f0_0 .net "xor1", 0 0, L_0x55ec33823d30; 1 drivers
S_0x55ec3381cec0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55ec3381cc60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x55ec33823ba0 .functor AND 1, L_0x55ec338243b0, L_0x55ec33823b30, C4<1>, C4<1>;
L_0x55ec33823d30 .functor XOR 1, L_0x55ec338243b0, L_0x55ec33823b30, C4<0>, C4<0>;
v0x55ec3381d130_0 .net "A", 0 0, L_0x55ec338243b0; alias, 1 drivers
v0x55ec3381d210_0 .net "B", 0 0, L_0x55ec33823b30; alias, 1 drivers
v0x55ec3381d2d0_0 .net "Carry", 0 0, L_0x55ec33823ba0; alias, 1 drivers
v0x55ec3381d3a0_0 .net "Sum", 0 0, L_0x55ec33823d30; alias, 1 drivers
S_0x55ec3381d510 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55ec3381cc60;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x55ec33823dc0 .functor AND 1, L_0x55ec33823d30, L_0x55ec33824660, C4<1>, C4<1>;
L_0x55ec33823f00 .functor XOR 1, L_0x55ec33823d30, L_0x55ec33824660, C4<0>, C4<0>;
v0x55ec3381d780_0 .net "A", 0 0, L_0x55ec33823d30; alias, 1 drivers
v0x55ec3381d850_0 .net "B", 0 0, L_0x55ec33824660; alias, 1 drivers
v0x55ec3381d8f0_0 .net "Carry", 0 0, L_0x55ec33823dc0; alias, 1 drivers
v0x55ec3381d9c0_0 .net "Sum", 0 0, L_0x55ec33823f00; alias, 1 drivers
S_0x55ec3381e1e0 .scope module, "m1" "mux2" 4 25, 7 1 0, S_0x55ec3381c9e0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A0";
.port_info 1 /INPUT 1 "A1";
.port_info 2 /INPUT 1 "S";
.port_info 3 /OUTPUT 1 "Y";
L_0x55ec33824160 .functor NOT 1, L_0x55ec338223e0, C4<0>, C4<0>, C4<0>;
L_0x55ec338241f0 .functor AND 1, L_0x55ec33823f00, L_0x55ec338223e0, C4<1>, C4<1>;
L_0x55ec33824280 .functor AND 1, L_0x55ec33824160, L_0x55ec338243b0, C4<1>, C4<1>;
L_0x55ec338242f0 .functor OR 1, L_0x55ec338241f0, L_0x55ec33824280, C4<0>, C4<0>;
v0x55ec3381e430_0 .net "A0", 0 0, L_0x55ec338243b0; alias, 1 drivers
v0x55ec3381e520_0 .net "A1", 0 0, L_0x55ec33823f00; alias, 1 drivers
v0x55ec3381e630_0 .net "S", 0 0, L_0x55ec338223e0; alias, 1 drivers
v0x55ec3381e6d0_0 .net "Y", 0 0, L_0x55ec338242f0; alias, 1 drivers
v0x55ec3381e770_0 .net "and1", 0 0, L_0x55ec338241f0; 1 drivers
v0x55ec3381e880_0 .net "and2", 0 0, L_0x55ec33824280; 1 drivers
v0x55ec3381e940_0 .net "notS", 0 0, L_0x55ec33824160; 1 drivers
S_0x55ec3381f0f0 .scope module, "PU4" "PU" 3 45, 4 1 0, S_0x55ec337fa3a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Cin";
.port_info 3 /INPUT 1 "S";
.port_info 4 /OUTPUT 1 "Y";
.port_info 5 /OUTPUT 1 "COut";
L_0x55ec338247f0 .functor NOT 1, L_0x55ec33825100, C4<0>, C4<0>, C4<0>;
v0x55ec33821210_0 .net "A", 0 0, L_0x55ec33825060; 1 drivers
v0x55ec338212d0_0 .net "B", 0 0, L_0x55ec33825100; 1 drivers
v0x55ec33821390_0 .net "COut", 0 0, L_0x55ec33824db0; 1 drivers
v0x55ec33821430_0 .net "Cin", 0 0, L_0x55ec33825210; 1 drivers
v0x55ec33821520_0 .net "S", 0 0, L_0x55ec338223e0; alias, 1 drivers
v0x55ec33821610_0 .net "Sum", 0 0, L_0x55ec33824c00; 1 drivers
v0x55ec338216b0_0 .net "Y", 0 0, L_0x55ec33824ff0; 1 drivers
v0x55ec33821750_0 .net "notB", 0 0, L_0x55ec338247f0; 1 drivers
S_0x55ec3381f370 .scope module, "f1" "fulladder" 4 16, 5 1 0, S_0x55ec3381f0f0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x55ec33824db0 .functor OR 1, L_0x55ec33824860, L_0x55ec33824ac0, C4<0>, C4<0>;
v0x55ec33820290_0 .net "A", 0 0, L_0x55ec33825060; alias, 1 drivers
v0x55ec33820350_0 .net "B", 0 0, L_0x55ec338247f0; alias, 1 drivers
v0x55ec33820420_0 .net "Carry", 0 0, L_0x55ec33825210; alias, 1 drivers
v0x55ec33820520_0 .net "CarryO", 0 0, L_0x55ec33824db0; alias, 1 drivers
v0x55ec338205c0_0 .net "Sum", 0 0, L_0x55ec33824c00; alias, 1 drivers
v0x55ec338206b0_0 .net "and1", 0 0, L_0x55ec33824860; 1 drivers
v0x55ec33820780_0 .net "and2", 0 0, L_0x55ec33824ac0; 1 drivers
v0x55ec33820850_0 .net "xor1", 0 0, L_0x55ec33824a30; 1 drivers
S_0x55ec3381f5f0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55ec3381f370;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x55ec33824860 .functor AND 1, L_0x55ec33825060, L_0x55ec338247f0, C4<1>, C4<1>;
L_0x55ec33824a30 .functor XOR 1, L_0x55ec33825060, L_0x55ec338247f0, C4<0>, C4<0>;
v0x55ec3381f890_0 .net "A", 0 0, L_0x55ec33825060; alias, 1 drivers
v0x55ec3381f970_0 .net "B", 0 0, L_0x55ec338247f0; alias, 1 drivers
v0x55ec3381fa30_0 .net "Carry", 0 0, L_0x55ec33824860; alias, 1 drivers
v0x55ec3381fb00_0 .net "Sum", 0 0, L_0x55ec33824a30; alias, 1 drivers
S_0x55ec3381fc70 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55ec3381f370;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x55ec33824ac0 .functor AND 1, L_0x55ec33824a30, L_0x55ec33825210, C4<1>, C4<1>;
L_0x55ec33824c00 .functor XOR 1, L_0x55ec33824a30, L_0x55ec33825210, C4<0>, C4<0>;
v0x55ec3381fee0_0 .net "A", 0 0, L_0x55ec33824a30; alias, 1 drivers
v0x55ec3381ffb0_0 .net "B", 0 0, L_0x55ec33825210; alias, 1 drivers
v0x55ec33820050_0 .net "Carry", 0 0, L_0x55ec33824ac0; alias, 1 drivers
v0x55ec33820120_0 .net "Sum", 0 0, L_0x55ec33824c00; alias, 1 drivers
S_0x55ec33820940 .scope module, "m1" "mux2" 4 25, 7 1 0, S_0x55ec3381f0f0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A0";
.port_info 1 /INPUT 1 "A1";
.port_info 2 /INPUT 1 "S";
.port_info 3 /OUTPUT 1 "Y";
L_0x55ec33824e60 .functor NOT 1, L_0x55ec338223e0, C4<0>, C4<0>, C4<0>;
L_0x55ec33824ef0 .functor AND 1, L_0x55ec33824c00, L_0x55ec338223e0, C4<1>, C4<1>;
L_0x55ec33824f80 .functor AND 1, L_0x55ec33824e60, L_0x55ec33825060, C4<1>, C4<1>;
L_0x55ec33824ff0 .functor OR 1, L_0x55ec33824ef0, L_0x55ec33824f80, C4<0>, C4<0>;
v0x55ec33820b90_0 .net "A0", 0 0, L_0x55ec33825060; alias, 1 drivers
v0x55ec33820c80_0 .net "A1", 0 0, L_0x55ec33824c00; alias, 1 drivers
v0x55ec33820d90_0 .net "S", 0 0, L_0x55ec338223e0; alias, 1 drivers
v0x55ec33820e80_0 .net "Y", 0 0, L_0x55ec33824ff0; alias, 1 drivers
v0x55ec33820f20_0 .net "and1", 0 0, L_0x55ec33824ef0; 1 drivers
v0x55ec33821010_0 .net "and2", 0 0, L_0x55ec33824f80; 1 drivers
v0x55ec338210d0_0 .net "notS", 0 0, L_0x55ec33824e60; 1 drivers
.scope S_0x55ec337fbbf0;
T_0 ;
%vpi_call 2 21 "$monitor", "Time=%0t | Dividend=%b | Divisor=%b | Quotient=%b | Remainder=%b", $time, v0x55ec33821ff0_0, v0x55ec338220d0_0, v0x55ec33822170_0, v0x55ec33822240_0 {0 0 0};
%vpi_call 2 23 "$dumpfile", "divider4.vcd" {0 0 0};
%vpi_call 2 24 "$dumpvars" {0 0 0};
%pushi/vec4 8, 0, 4;
%store/vec4 v0x55ec33821ff0_0, 0, 4;
%pushi/vec4 2, 0, 2;
%store/vec4 v0x55ec338220d0_0, 0, 2;
%delay 10, 0;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x55ec33821ff0_0, 0, 4;
%pushi/vec4 3, 0, 2;
%store/vec4 v0x55ec338220d0_0, 0, 2;
%delay 10, 0;
%pushi/vec4 7, 0, 4;
%store/vec4 v0x55ec33821ff0_0, 0, 4;
%pushi/vec4 2, 0, 2;
%store/vec4 v0x55ec338220d0_0, 0, 2;
%delay 10, 0;
%pushi/vec4 9, 0, 4;
%store/vec4 v0x55ec33821ff0_0, 0, 4;
%pushi/vec4 3, 0, 2;
%store/vec4 v0x55ec338220d0_0, 0, 2;
%delay 10, 0;
%pushi/vec4 6, 0, 4;
%store/vec4 v0x55ec33821ff0_0, 0, 4;
%pushi/vec4 1, 0, 2;
%store/vec4 v0x55ec338220d0_0, 0, 2;
%delay 10, 0;
%pushi/vec4 10, 0, 4;
%store/vec4 v0x55ec33821ff0_0, 0, 4;
%pushi/vec4 0, 0, 2;
%store/vec4 v0x55ec338220d0_0, 0, 2;
%delay 10, 0;
%vpi_call 2 57 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 8;
"N/A";
"<interactive>";
"divider4TB.v";
"divider4.v";
"PU.v";
"fulladder.v";
"halfadder.v";
"mux2.v";

58
project0.2/divider4.v
View File

@ -1,58 +0,0 @@
module divider4 (
input [3:0] Dividend, // 4-bit dividend
input [1:0] Divisor, // 2-bit divisor
output [3:0] Quotient, // 4-bit quotient
output [2:0] Remainder // 3-bit remainder
);
wire [3:0] Carry; // Carry wires between PUs
wire [3:0] Y; // Intermediate PU outputs
wire S0, S1; // Select signals based on division logic
// Calculate select signals based on carry outputs
assign S0 = Carry[3]; // First select signal
assign S1 = Carry[2]; // Second select signal
// Row 1
PU PU1 (
.A(Dividend[3]),
.B(Divisor[1]),
.Cin(1'b0), // Initial carry input is 0
.S(S0),
.Y(Y[3]),
.COut(Carry[3])
);
PU PU2 (
.A(Dividend[2]),
.B(Divisor[1]),
.Cin(Carry[3]),
.S(S0),
.Y(Y[2]),
.COut(Carry[2])
);
// Row 2
PU PU3 (
.A(Dividend[1]),
.B(Divisor[0]),
.Cin(Carry[2]),
.S(S1),
.Y(Y[1]),
.COut(Carry[1])
);
PU PU4 (
.A(Dividend[0]),
.B(Divisor[0]),
.Cin(Carry[1]),
.S(S1),
.Y(Y[0]),
.COut(Carry[0])
);
// Assign outputs
assign Quotient = Y; // Output of the PUs is the quotient
assign Remainder = Carry; // Final carry values are the remainder
endmodule

457
project0.2/divider4.vcd
View File

@ -1,457 +0,0 @@
$date
Fri Dec 27 21:47:45 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module divider4TB $end
$var wire 3 ! Remainder [2:0] $end
$var wire 4 " Quotient [3:0] $end
$var reg 4 # Dividend [3:0] $end
$var reg 2 $ Divisor [1:0] $end
$scope module uut $end
$var wire 4 % Dividend [3:0] $end
$var wire 2 & Divisor [1:0] $end
$var wire 4 ' Quotient [3:0] $end
$var wire 4 ( Y [3:0] $end
$var wire 1 ) S1 $end
$var wire 1 * S0 $end
$var wire 3 + Remainder [2:0] $end
$var wire 4 , Carry [3:0] $end
$scope module PU1 $end
$var wire 1 - A $end
$var wire 1 . B $end
$var wire 1 / Cin $end
$var wire 1 * S $end
$var wire 1 0 notB $end
$var wire 1 1 Y $end
$var wire 1 2 Sum $end
$var wire 1 3 COut $end
$scope module f1 $end
$var wire 1 - A $end
$var wire 1 0 B $end
$var wire 1 / Carry $end
$var wire 1 3 CarryO $end
$var wire 1 4 xor1 $end
$var wire 1 5 and2 $end
$var wire 1 6 and1 $end
$var wire 1 2 Sum $end
$scope module h1 $end
$var wire 1 - A $end
$var wire 1 0 B $end
$var wire 1 6 Carry $end
$var wire 1 4 Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 4 A $end
$var wire 1 / B $end
$var wire 1 5 Carry $end
$var wire 1 2 Sum $end
$upscope $end
$upscope $end
$scope module m1 $end
$var wire 1 - A0 $end
$var wire 1 2 A1 $end
$var wire 1 * S $end
$var wire 1 1 Y $end
$var wire 1 7 and1 $end
$var wire 1 8 and2 $end
$var wire 1 9 notS $end
$upscope $end
$upscope $end
$scope module PU2 $end
$var wire 1 : A $end
$var wire 1 ; B $end
$var wire 1 < Cin $end
$var wire 1 * S $end
$var wire 1 = notB $end
$var wire 1 > Y $end
$var wire 1 ? Sum $end
$var wire 1 @ COut $end
$scope module f1 $end
$var wire 1 : A $end
$var wire 1 = B $end
$var wire 1 < Carry $end
$var wire 1 @ CarryO $end
$var wire 1 A xor1 $end
$var wire 1 B and2 $end
$var wire 1 C and1 $end
$var wire 1 ? Sum $end
$scope module h1 $end
$var wire 1 : A $end
$var wire 1 = B $end
$var wire 1 C Carry $end
$var wire 1 A Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 A A $end
$var wire 1 < B $end
$var wire 1 B Carry $end
$var wire 1 ? Sum $end
$upscope $end
$upscope $end
$scope module m1 $end
$var wire 1 : A0 $end
$var wire 1 ? A1 $end
$var wire 1 * S $end
$var wire 1 > Y $end
$var wire 1 D and1 $end
$var wire 1 E and2 $end
$var wire 1 F notS $end
$upscope $end
$upscope $end
$scope module PU3 $end
$var wire 1 G A $end
$var wire 1 H B $end
$var wire 1 I Cin $end
$var wire 1 ) S $end
$var wire 1 J notB $end
$var wire 1 K Y $end
$var wire 1 L Sum $end
$var wire 1 M COut $end
$scope module f1 $end
$var wire 1 G A $end
$var wire 1 J B $end
$var wire 1 I Carry $end
$var wire 1 M CarryO $end
$var wire 1 N xor1 $end
$var wire 1 O and2 $end
$var wire 1 P and1 $end
$var wire 1 L Sum $end
$scope module h1 $end
$var wire 1 G A $end
$var wire 1 J B $end
$var wire 1 P Carry $end
$var wire 1 N Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 N A $end
$var wire 1 I B $end
$var wire 1 O Carry $end
$var wire 1 L Sum $end
$upscope $end
$upscope $end
$scope module m1 $end
$var wire 1 G A0 $end
$var wire 1 L A1 $end
$var wire 1 ) S $end
$var wire 1 K Y $end
$var wire 1 Q and1 $end
$var wire 1 R and2 $end
$var wire 1 S notS $end
$upscope $end
$upscope $end
$scope module PU4 $end
$var wire 1 T A $end
$var wire 1 U B $end
$var wire 1 V Cin $end
$var wire 1 ) S $end
$var wire 1 W notB $end
$var wire 1 X Y $end
$var wire 1 Y Sum $end
$var wire 1 Z COut $end
$scope module f1 $end
$var wire 1 T A $end
$var wire 1 W B $end
$var wire 1 V Carry $end
$var wire 1 Z CarryO $end
$var wire 1 [ xor1 $end
$var wire 1 \ and2 $end
$var wire 1 ] and1 $end
$var wire 1 Y Sum $end
$scope module h1 $end
$var wire 1 T A $end
$var wire 1 W B $end
$var wire 1 ] Carry $end
$var wire 1 [ Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 [ A $end
$var wire 1 V B $end
$var wire 1 \ Carry $end
$var wire 1 Y Sum $end
$upscope $end
$upscope $end
$scope module m1 $end
$var wire 1 T A0 $end
$var wire 1 Y A1 $end
$var wire 1 ) S $end
$var wire 1 X Y $end
$var wire 1 ^ and1 $end
$var wire 1 _ and2 $end
$var wire 1 ` notS $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1`
0_
0^
0]
0\
1[
0Z
1Y
0X
1W
0V
0U
0T
1S
0R
0Q
0P
0O
1N
0M
1L
0K
1J
0I
0H
0G
1F
0E
0D
0C
0B
0A
0@
0?
0>
0=
0<
1;
0:
19
18
07
06
05
14
03
12
11
00
0/
1.
1-
b0 ,
b0 +
0*
0)
b1000 (
b1000 '
b10 &
b1000 %
b10 $
b1000 #
b1000 "
b0 !
$end
#10
0\
0V
b0 !
b0 +
1?
1>
0M
1L
1K
b0 ,
0Z
1Y
b1111 "
b1111 '
b1111 (
1X
0J
0W
1A
1E
0P
1N
1R
0]
1[
1_
1H
1U
1:
1G
1T
b11 $
b11 &
b1111 #
b1111 %
#20
1V
b11 !
b11 +
1M
0L
b11 ,
1Z
1Y
1P
0N
1]
0[
02
b111 "
b111 '
b111 (
01
1J
1W
04
08
0H
0U
0-
b10 $
b10 &
b111 #
b111 %
#30
0Z
b0 !
b0 +
0V
0]
1[
12
11
0?
0>
b0 ,
0M
0L
b1001 "
b1001 '
b1001 (
0K
0J
0W
14
18
0A
0E
0P
0N
0R
1H
1U
1-
0:
0G
b11 $
b11 &
b1001 #
b1001 %
#40
1^
1V
1M
1O
0S
0Q
0`
b110 !
b110 +
1I
1)
b110 ,
1@
1C
12
01
0?
1>
0L
0K
1Y
b101 "
b101 '
b101 (
1X
10
1=
14
08
0A
1E
1N
0R
0[
0_
0.
0;
0-
1:
1G
0T
b1 $
b1 &
b110 #
b110 %
#50
1Q
1L
1K
0R
0X
1Z
1B
09
0F
0D
0S
0`
0^
0O
1\
0Y
1<
1*
b111 !
b111 +
1I
1)
1P
0N
1[
13
02
01
b1111 ,
1@
0?
b10 "
b10 '
b10 (
0>
1J
1W
16
04
08
0C
1A
0E
0H
0U
1-
0:
b0 $
b0 &
b1010 #
b1010 %
#60

60
project0.2/divider4TB.v
View File

@ -1,60 +0,0 @@
module divider4TB;
// Inputs
reg [3:0] Dividend;
reg [1:0] Divisor;
// Outputs
wire [3:0] Quotient;
wire [2:0] Remainder;
// Instantiate the Unit Under Test (UUT)
divider4 uut (
.Dividend(Dividend),
.Divisor(Divisor),
.Quotient(Quotient),
.Remainder(Remainder)
);
initial begin
// Monitor output changes
$monitor("Time=%0t | Dividend=%b | Divisor=%b | Quotient=%b | Remainder=%b",
$time, Dividend, Divisor, Quotient, Remainder);
$dumpfile("divider4.vcd");
$dumpvars;
// Test Case 1: 8 / 2
Dividend = 4'b1000; // 8 in binary
Divisor = 2'b10; // 2 in binary
#10;
// Test Case 2: 15 / 3
Dividend = 4'b1111; // 15 in binary
Divisor = 2'b11; // 3 in binary
#10;
// Test Case 3: 7 / 2
Dividend = 4'b0111; // 7 in binary
Divisor = 2'b10; // 2 in binary
#10;
// Test Case 4: 9 / 3
Dividend = 4'b1001; // 9 in binary
Divisor = 2'b11; // 3 in binary
#10;
// Test Case 5: 6 / 1
Dividend = 4'b0110; // 6 in binary
Divisor = 2'b01; // 1 in binary
#10;
// Test Case 6: Division by 0 (should be undefined behavior)
Dividend = 4'b1010; // 10 in binary
Divisor = 2'b00; // Division by zero
#10;
// End simulation
$finish;
end
endmodule

16
project0.2/mux2.v
View File

@ -1,16 +0,0 @@
module mux2 (
input A0, A1,
input S,
output Y
);
wire notS, and1, and2;
not n1 (notS, S);
and an1 (and1, A1, S);
and an2 (and2, notS, A0);
or o1 (Y, and1, and2);
endmodule

300
project0.2/selector
View File

@ -1,300 +0,0 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55b89815f210 .scope module, "selectorTB" "selectorTB" 2 1;
.timescale 0 0;
v0x55b898185a70_0 .var "A", 3 0;
v0x55b898185b50_0 .var "B", 3 0;
v0x55b898185c20_0 .var "Y", 7 0;
v0x55b898185cf0_0 .var "opCodeA", 2 0;
v0x55b898185de0_0 .net "s0", 7 0, L_0x55b89818e810; 1 drivers
v0x55b898185e80_0 .var "select", 3 0;
S_0x55b898152b60 .scope module, "uut" "selector" 2 8, 3 1 0, S_0x55b89815f210;
.timescale 0 0;
.port_info 0 /INPUT 4 "select";
.port_info 1 /INPUT 8 "Y";
.port_info 2 /INPUT 4 "A";
.port_info 3 /INPUT 4 "B";
.port_info 4 /INPUT 3 "opCodeA";
.port_info 5 /OUTPUT 8 "s0";
L_0x55b898185f50 .functor AND 1, L_0x55b898186050, L_0x55b898186190, C4<1>, C4<1>;
L_0x55b8981862d0 .functor AND 1, L_0x55b898186340, L_0x55b898186430, C4<1>, C4<1>;
L_0x55b898186550 .functor AND 1, L_0x55b8981865c0, L_0x55b8981866b0, C4<1>, C4<1>;
L_0x55b8981868d0 .functor AND 1, L_0x55b8981869c0, L_0x55b898186b00, C4<1>, C4<1>;
L_0x55b898186bf0 .functor AND 1, L_0x55b898186c60, L_0x55b898186db0, C4<1>, C4<1>;
L_0x55b898186ea0 .functor AND 1, L_0x55b898186f50, L_0x55b8981870b0, C4<1>, C4<1>;
L_0x55b8981871a0 .functor AND 1, L_0x55b898187210, L_0x55b898187380, C4<1>, C4<1>;
L_0x55b898187040 .functor AND 1, L_0x55b8981876e0, L_0x55b8981877d0, C4<1>, C4<1>;
L_0x55b898187960 .functor AND 1, L_0x55b8981879d0, L_0x55b898187ac0, C4<1>, C4<1>;
L_0x55b898187c60 .functor AND 1, L_0x55b8981878c0, L_0x55b898187d60, C4<1>, C4<1>;
L_0x55b898187f60 .functor AND 1, L_0x55b898187fd0, L_0x55b8981880c0, C4<1>, C4<1>;
L_0x55b898188280 .functor AND 1, L_0x55b898188390, L_0x55b898188480, C4<1>, C4<1>;
L_0x55b898188650 .functor AND 1, L_0x55b8981886f0, L_0x55b898188790, C4<1>, C4<1>;
L_0x55b898188970 .functor AND 1, L_0x55b898188a90, L_0x55b898188b80, C4<1>, C4<1>;
L_0x55b898188320 .functor AND 1, L_0x55b898188da0, L_0x55b898188e90, C4<1>, C4<1>;
L_0x55b8981893b0 .functor AND 1, L_0x55b898189500, L_0x55b898189710, C4<1>, C4<1>;
L_0x55b898189800 .functor AND 1, L_0x55b898189870, L_0x55b898189a90, C4<1>, C4<1>;
L_0x55b898189bd0 .functor AND 1, L_0x55b898189ce0, L_0x55b898189f10, C4<1>, C4<1>;
L_0x55b89818a290 .functor AND 1, L_0x55b89818a350, L_0x55b89818a440, C4<1>, C4<1>;
L_0x55b89818a690 .functor OR 1, L_0x55b898189c40, L_0x55b89818a800, C4<0>, C4<0>;
L_0x55b89818aab0 .functor OR 1, L_0x55b89818ab20, L_0x55b89818ac10, C4<0>, C4<0>;
L_0x55b89818ae80 .functor OR 1, L_0x55b89818afb0, L_0x55b89818b0a0, C4<0>, C4<0>;
L_0x55b89818b4a0 .functor OR 1, L_0x55b89818b560, L_0x55b89818b7f0, C4<0>, C4<0>;
L_0x55b89818b8e0 .functor OR 1, L_0x55b89818ba20, L_0x55b89818bd10, C4<0>, C4<0>;
L_0x55b89818be50 .functor OR 1, L_0x55b89818bec0, L_0x55b89818c170, C4<0>, C4<0>;
L_0x55b89818c260 .functor OR 1, L_0x55b89818c3b0, L_0x55b89818c700, C4<0>, C4<0>;
L_0x7f2e051b7018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x55b89818cb50 .functor OR 1, L_0x55b89818cc10, L_0x7f2e051b7018, C4<0>, C4<0>;
L_0x55b89818cd50 .functor OR 1, L_0x55b89818ceb0, L_0x55b89818d1e0, C4<0>, C4<0>;
L_0x55b89818d320 .functor OR 1, L_0x55b89818d390, L_0x55b89818d680, C4<0>, C4<0>;
L_0x55b89818d770 .functor OR 1, L_0x55b89818d8e0, L_0x55b89818dc70, C4<0>, C4<0>;
L_0x55b89818dda0 .functor OR 1, L_0x55b89818de10, L_0x55b89818e0d0, C4<0>, C4<0>;
v0x55b89815cd40_0 .net "A", 3 0, v0x55b898185a70_0; 1 drivers
v0x55b89815c0d0_0 .net "B", 3 0, v0x55b898185b50_0; 1 drivers
o0x7f2e0544e078 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
v0x55b89815b460_0 .net "Y", 7 0, o0x7f2e0544e078; 0 drivers
v0x55b898142380_0 .net *"_ivl_0", 0 0, L_0x55b898185f50; 1 drivers
v0x55b89817f760_0 .net *"_ivl_102", 0 0, L_0x55b898189870; 1 drivers
v0x55b89817f890_0 .net *"_ivl_104", 0 0, L_0x55b898189a90; 1 drivers
v0x55b89817f970_0 .net *"_ivl_105", 0 0, L_0x55b898189bd0; 1 drivers
v0x55b89817fa50_0 .net *"_ivl_108", 0 0, L_0x55b898189ce0; 1 drivers
v0x55b89817fb30_0 .net *"_ivl_11", 0 0, L_0x55b898186430; 1 drivers
v0x55b89817fc10_0 .net *"_ivl_110", 0 0, L_0x55b898189f10; 1 drivers
v0x55b89817fcf0_0 .net *"_ivl_111", 0 0, L_0x55b89818a290; 1 drivers
v0x55b89817fdd0_0 .net *"_ivl_115", 0 0, L_0x55b89818a350; 1 drivers
v0x55b89817feb0_0 .net *"_ivl_117", 0 0, L_0x55b89818a440; 1 drivers
v0x55b89817ff90_0 .net *"_ivl_118", 0 0, L_0x55b89818a690; 1 drivers
v0x55b898180070_0 .net *"_ivl_12", 0 0, L_0x55b898186550; 1 drivers
v0x55b898180150_0 .net *"_ivl_121", 0 0, L_0x55b898189c40; 1 drivers
v0x55b898180230_0 .net *"_ivl_123", 0 0, L_0x55b89818a800; 1 drivers
v0x55b898180310_0 .net *"_ivl_124", 0 0, L_0x55b89818aab0; 1 drivers
v0x55b8981803f0_0 .net *"_ivl_127", 0 0, L_0x55b89818ab20; 1 drivers
v0x55b8981804d0_0 .net *"_ivl_129", 0 0, L_0x55b89818ac10; 1 drivers
v0x55b8981805b0_0 .net *"_ivl_130", 0 0, L_0x55b89818ae80; 1 drivers
v0x55b898180690_0 .net *"_ivl_133", 0 0, L_0x55b89818afb0; 1 drivers
v0x55b898180770_0 .net *"_ivl_135", 0 0, L_0x55b89818b0a0; 1 drivers
v0x55b898180850_0 .net *"_ivl_136", 0 0, L_0x55b89818b4a0; 1 drivers
v0x55b898180930_0 .net *"_ivl_140", 0 0, L_0x55b89818b560; 1 drivers
v0x55b898180a10_0 .net *"_ivl_142", 0 0, L_0x55b89818b7f0; 1 drivers
v0x55b898180af0_0 .net *"_ivl_143", 0 0, L_0x55b89818b8e0; 1 drivers
v0x55b898180bd0_0 .net *"_ivl_146", 0 0, L_0x55b89818ba20; 1 drivers
v0x55b898180cb0_0 .net *"_ivl_148", 0 0, L_0x55b89818bd10; 1 drivers
v0x55b898180d90_0 .net *"_ivl_149", 0 0, L_0x55b89818be50; 1 drivers
v0x55b898180e70_0 .net *"_ivl_15", 0 0, L_0x55b8981865c0; 1 drivers
v0x55b898180f50_0 .net *"_ivl_152", 0 0, L_0x55b89818bec0; 1 drivers
v0x55b898181030_0 .net *"_ivl_154", 0 0, L_0x55b89818c170; 1 drivers
v0x55b898181320_0 .net *"_ivl_155", 0 0, L_0x55b89818c260; 1 drivers
v0x55b898181400_0 .net *"_ivl_158", 0 0, L_0x55b89818c3b0; 1 drivers
v0x55b8981814e0_0 .net *"_ivl_160", 0 0, L_0x55b89818c700; 1 drivers
v0x55b8981815c0_0 .net *"_ivl_161", 0 0, L_0x55b89818cb50; 1 drivers
v0x55b8981816a0_0 .net *"_ivl_165", 0 0, L_0x55b89818cc10; 1 drivers
v0x55b898181780_0 .net/2u *"_ivl_166", 0 0, L_0x7f2e051b7018; 1 drivers
v0x55b898181860_0 .net *"_ivl_168", 0 0, L_0x55b89818cd50; 1 drivers
v0x55b898181940_0 .net *"_ivl_17", 0 0, L_0x55b8981866b0; 1 drivers
v0x55b898181a20_0 .net *"_ivl_171", 0 0, L_0x55b89818ceb0; 1 drivers
v0x55b898181b00_0 .net *"_ivl_173", 0 0, L_0x55b89818d1e0; 1 drivers
v0x55b898181be0_0 .net *"_ivl_174", 0 0, L_0x55b89818d320; 1 drivers
v0x55b898181cc0_0 .net *"_ivl_177", 0 0, L_0x55b89818d390; 1 drivers
v0x55b898181da0_0 .net *"_ivl_179", 0 0, L_0x55b89818d680; 1 drivers
v0x55b898181e80_0 .net *"_ivl_18", 0 0, L_0x55b8981868d0; 1 drivers
v0x55b898181f60_0 .net *"_ivl_180", 0 0, L_0x55b89818d770; 1 drivers
v0x55b898182040_0 .net *"_ivl_183", 0 0, L_0x55b89818d8e0; 1 drivers
v0x55b898182120_0 .net *"_ivl_185", 0 0, L_0x55b89818dc70; 1 drivers
v0x55b898182200_0 .net *"_ivl_186", 0 0, L_0x55b89818dda0; 1 drivers
v0x55b8981822e0_0 .net *"_ivl_189", 0 0, L_0x55b89818de10; 1 drivers
v0x55b8981823c0_0 .net *"_ivl_191", 0 0, L_0x55b89818e0d0; 1 drivers
v0x55b8981824a0_0 .net *"_ivl_195", 0 0, L_0x55b89818e1c0; 1 drivers
v0x55b898182580_0 .net *"_ivl_199", 0 0, L_0x55b89818e490; 1 drivers
v0x55b898182660_0 .net *"_ivl_203", 0 0, L_0x55b89818e530; 1 drivers
v0x55b898182740_0 .net *"_ivl_208", 0 0, L_0x55b89818eb80; 1 drivers
v0x55b898182820_0 .net *"_ivl_22", 0 0, L_0x55b8981869c0; 1 drivers
v0x55b898182900_0 .net *"_ivl_24", 0 0, L_0x55b898186b00; 1 drivers
v0x55b8981829e0_0 .net *"_ivl_25", 0 0, L_0x55b898186bf0; 1 drivers
v0x55b898182ac0_0 .net *"_ivl_28", 0 0, L_0x55b898186c60; 1 drivers
v0x55b898182ba0_0 .net *"_ivl_3", 0 0, L_0x55b898186050; 1 drivers
v0x55b898182c80_0 .net *"_ivl_30", 0 0, L_0x55b898186db0; 1 drivers
v0x55b898182d60_0 .net *"_ivl_31", 0 0, L_0x55b898186ea0; 1 drivers
v0x55b898182e40_0 .net *"_ivl_34", 0 0, L_0x55b898186f50; 1 drivers
v0x55b898183330_0 .net *"_ivl_36", 0 0, L_0x55b8981870b0; 1 drivers
v0x55b898183410_0 .net *"_ivl_37", 0 0, L_0x55b8981871a0; 1 drivers
v0x55b8981834f0_0 .net *"_ivl_40", 0 0, L_0x55b898187210; 1 drivers
v0x55b8981835d0_0 .net *"_ivl_42", 0 0, L_0x55b898187380; 1 drivers
v0x55b8981836b0_0 .net *"_ivl_43", 0 0, L_0x55b898187040; 1 drivers
v0x55b898183790_0 .net *"_ivl_47", 0 0, L_0x55b8981876e0; 1 drivers
v0x55b898183870_0 .net *"_ivl_49", 0 0, L_0x55b8981877d0; 1 drivers
v0x55b898183950_0 .net *"_ivl_5", 0 0, L_0x55b898186190; 1 drivers
v0x55b898183a30_0 .net *"_ivl_50", 0 0, L_0x55b898187960; 1 drivers
v0x55b898183b10_0 .net *"_ivl_53", 0 0, L_0x55b8981879d0; 1 drivers
v0x55b898183bf0_0 .net *"_ivl_55", 0 0, L_0x55b898187ac0; 1 drivers
v0x55b898183cd0_0 .net *"_ivl_56", 0 0, L_0x55b898187c60; 1 drivers
v0x55b898183db0_0 .net *"_ivl_59", 0 0, L_0x55b8981878c0; 1 drivers
v0x55b898183e90_0 .net *"_ivl_6", 0 0, L_0x55b8981862d0; 1 drivers
v0x55b898183f70_0 .net *"_ivl_61", 0 0, L_0x55b898187d60; 1 drivers
v0x55b898184050_0 .net *"_ivl_62", 0 0, L_0x55b898187f60; 1 drivers
v0x55b898184130_0 .net *"_ivl_65", 0 0, L_0x55b898187fd0; 1 drivers
v0x55b898184210_0 .net *"_ivl_67", 0 0, L_0x55b8981880c0; 1 drivers
v0x55b8981842f0_0 .net *"_ivl_68", 0 0, L_0x55b898188280; 1 drivers
v0x55b8981843d0_0 .net *"_ivl_71", 0 0, L_0x55b898188390; 1 drivers
v0x55b8981844b0_0 .net *"_ivl_73", 0 0, L_0x55b898188480; 1 drivers
v0x55b898184590_0 .net *"_ivl_74", 0 0, L_0x55b898188650; 1 drivers
v0x55b898184670_0 .net *"_ivl_77", 0 0, L_0x55b8981886f0; 1 drivers
v0x55b898184750_0 .net *"_ivl_79", 0 0, L_0x55b898188790; 1 drivers
v0x55b898184830_0 .net *"_ivl_80", 0 0, L_0x55b898188970; 1 drivers
v0x55b898184910_0 .net *"_ivl_83", 0 0, L_0x55b898188a90; 1 drivers
v0x55b8981849f0_0 .net *"_ivl_85", 0 0, L_0x55b898188b80; 1 drivers
v0x55b898184ad0_0 .net *"_ivl_86", 0 0, L_0x55b898188320; 1 drivers
v0x55b898184bb0_0 .net *"_ivl_89", 0 0, L_0x55b898188da0; 1 drivers
v0x55b898184c90_0 .net *"_ivl_9", 0 0, L_0x55b898186340; 1 drivers
v0x55b898184d70_0 .net *"_ivl_91", 0 0, L_0x55b898188e90; 1 drivers
v0x55b898184e50_0 .net *"_ivl_92", 0 0, L_0x55b8981893b0; 1 drivers
v0x55b898184f30_0 .net *"_ivl_96", 0 0, L_0x55b898189500; 1 drivers
v0x55b898185010_0 .net *"_ivl_98", 0 0, L_0x55b898189710; 1 drivers
v0x55b8981850f0_0 .net *"_ivl_99", 0 0, L_0x55b898189800; 1 drivers
v0x55b8981851d0_0 .net "a0", 3 0, L_0x55b898186790; 1 drivers
v0x55b8981852b0_0 .net "b0", 3 0, L_0x55b898187470; 1 drivers
v0x55b898185390_0 .net "op0", 2 0, L_0x55b89818a000; 1 drivers
v0x55b898185470_0 .net "opCodeA", 2 0, v0x55b898185cf0_0; 1 drivers
v0x55b898185550_0 .net "s0", 7 0, L_0x55b89818e810; alias, 1 drivers
v0x55b898185630_0 .net "select", 3 0, v0x55b898185e80_0; 1 drivers
v0x55b898185710_0 .net "tempAB", 3 0, L_0x55b89818b360; 1 drivers
v0x55b8981857f0_0 .net "tempYO", 3 0, L_0x55b89818c830; 1 drivers
v0x55b8981858d0_0 .net "y0", 7 0, L_0x55b898189090; 1 drivers
L_0x55b898186050 .part v0x55b898185e80_0, 0, 1;
L_0x55b898186190 .part v0x55b898185a70_0, 0, 1;
L_0x55b898186340 .part v0x55b898185e80_0, 0, 1;
L_0x55b898186430 .part v0x55b898185a70_0, 1, 1;
L_0x55b8981865c0 .part v0x55b898185e80_0, 0, 1;
L_0x55b8981866b0 .part v0x55b898185a70_0, 2, 1;
L_0x55b898186790 .concat8 [ 1 1 1 1], L_0x55b898185f50, L_0x55b8981862d0, L_0x55b898186550, L_0x55b8981868d0;
L_0x55b8981869c0 .part v0x55b898185e80_0, 0, 1;
L_0x55b898186b00 .part v0x55b898185a70_0, 3, 1;
L_0x55b898186c60 .part v0x55b898185e80_0, 1, 1;
L_0x55b898186db0 .part v0x55b898185b50_0, 0, 1;
L_0x55b898186f50 .part v0x55b898185e80_0, 1, 1;
L_0x55b8981870b0 .part v0x55b898185b50_0, 1, 1;
L_0x55b898187210 .part v0x55b898185e80_0, 1, 1;
L_0x55b898187380 .part v0x55b898185b50_0, 2, 1;
L_0x55b898187470 .concat8 [ 1 1 1 1], L_0x55b898186bf0, L_0x55b898186ea0, L_0x55b8981871a0, L_0x55b898187040;
L_0x55b8981876e0 .part v0x55b898185e80_0, 1, 1;
L_0x55b8981877d0 .part v0x55b898185b50_0, 3, 1;
L_0x55b8981879d0 .part v0x55b898185e80_0, 2, 1;
L_0x55b898187ac0 .part o0x7f2e0544e078, 0, 1;
L_0x55b8981878c0 .part v0x55b898185e80_0, 2, 1;
L_0x55b898187d60 .part o0x7f2e0544e078, 1, 1;
L_0x55b898187fd0 .part v0x55b898185e80_0, 2, 1;
L_0x55b8981880c0 .part o0x7f2e0544e078, 2, 1;
L_0x55b898188390 .part v0x55b898185e80_0, 2, 1;
L_0x55b898188480 .part o0x7f2e0544e078, 3, 1;
L_0x55b8981886f0 .part v0x55b898185e80_0, 2, 1;
L_0x55b898188790 .part o0x7f2e0544e078, 4, 1;
L_0x55b898188a90 .part v0x55b898185e80_0, 2, 1;
L_0x55b898188b80 .part o0x7f2e0544e078, 5, 1;
L_0x55b898188da0 .part v0x55b898185e80_0, 2, 1;
L_0x55b898188e90 .part o0x7f2e0544e078, 6, 1;
LS_0x55b898189090_0_0 .concat8 [ 1 1 1 1], L_0x55b898187960, L_0x55b898187c60, L_0x55b898187f60, L_0x55b898188280;
LS_0x55b898189090_0_4 .concat8 [ 1 1 1 1], L_0x55b898188650, L_0x55b898188970, L_0x55b898188320, L_0x55b8981893b0;
L_0x55b898189090 .concat8 [ 4 4 0 0], LS_0x55b898189090_0_0, LS_0x55b898189090_0_4;
L_0x55b898189500 .part v0x55b898185e80_0, 2, 1;
L_0x55b898189710 .part o0x7f2e0544e078, 7, 1;
L_0x55b898189870 .part v0x55b898185e80_0, 3, 1;
L_0x55b898189a90 .part v0x55b898185cf0_0, 0, 1;
L_0x55b898189ce0 .part v0x55b898185e80_0, 3, 1;
L_0x55b898189f10 .part v0x55b898185cf0_0, 1, 1;
L_0x55b89818a000 .concat8 [ 1 1 1 0], L_0x55b898189800, L_0x55b898189bd0, L_0x55b89818a290;
L_0x55b89818a350 .part v0x55b898185e80_0, 3, 1;
L_0x55b89818a440 .part v0x55b898185cf0_0, 2, 1;
L_0x55b898189c40 .part L_0x55b898186790, 0, 1;
L_0x55b89818a800 .part L_0x55b898187470, 0, 1;
L_0x55b89818ab20 .part L_0x55b898186790, 1, 1;
L_0x55b89818ac10 .part L_0x55b898187470, 1, 1;
L_0x55b89818afb0 .part L_0x55b898186790, 2, 1;
L_0x55b89818b0a0 .part L_0x55b898187470, 2, 1;
L_0x55b89818b360 .concat8 [ 1 1 1 1], L_0x55b89818a690, L_0x55b89818aab0, L_0x55b89818ae80, L_0x55b89818b4a0;
L_0x55b89818b560 .part L_0x55b898186790, 3, 1;
L_0x55b89818b7f0 .part L_0x55b898187470, 3, 1;
L_0x55b89818ba20 .part L_0x55b898189090, 0, 1;
L_0x55b89818bd10 .part L_0x55b89818a000, 0, 1;
L_0x55b89818bec0 .part L_0x55b898189090, 1, 1;
L_0x55b89818c170 .part L_0x55b89818a000, 1, 1;
L_0x55b89818c3b0 .part L_0x55b898189090, 2, 1;
L_0x55b89818c700 .part L_0x55b89818a000, 2, 1;
L_0x55b89818c830 .concat8 [ 1 1 1 1], L_0x55b89818b8e0, L_0x55b89818be50, L_0x55b89818c260, L_0x55b89818cb50;
L_0x55b89818cc10 .part L_0x55b898189090, 3, 1;
L_0x55b89818ceb0 .part L_0x55b89818b360, 0, 1;
L_0x55b89818d1e0 .part L_0x55b89818c830, 0, 1;
L_0x55b89818d390 .part L_0x55b89818b360, 1, 1;
L_0x55b89818d680 .part L_0x55b89818c830, 1, 1;
L_0x55b89818d8e0 .part L_0x55b89818b360, 2, 1;
L_0x55b89818dc70 .part L_0x55b89818c830, 2, 1;
L_0x55b89818de10 .part L_0x55b89818b360, 3, 1;
L_0x55b89818e0d0 .part L_0x55b89818c830, 3, 1;
L_0x55b89818e1c0 .part L_0x55b898189090, 4, 1;
L_0x55b89818e490 .part L_0x55b898189090, 5, 1;
L_0x55b89818e530 .part L_0x55b898189090, 6, 1;
LS_0x55b89818e810_0_0 .concat8 [ 1 1 1 1], L_0x55b89818cd50, L_0x55b89818d320, L_0x55b89818d770, L_0x55b89818dda0;
LS_0x55b89818e810_0_4 .concat8 [ 1 1 1 1], L_0x55b89818e1c0, L_0x55b89818e490, L_0x55b89818e530, L_0x55b89818eb80;
L_0x55b89818e810 .concat8 [ 4 4 0 0], LS_0x55b89818e810_0_0, LS_0x55b89818e810_0_4;
L_0x55b89818eb80 .part L_0x55b898189090, 7, 1;
.scope S_0x55b89815f210;
T_0 ;
%vpi_call 2 17 "$dumpfile", "selector.vcd" {0 0 0};
%vpi_call 2 18 "$dumpvars" {0 0 0};
%pushi/vec4 1, 0, 4;
%store/vec4 v0x55b898185a70_0, 0, 4;
%pushi/vec4 2, 0, 4;
%store/vec4 v0x55b898185b50_0, 0, 4;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b898185cf0_0, 0, 3;
%pushi/vec4 240, 0, 8;
%store/vec4 v0x55b898185c20_0, 0, 8;
%pushi/vec4 2, 0, 4;
%store/vec4 v0x55b898185e80_0, 0, 4;
%delay 5, 0;
%pushi/vec4 1, 0, 4;
%store/vec4 v0x55b898185a70_0, 0, 4;
%pushi/vec4 2, 0, 4;
%store/vec4 v0x55b898185b50_0, 0, 4;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b898185cf0_0, 0, 3;
%pushi/vec4 240, 0, 8;
%store/vec4 v0x55b898185c20_0, 0, 8;
%pushi/vec4 1, 0, 4;
%store/vec4 v0x55b898185e80_0, 0, 4;
%delay 5, 0;
%pushi/vec4 1, 0, 4;
%store/vec4 v0x55b898185a70_0, 0, 4;
%pushi/vec4 2, 0, 4;
%store/vec4 v0x55b898185b50_0, 0, 4;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b898185cf0_0, 0, 3;
%pushi/vec4 112, 0, 8;
%store/vec4 v0x55b898185c20_0, 0, 8;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x55b898185e80_0, 0, 4;
%delay 5, 0;
%pushi/vec4 1, 0, 4;
%store/vec4 v0x55b898185a70_0, 0, 4;
%pushi/vec4 2, 0, 4;
%store/vec4 v0x55b898185b50_0, 0, 4;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b898185cf0_0, 0, 3;
%pushi/vec4 112, 0, 8;
%store/vec4 v0x55b898185c20_0, 0, 8;
%pushi/vec4 8, 0, 4;
%store/vec4 v0x55b898185e80_0, 0, 4;
%delay 5, 0;
%vpi_call 2 23 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"selectorTB.v";
"selector.v";

80
project0.2/selector.vcd
View File

@ -1,80 +0,0 @@
$date
Wed Jan 8 01:16:47 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module selectorTB $end
$var wire 8 ! s0 [7:0] $end
$var reg 4 " A [3:0] $end
$var reg 4 # B [3:0] $end
$var reg 8 $ Y [7:0] $end
$var reg 3 % opCodeA [2:0] $end
$var reg 4 & select [3:0] $end
$scope module uut $end
$var wire 4 ' A [3:0] $end
$var wire 4 ( B [3:0] $end
$var wire 8 ) Y [7:0] $end
$var wire 3 * opCodeA [2:0] $end
$var wire 4 + select [3:0] $end
$var wire 8 , y0 [7:0] $end
$var wire 4 - tempYO [3:0] $end
$var wire 4 . tempAB [3:0] $end
$var wire 8 / s0 [7:0] $end
$var wire 3 0 op0 [2:0] $end
$var wire 4 1 b0 [3:0] $end
$var wire 4 2 a0 [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 2
b10 1
b0 0
b10 /
b10 .
b0 -
b0 ,
b10 +
b111 *
bz )
b10 (
b1 '
b10 &
b111 %
b11110000 $
b10 #
b1 "
b10 !
$end
#5
b1 !
b1 /
b1 .
b1 2
b0 1
b1 &
b1 +
#10
b0 .
bx -
bx !
bx /
b0 2
bx ,
b100 &
b100 +
b1110000 $
#15
b111 -
b111 !
b111 /
b0 ,
b111 0
b1000 &
b1000 +
#20

2220
tangTest/bttn
View File

File diff suppressed because it is too large Load Diff

10
tangTest/compile.sh Normal file
View File

@ -0,0 +1,10 @@
#!/bin/bash
# Granting execute permissions to this script (one-time setup)
# chmod +x script_name.sh
# Using Icarus Verilog to compile Verilog files for simulation
iverilog -o top top.v topTB.v ALU.v selector.v BinaryToBCD.v arithmeticUnit.v logicUnit.v multiplier.v opCode.v addition.v dabble.v subtraction.v fulladder.v fullsubtraction.v halfadder.v halfsubtraction.v
# Running the simulation
vvp top

2220
tangTest/top Normal file
View File

File diff suppressed because it is too large Load Diff

2
tangTest/bttn.v → tangTest/top.v
View File

@ -1,4 +1,4 @@
module bttn ( module top (
input [3:0] A, B, input [3:0] A, B,
input [2:0] opCodeA, input [2:0] opCodeA,
input [1:0] select, input [1:0] select,

4
tangTest/bttn.vcd → tangTest/top.vcd
View File

@ -1,5 +1,5 @@
$date $date
Mon Jan 20 01:37:42 2025 Thu Jan 23 05:37:04 2025
$end $end
$version $version
Icarus Verilog Icarus Verilog
@ -7,7 +7,7 @@ $end
$timescale $timescale
1s 1s
$end $end
$scope module bttnTB $end $scope module topTB $end
$var wire 2 ! led [1:0] $end $var wire 2 ! led [1:0] $end
$var wire 12 " Y [11:0] $end $var wire 12 " Y [11:0] $end
$var reg 4 # A [3:0] $end $var reg 4 # A [3:0] $end

6
tangTest/bttnTB.v → tangTest/topTB.v
View File

@ -1,4 +1,4 @@
module bttnTB(); module topTB();
reg [3:0] A,B; reg [3:0] A,B;
reg [2:0] opCodeA; reg [2:0] opCodeA;
@ -6,7 +6,7 @@ reg [1:0] select;
wire [1:0] led; wire [1:0] led;
wire [11:0] Y; wire [11:0] Y;
bttn uut ( top uut (
.A(A), .A(A),
.B(B), .B(B),
.opCodeA(opCodeA), .opCodeA(opCodeA),
@ -16,7 +16,7 @@ bttn uut (
); );
initial begin initial begin
$dumpfile("bttn.vcd"); $dumpfile("top.vcd");
$dumpvars; $dumpvars;
A = 4'b1111; B = 4'b1111; opCodeA = 3'b000; select = 2'b01; #5; A = 4'b1111; B = 4'b1111; opCodeA = 3'b000; select = 2'b01; #5;
A = 4'b0000; B = 4'b1111; opCodeA = 3'b001; select = 2'b01; #5; A = 4'b0000; B = 4'b1111; opCodeA = 3'b001; select = 2'b01; #5;