verilog

2024-04-13 05:48:55 +03:00
commit ed465dd690
61 changed files with 2719 additions and 0 deletions
--- a/lab3/impl/gwsynthesis/lab3.log
+++ b/lab3/impl/gwsynthesis/lab3.log
@@ -0,0 +1,23 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v'
+Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v'
+ERROR (EX3615) : '.name implicit port connection' is not allowed in this dialect, use SystemVerilog mode instead("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":7)
+ERROR (EX3863) : Syntax error near '['("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":7)
+ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
+ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
+ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
+ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
+ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
+ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
+ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
+ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
+ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
+ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
+ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
+ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
+ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
+ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
+ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
+Sorry, too many errors..
+GowinSynthesis finish
--- a/lab3/impl/gwsynthesis/lab3.prj
+++ b/lab3/impl/gwsynthesis/lab3.prj
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
+    <FileList>
+        <File path="C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v" type="verilog"/>
+        <File path="C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="0"/>
+        <Option type="global_freq" value="100.000"/>
+        <Option type="looplimit" value="2000"/>
+        <Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg"/>
+        <Option type="print_all_synthesis_warning" value="0"/>
+        <Option type="ram_rw_check" value="0"/>
+        <Option type="verilog_language" value="verilog-2001"/>
+        <Option type="vhdl_language" value="vhdl-1993"/>
+    </OptionList>
+</Project>
--- a/lab3/impl/gwsynthesis/lab3.vg
+++ b/lab3/impl/gwsynthesis/lab3.vg
@@ -0,0 +1,125 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Sat Apr 13 05:09:20 2024
+
+//Source file index table:
+//file0 "\C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v"
+`timescale 100 ps/100 ps
+module Adder3Bit (
+  num1,
+  num2,
+  Carry,
+  sum
+)
+;
+input [2:0] num1;
+input [2:0] num2;
+output [2:0] Carry;
+output [2:0] sum;
+wire [2:0] num1_d;
+wire [2:0] num2_d;
+wire [2:0] sum_d;
+wire [2:0] Carry_d;
+wire VCC;
+wire GND;
+  IBUF num1_0_ibuf (
+    .O(num1_d[0]),
+    .I(num1[0]) 
+);
+  IBUF num1_1_ibuf (
+    .O(num1_d[1]),
+    .I(num1[1]) 
+);
+  IBUF num1_2_ibuf (
+    .O(num1_d[2]),
+    .I(num1[2]) 
+);
+  IBUF num2_0_ibuf (
+    .O(num2_d[0]),
+    .I(num2[0]) 
+);
+  IBUF num2_1_ibuf (
+    .O(num2_d[1]),
+    .I(num2[1]) 
+);
+  IBUF num2_2_ibuf (
+    .O(num2_d[2]),
+    .I(num2[2]) 
+);
+  OBUF Carry_0_obuf (
+    .O(Carry[0]),
+    .I(Carry_d[0]) 
+);
+  OBUF Carry_1_obuf (
+    .O(Carry[1]),
+    .I(Carry_d[1]) 
+);
+  OBUF Carry_2_obuf (
+    .O(Carry[2]),
+    .I(Carry_d[2]) 
+);
+  OBUF sum_0_obuf (
+    .O(sum[0]),
+    .I(sum_d[0]) 
+);
+  OBUF sum_1_obuf (
+    .O(sum[1]),
+    .I(sum_d[1]) 
+);
+  OBUF sum_2_obuf (
+    .O(sum[2]),
+    .I(sum_d[2]) 
+);
+  LUT2 sum_d_0_s (
+    .F(sum_d[0]),
+    .I0(num1_d[0]),
+    .I1(num2_d[0]) 
+);
+defparam sum_d_0_s.INIT=4'h6;
+  LUT2 Carry_d_0_s (
+    .F(Carry_d[0]),
+    .I0(num1_d[0]),
+    .I1(num2_d[0]) 
+);
+defparam Carry_d_0_s.INIT=4'h8;
+  LUT4 Carry_d_1_s (
+    .F(Carry_d[1]),
+    .I0(num1_d[1]),
+    .I1(num2_d[1]),
+    .I2(num1_d[0]),
+    .I3(num2_d[0]) 
+);
+defparam Carry_d_1_s.INIT=16'hE888;
+  LUT3 sum_d_2_s (
+    .F(sum_d[2]),
+    .I0(Carry_d[1]),
+    .I1(num1_d[2]),
+    .I2(num2_d[2]) 
+);
+defparam sum_d_2_s.INIT=8'h96;
+  LUT3 Carry_d_2_s (
+    .F(Carry_d[2]),
+    .I0(Carry_d[1]),
+    .I1(num1_d[2]),
+    .I2(num2_d[2]) 
+);
+defparam Carry_d_2_s.INIT=8'hE8;
+  LUT4 sum_d_1_s0 (
+    .F(sum_d[1]),
+    .I0(num1_d[0]),
+    .I1(num2_d[0]),
+    .I2(num1_d[1]),
+    .I3(num2_d[1]) 
+);
+defparam sum_d_1_s0.INIT=16'h8778;
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* Adder3Bit */
--- a/lab3/impl/gwsynthesis/lab3_syn.rpt.html
+++ b/lab3/impl/gwsynthesis/lab3_syn.rpt.html
@@ -0,0 +1,175 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>synthesis Report</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
+div#main_wrapper{ width: 100%; }
+div#content { margin-left: 350px; margin-right: 30px; }
+div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
+div#catalog ul { list-style-type: none; }
+div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
+div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
+div#catalog a:visited { color: #0084ff; }
+div#catalog a:hover { color: #fff; background: #0084ff; }
+hr { margin-top: 30px; margin-bottom: 30px; }
+h1, h3 { text-align: center; }
+h1 {margin-top: 50px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { padding: 5px 5px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
+table.detail_table td.label { min-width: 100px; width: 8%;}
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="catalog_wrapper">
+<div id="catalog">
+<ul>
+<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
+<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
+<li><a href="#resource" style=" font-size: 16px;">Resource</a>
+<ul>
+<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
+<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
+</ul>
+</li>
+</ul>
+</div><!-- catalog -->
+</div><!-- catalog_wrapper -->
+<div id="content">
+<h1><a name="about">Synthesis Messages</a></h1>
+<table class="summary_table">
+<tr>
+<td class="label">Report Title</td>
+<td>GowinSynthesis Report</td>
+</tr>
+<tr>
+<td class="label">Design File</td>
+<td>C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v<br>
+</td>
+</tr>
+<tr>
+<td class="label">GowinSynthesis Constraints File</td>
+<td>---</td>
+</tr>
+<tr>
+<td class="label">Tool Version</td>
+<td>V1.9.9.02</td>
+</tr>
+<tr>
+<td class="label">Part Number</td>
+<td>GW2A-LV18PG256C8/I7</td>
+</tr>
+<tr>
+<td class="label">Device</td>
+<td>GW2A-18</td>
+</tr>
+<tr>
+<td class="label">Device Version</td>
+<td>C</td>
+</tr>
+<tr>
+<td class="label">Created Time</td>
+<td>Sat Apr 13 05:09:20 2024
+</td>
+</tr>
+<tr>
+<td class="label">Legal Announcement</td>
+<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
+</tr>
+</table>
+<h1><a name="summary">Synthesis Details</a></h1>
+<table class="summary_table">
+<tr>
+<td class="label">Top Level Module</td>
+<td>Adder3Bit</td>
+</tr>
+<tr>
+<td class="label">Synthesis Process</td>
+<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.093s, Peak memory usage = 156.254MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 156.254MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 156.254MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 156.254MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 156.254MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 156.254MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 156.254MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.301s, Peak memory usage = 172.207MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 172.207MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 172.207MB<br/></td>
+</tr>
+<tr>
+<td class="label">Total Time and Memory Usage</td>
+<td>CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.483s, Peak memory usage = 172.207MB</td>
+</tr>
+</table>
+<h1><a name="resource">Resource</a></h1>
+<h2><a name="usage">Resource Usage Summary</a></h2>
+<table class="summary_table">
+<tr>
+<td class="label"><b>Resource</b></td>
+<td><b>Usage</b></td>
+</tr>
+<tr>
+<td class="label"><b>I/O Port </b></td>
+<td>12</td>
+</tr>
+<tr>
+<td class="label"><b>I/O Buf </b></td>
+<td>12</td>
+</tr>
+<tr>
+<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
+<td>6</td>
+</tr>
+<tr>
+<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
+<td>6</td>
+</tr>
+<tr>
+<td class="label"><b>LUT </b></td>
+<td>6</td>
+</tr>
+<tr>
+<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
+<td>2</td>
+</tr>
+<tr>
+<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
+<td>2</td>
+</tr>
+<tr>
+<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
+<td>2</td>
+</tr>
+</table>
+<h2><a name="utilization">Resource Utilization Summary</a></h2>
+<table class="summary_table">
+<tr>
+<td class="label"><b>Resource</b></td>
+<td><b>Usage</b></td>
+<td><b>Utilization</b></td>
+</tr>
+<tr>
+<td class="label">Logic</td>
+<td>6(6 LUT, 0 ALU) / 20736</td>
+<td><1%</td>
+</tr>
+<tr>
+<td class="label">Register</td>
+<td>0 / 16173</td>
+<td>0%</td>
+</tr>
+<tr>
+<td class="label">&nbsp&nbsp--Register as Latch</td>
+<td>0 / 16173</td>
+<td>0%</td>
+</tr>
+<tr>
+<td class="label">&nbsp&nbsp--Register as FF</td>
+<td>0 / 16173</td>
+<td>0%</td>
+</tr>
+<tr>
+<td class="label">BSRAM</td>
+<td>0 / 46</td>
+<td>0%</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>
--- a/lab3/impl/gwsynthesis/lab3_syn_resource.html
+++ b/lab3/impl/gwsynthesis/lab3_syn_resource.html
@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">Adder3Bit (C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v)</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+<td align = "center">6</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>
--- a/lab3/impl/gwsynthesis/lab3_syn_rsc.xml
+++ b/lab3/impl/gwsynthesis/lab3_syn_rsc.xml
@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="Adder3Bit" Lut="6" T_Lut="6(6)"/>
--- a/lab3/impl/lab3_process_config.json
+++ b/lab3/impl/lab3_process_config.json
@@ -0,0 +1,88 @@
+{
+ "BACKGROUND_PROGRAMMING" : "off",
+ "COMPRESS" : false,
+ "CPU" : false,
+ "CRC_CHECK" : true,
+ "Clock_Route_Order" : 0,
+ "Correct_Hold_Violation" : true,
+ "DONE" : false,
+ "DOWNLOAD_SPEED" : "default",
+ "Disable_Insert_Pad" : false,
+ "ENABLE_CTP" : false,
+ "ENABLE_MERGE_MODE" : false,
+ "ENCRYPTION_KEY" : false,
+ "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
+ "ERROR_DECTION_AND_CORRECTION" : false,
+ "ERROR_DECTION_ONLY" : false,
+ "ERROR_INJECTION" : false,
+ "EXTERNAL_MASTER_CONFIG_CLOCK" : false,
+ "Enable_DSRM" : false,
+ "FORMAT" : "binary",
+ "FREQUENCY_DIVIDER" : "",
+ "Generate_Constraint_File_of_Ports" : false,
+ "Generate_IBIS_File" : false,
+ "Generate_Plain_Text_Timing_Report" : false,
+ "Generate_Post_PNR_Simulation_Model_File" : false,
+ "Generate_Post_Place_File" : false,
+ "Generate_SDF_File" : false,
+ "Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
+ "Global_Freq" : "default",
+ "GwSyn_Loop_Limit" : 2000,
+ "HOTBOOT" : false,
+ "I2C" : false,
+ "I2C_SLAVE_ADDR" : "00",
+ "IncludePath" : [
+
+ ],
+ "Incremental_Compile" : "",
+ "Initialize_Primitives" : false,
+ "JTAG" : false,
+ "MODE_IO" : false,
+ "MSPI" : false,
+ "MSPI_JUMP" : false,
+ "MULTIBOOT_ADDRESS_WIDTH" : "24",
+ "MULTIBOOT_MODE" : "Normal",
+ "MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
+ "MULTIJUMP_ADDRESS_WIDTH" : "24",
+ "MULTIJUMP_MODE" : "Normal",
+ "MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
+ "Multi_Boot" : true,
+ "OUTPUT_BASE_NAME" : "lab3",
+ "POWER_ON_RESET_MONITOR" : true,
+ "PRINT_BSRAM_VALUE" : true,
+ "PROGRAM_DONE_BYPASS" : false,
+ "PlaceInRegToIob" : true,
+ "PlaceIoRegToIob" : true,
+ "PlaceOutRegToIob" : true,
+ "Place_Option" : "0",
+ "Process_Configuration_Verion" : "1.0",
+ "Promote_Physical_Constraint_Warning_to_Error" : true,
+ "READY" : false,
+ "RECONFIG_N" : false,
+ "Ram_RW_Check" : false,
+ "Replicate_Resources" : false,
+ "Report_Auto-Placed_Io_Information" : false,
+ "Route_Maxfan" : 23,
+ "Route_Option" : "0",
+ "Run_Timing_Driven" : true,
+ "SECURE_MODE" : false,
+ "SECURITY_BIT" : true,
+ "SEU_HANDLER" : false,
+ "SEU_HANDLER_CHECKSUM" : false,
+ "SEU_HANDLER_MODE" : "auto",
+ "SSPI" : false,
+ "STOP_SEU_HANDLER" : false,
+ "Show_All_Warnings" : false,
+ "Synthesize_tool" : "GowinSyn",
+ "TclPre" : "",
+ "TopModule" : "",
+ "USERCODE" : "default",
+ "Unused_Pin" : "As_input_tri_stated_with_pull_up",
+ "VCCAUX" : 3.3,
+ "VCCX" : "3.3",
+ "VHDL_Standard" : "VHDL_Std_1993",
+ "Verilog_Standard" : "Vlg_Std_2001",
+ "WAKE_UP" : "0",
+ "show_all_warnings" : false,
+ "turn_off_bg" : false
+}
--- a/lab3/impl/temp/rtl_parser.result
+++ b/lab3/impl/temp/rtl_parser.result
@@ -0,0 +1,10 @@
+[
+ {
+  "InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
+  "InstLine" : 1,
+  "InstName" : "Adder3Bit",
+  "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
+  "ModuleLine" : 1,
+  "ModuleName" : "Adder3Bit"
+ }
+]
--- a/lab3/impl/temp/rtl_parser_arg.json
+++ b/lab3/impl/temp/rtl_parser_arg.json
@@ -0,0 +1,21 @@
+{
+ "Device" : "GW2A-18C",
+ "Files" : [
+  {
+   "Path" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
+   "Type" : "verilog"
+  },
+  {
+   "Path" : "C:/cygwin64/home/koray/verilog/lab3/src/tbAdder3Bit.v",
+   "Type" : "verilog"
+  }
+ ],
+ "IncludePath" : [
+
+ ],
+ "LoopLimit" : 2000,
+ "ResultFile" : "C:/cygwin64/home/koray/verilog/lab3/impl/temp/rtl_parser.result",
+ "Top" : "",
+ "VerilogStd" : "verilog_2001",
+ "VhdlStd" : "vhdl_93"
+}