verilog

lab3/impl/temp/rtl_parser.result

@@ -1,10 +1,54 @@
 [
  {
-  "InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
+  "InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
   "InstLine" : 1,
-  "InstName" : "Adder3Bit",
-  "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
+  "InstName" : "fullAdder",
+  "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
   "ModuleLine" : 1,
-  "ModuleName" : "Adder3Bit"
+  "ModuleName" : "fullAdder",
+  "SubInsts" : [
+   {
+    "InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
+    "InstLine" : 7,
+    "InstName" : "h0",
+    "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
+    "ModuleLine" : 1,
+    "ModuleName" : "halfAdder"
+   },
+   {
+    "InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
+    "InstLine" : 8,
+    "InstName" : "h1",
+    "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
+    "ModuleLine" : 1,
+    "ModuleName" : "halfAdder"
+   }
+  ]
+ },
+ {
+  "InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
+  "InstLine" : 1,
+  "InstName" : "mult2bit",
+  "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
+  "ModuleLine" : 1,
+  "ModuleName" : "mult2bit",
+  "SubInsts" : [
+   {
+    "InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
+    "InstLine" : 14,
+    "InstName" : "h0",
+    "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
+    "ModuleLine" : 1,
+    "ModuleName" : "halfAdder"
+   },
+   {
+    "InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
+    "InstLine" : 15,
+    "InstName" : "h1",
+    "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
+    "ModuleLine" : 1,
+    "ModuleName" : "halfAdder"
+   }
+  ]
  }
 ]

lab3/impl/temp/rtl_parser_arg.json

@@ -2,11 +2,15 @@
  "Device" : "GW2A-18C",
  "Files" : [
   {
-   "Path" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
+   "Path" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
    "Type" : "verilog"
   },
   {
-   "Path" : "C:/cygwin64/home/koray/verilog/lab3/src/tbAdder3Bit.v",
+   "Path" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
+   "Type" : "verilog"
+  },
+  {
+   "Path" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
    "Type" : "verilog"
   }
  ],