kaltinsoy/verilog
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verilog/spartanTest
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k0rrluna 3d71f7e69f fpga
2025-01-12 07:23:34 +03:00
..
addition.v
fpga
2025-01-12 07:23:34 +03:00
ALU.v
fpga
2025-01-12 07:23:34 +03:00
aluboard.v
fpga
2025-01-12 07:23:34 +03:00
ALUTB.v
fpga
2025-01-12 07:23:34 +03:00
arithmeticUnit.v
fpga
2025-01-12 07:23:34 +03:00
BinaryToBCD.v
fpga
2025-01-12 07:23:34 +03:00
BinaryToBCDTB.v
fpga
2025-01-12 07:23:34 +03:00
char_mem.v
fpga
2025-01-12 07:23:34 +03:00
dabble.v
fpga
2025-01-12 07:23:34 +03:00
data.jed
fpga
2025-01-12 07:23:34 +03:00
fulladder.v
fpga
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fullsubtraction.v
fpga
2025-01-12 07:23:34 +03:00
halfadder.v
fpga
2025-01-12 07:23:34 +03:00
halfsubtraction.v
fpga
2025-01-12 07:23:34 +03:00
lcd.v
fpga
2025-01-12 07:23:34 +03:00
logicUnit.v
fpga
2025-01-12 07:23:34 +03:00
logicUnitTB.v
fpga
2025-01-12 07:23:34 +03:00
multiplier.v
fpga
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multiplierTB.v
fpga
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opCode.v
fpga
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opCodeTB.v
fpga
2025-01-12 07:23:34 +03:00
selectorTB.v
fpga
2025-01-12 07:23:34 +03:00
spartan3e.ucf
fpga
2025-01-12 07:23:34 +03:00
subtraction.v
fpga
2025-01-12 07:23:34 +03:00
subtractionTB.v
fpga
2025-01-12 07:23:34 +03:00
switchRotary.v
fpga
2025-01-12 07:23:34 +03:00
top.v
fpga
2025-01-12 07:23:34 +03:00