62 lines
2.0 KiB
Verilog
62 lines
2.0 KiB
Verilog
module switchRotary(
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input clk, // Clock signal
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input [3:0] switches, // Slide switches SW3 to SW0
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input rot_a, rot_b, // Rotary encoder signals
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input rot_center, // Rotary encoder push button
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output reg [3:0] A = 0, // Value of A
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output reg [3:0] B = 0, // Value of B
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output reg [2:0] opCode = 0 // Value of opCode
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);
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// Internal signals for rotary encoder
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reg [1:0] rot_state = 2'b00;
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reg [1:0] rot_prev = 2'b00;
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// Selected register for modification
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reg [1:0] selected = 2'b00; // 0 = A, 1 = B, 2 = opCode
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// Debouncing for rotary center button
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reg [15:0] debounce_counter = 0;
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reg debounce_pressed = 0;
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// Update selected register on rotary center press
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always @(posedge clk) begin
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if (rot_center && !debounce_pressed) begin
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debounce_pressed <= 1;
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selected <= selected + 1;
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end
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if (!rot_center) begin
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debounce_pressed <= 0;
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end
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end
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// Handle rotary encoder signals
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always @(posedge clk) begin
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rot_prev <= rot_state;
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rot_state <= {rot_a, rot_b};
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// Detect clockwise or counterclockwise rotation
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if (rot_prev == 2'b01 && rot_state == 2'b11) begin
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case (selected)
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2'b00: if (A < 15) A <= A + 1;
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2'b01: if (B < 15) B <= B + 1;
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2'b10: if (opCode < 7) opCode <= opCode + 1;
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endcase
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end else if (rot_prev == 2'b11 && rot_state == 2'b01) begin
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case (selected)
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2'b00: if (A > 0) A <= A - 1;
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2'b01: if (B > 0) B <= B - 1;
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2'b10: if (opCode > 0) opCode <= opCode - 1;
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endcase
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end
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end
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// Update A, B, or opCode based on switches
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always @(posedge clk) begin
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case (switches)
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4'b0001: A <= switches[3:0];
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4'b0010: B <= switches[3:0];
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4'b1000: opCode <= switches[2:0];
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endcase
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end
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endmodule
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